DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/21/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I and Species 3 (claims 1-19 and newly added claim 21) in the reply filed on 02/05/2026 is acknowledged.
Claim 20 withdrawn and cancelled by applicant from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/05/2025.
Claims 5-6, 12, and 17 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant noted claims 5-6, 12, and 17 are included in the elected species, however, the limitation “a third via electrically coupling the first conductor and the second gate together” and “a third via electrically coupling the third conductor and the seventh gate together” is not shown in the selected Species 3 (figs. 3A-3E). Therefore, claims 5-6, 12, and 17 are withdrawn.
Drawings
The drawings are objected to because figs. 3B and 3E are inconsistent. Figure 3B shows 308b and 308e connected to 326a but figure 3E shows 308a and 308d connected to 332b. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-4, 7-11, 13-16, 18-19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US Publication 20220130968).
Regarding independent claim 1, Peng teaches an integrated circuit (fig. 2A, 200), comprising:
a first gate (204a) on a first level (PO);
a second gate (204a) on a second level below the first level, and being coupled to the first gate (paragraphs 0123 and 0363, “gate terminal of PMOS transistor P13-1 and a gate terminal of NMOS transistor N13-1 are coupled together”);
a third gate (204b) on the first level, and being separated from the first gate in a first direction (fig. 2A, see also paragraphs 0055-056);
a fourth gate (204b) on the second level, being separated from the second gate in the first direction (fig. 2A), and being coupled to the third gate (paragraphs 0123 and 0363, “gate terminal of PMOS transistor P13-2 and a gate terminal of NMOS transistor N13-2 are coupled together”); [[and]]
a first input pin (fig. 16C, 1680a) extending in a second direction different from the first direction (fig. 16C), being on a first metal layer (M1) above a front-side of a substrate, being coupled to at least the first gate (fig. 16C, coupled through via 1682a), and being configured to receive a first input signal (paragraph 0464); and
a first conductor (fig. 2A, 220a) extending in the first direction, being on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate (paragraph 0167), and the first conductor being coupled to at least the second gate and the fourth gate (fig. 2A),
wherein the first input pin is electrically coupled to the third gate by at least the first gate, the second gate or the fourth gate (fig. 13, IN1b corresponding to input pin 1680a coupled to third gate via first gate).
Peng does not explicitly teach “on a second level below the first level”, however, Peng discloses “other configurations, arrangements on other layout levels or quantities of gates in the set of gates 204 are within the scope of the present disclosure” (paragraph 0125).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the second and fourth gates of Peng on a second level different from the first level, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding dependent claims 2 and 14, Peng further teaches the integrated circuit of claim 1/claim 13, wherein the first input pin comprises:
a second conductor (fig. 16C, 1680a) extending in the second direction, being on the first metal layer, the second conductor being next to the first gate (fig. 16C, 1606a corresponding to first gate is next to 1680a).
Regarding dependent claim 3, Peng further teaches the integrated circuit of claim 2, further comprising:
a third conductor (fig. 16A, 1660a) extending in the first direction, being on a third metal layer (M0) above the front-side of the substrate, the third metal layer being different from the first metal layer and the second metal layer (figs. 2A and 16A), and the third conductor overlapping the first gate and the second gate (fig. 16A); and
a first via (fig. 16C, 1682a) electrically coupling the third conductor and the second conductor together, the first via being between the third conductor and the second conductor (paragraph 0465).
Regarding dependent claim 4, Peng further teaches the integrated circuit of claim 3, further comprising:
a second via (fig. 16A, 1672a) electrically coupling the third conductor and the first gate together, the second via being between the third conductor and the first gate (paragraph 0463).
Regarding dependent claim 7, Peng further teaches the integrated circuit of claim 1, further comprising:
a fifth gate (fig. 2A, 204d) on the first level, and being separated from the first gate and the third gate in the first direction (fig. 2A);
a sixth gate (204d) on the second level, being separated from the second gate and the fourth gate in the first direction (fig. 2A), and being coupled to the fifth gate (fig. 13, gate of P13-4 and N-13-4 corresponds to fifth and sixth gates, see also paragraphs 0123 and 0363, “gate terminal of PMOS transistor P13-4 and a gate terminal of NMOS transistor N13-4 are coupled together”); and
a second input pin (fig. 16C, 1680b) extending in the second direction, being on the first metal layer, being coupled to at least the fifth gate or the sixth gate (fig. 13, IN3b corresponds to 1680b), and being configured to receive a second input signal (paragraph 0464).
Peng does not explicitly teach “on a second level below the first level”, however, Peng discloses “other configurations, arrangements on other layout levels or quantities of gates in the set of gates 204 are within the scope of the present disclosure” (paragraph 0125).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the sixth gate of Peng on a second level different from the first level, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding dependent claim 8, Peng further teaches the integrated circuit of claim 7, wherein the second input pin comprises:
a second conductor (16C, 1680b) extending in the second direction, being on the first metal layer, the second conductor being between the fifth gate and the third gate (fig. 16C, 1604a corresponding to second gate is next to 1680b).
Regarding dependent claim 9, Peng further teaches the integrated circuit of claim 8, further comprising:
a third conductor (fig. 16A, 1660a) extending in the first direction, being on a third metal layer (M0) above the front-side of the substrate, the third metal layer being different from the first metal layer and the second metal layer (figs. 2A and 16A), and the third conductor overlapping the fifth gate and the sixth gate (fig. 16A).
Regarding dependent claim 10, Peng further teaches the integrated circuit of claim 9, further comprising:
a first via (fig. 16C, 1682a) electrically coupling the third conductor and the second conductor together, the first via being between the third conductor and the second conductor (paragraph 0465); and
a second via (fig. 16C, 1682c) electrically coupling the third conductor and the fifth gate together, the second via being between the third conductor and the fifth gate (paragraph 0465).
Regarding dependent claim 11, Peng further teaches the integrated circuit of claim 10, further comprising:
a seventh gate (fig. 2A, 204c) on the first level, and being between the fifth gate and the third gate in the first direction; and
an eighth gate (204c) on the second level, being between the sixth gate and the fourth gate in the first direction, and being coupled to the seventh gate (paragraphs 0123 and 0363, “gate terminal of PMOS transistor P13-3 and a gate terminal of NMOS transistor N13-3 are coupled together”).
Peng does not explicitly teach “on a second level below the first level”, however, Peng discloses “other configurations, arrangements on other layout levels or quantities of gates in the set of gates 204 are within the scope of the present disclosure” (paragraph 0125).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the eighth gate of Peng on a second level different from the first level, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding independent claim 13, Peng teaches an integrated circuit (fig. 13), comprising:
a first transistor stack (P13-1 and N13-1) on a substrate, the first transistor stack comprising:
a first transistor (P-13-1) of a first type, the first transistor including a first gate (fig. 14A, 1404b, see paragraph 0378) on a first level; and
a second transistor (fig. 13, N-13-1) of a second type different from the first type, and the second transistor including a second gate (fig. 14A, 1404b) on a second level below the first level;
a second transistor stack (P13-2 and N13-2) on the substrate, the second transistor stack comprising:
a third transistor (P-13-2) of the first type, the third transistor including a third gate (fig. 14A, 1404c) on the first level, and being separated from the first gate in a first direction (fig. 14A); and
a fourth transistor (N-13-2) of the second type, the fourth transistor including a fourth gate (fig. 14A, 1404c) on the second level, and being separated from the third gate in the first direction;
a first input pin (fig. 16C, 1680a) extending in a second direction, being on a first metal layer (M1) above a front-side of the substrate, and being coupled to the first transistor and the second transistor (fig. 13, IN1b corresponding to input pin 1680a coupled to first and second transistor); and
a first conductor (fig. 14C, 1420a) extending in the first direction, being on a second metal layer (BM1) below a back-side of the substrate opposite from the front-side of the substrate (paragraph 0167), and the first conductor being coupled to the third gate and the fourth gate (fig. 14C), wherein the first input pin is electrically coupled to the third gate from the back-side of the substrate (fig. 13, INb1 corresponding to input pin 1680a coupled to third gate, can be coupled from the back-side of the substrate per MPEP 2144.04).
Peng does not explicitly teach “on a second level below the first level”, however, Peng discloses “other configurations, arrangements on other layout levels or quantities of gates in the set of gates 204 are within the scope of the present disclosure” (paragraph 0125).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the second and fourth gates of Peng on a second level different from the first level, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding dependent claim 15, Peng further teaches the integrated circuit of claim 14, further comprising:
a third conductor (fig. 16A, 1660a) extending in the first direction, being on a third metal layer (M0) above the front-side of the substrate, the third metal layer being different from the first metal layer and the second metal layer (figs. 2A and 16A), the third conductor being overlapped by the second conductor (figs. 2A and 16A), and the third conductor overlapping the first gate and the second gate (fig. 16A).
Regarding dependent claim 16, Peng further teaches the integrated circuit of claim 15, further comprising:
a first via (fig. 16C, 1682a) electrically coupling the third conductor and the second conductor together, the first via being between the third conductor and the second conductor (paragraph 0465); and
a second via (fig. 16a, 1672a) electrically coupling the third conductor and the first gate together, the second via being between the third conductor and the first gate (paragraph 0463).
Regarding dependent claim 18, Peng further teaches the integrated circuit of claim 13, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are part of a NOR logic gate circuit (paragraph 0042).
Regarding dependent claim 19, Peng further teaches the integrated circuit of claim 13, wherein the first gate extends in the second direction, and overlaps the first conductor (fig. 2A);
the second gate extends in the second direction, and overlaps the first conductor (fig. 2A);
the third gate extends in the second direction, and overlaps the first conductor (fig. 2A); and
the fourth gate extends in the second direction, and overlaps the first conductor (fig. 2A).
Regarding independent claim 21, Peng teaches an integrated circuit (fig. 13), comprising:
a first transistor (P13-1) including a first gate (fig. 14A, 1404b, see paragraph 0378) on a first level;
a second transistor (fig. 13, P13-2) including a second gate (fig. 14A, 1404b) on a second level below the first level, and being coupled to the first gate (paragraph 0378);
a third transistor (fig. 13, P13-2) including a third gate (fig. 14A, 1404c) on the first level, and being separated from the first gate in a first direction (fig. 14A);
a fourth transistor (fig. 13, N-13-2) including a fourth gate (fig. 14A. 1404c) on the second level, being separated from the second gate in the first direction, and being coupled to the third gate (paragraph 0378);
a first conductor (fig. 16C, 1680a) extending in a second direction different from the first direction, being on a first metal layer (M1) above a front-side of a substrate, being coupled to at least the first gate (fig. 13, IN1b corresponding to input pin 1680a coupled to third gate via first gate), and being configured to receive a first input signal (paragraph 0464);
a second conductor (fig. 14C, 1420a) extending in the first direction, being on a second metal layer (BM1) below a back-side of the substrate opposite from the front-side of the substrate, and the second conductor being coupled to at least the second gate and the fourth gate (fig. 14C); and
a third conductor (fig. 16C, 1680b) extending in the second direction, being on the first metal layer, being separated from the first conductor in the first direction (fig. 16C), and being coupled to at least the third transistor;
wherein the first conductor is electrically coupled to the third gate by at least the first gate, the second gate or the fourth gate (fig. 13, IN1b corresponding to first conductor 1680a coupled to third gate via first gate).
Peng does not explicitly teach “on a second level below the first level”, however, Peng discloses “other configurations, arrangements on other layout levels or quantities of gates in the set of gates 204 are within the scope of the present disclosure” (paragraph 0125).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the second and fourth gates of Peng on a second level different from the first level, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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