The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
1. Figure 7 does not include reference sign 76 of the spacer layer.
2. Reference sign 88 is not directed to a specific layer. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: Paragraph [0055] of the publication recites that “third spacer layer 76” is also identified as “the second and third field plates 74, 76”. A dielectric layer cannot be identified as a conductive layer.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 15 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the elected embodiment of figure 7 for the claimed limitation of “the spacer layer extends between the gate and the field plate”, as recited in claim 15.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-20 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “a second distance on the active region that is greater than the first distance”, as recited in claim 17 is unclear as to which element is greater than the first distance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, 21 and 24-25 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Fujishima et al. (2002/0145172).Regarding claim 1, Fujishima et al. teach in figure 20 and related text a transistor, comprising:
an active region comprising a channel layer 2;
a source electrode 11 and a drain electrode 12 in electrical contact with the active region;
a gate 9 between the source and drain electrodes and on the active region;
a field plate FP1 on the gate and is electrically connected to the gate; and
a spacer layer 10 between the field plate and the active region,
wherein a first portion of the field plate extends a first distance on the spacer layer from a first vertical edge of the gate toward the drain electrode, and
wherein a second portion of the field plate extends a second distance on the spacer layer from a second vertical edge of the gate opposite the first vertical edge toward the source electrode.
Fujishima et al. do not explicitly state that the first distance is greater than the second distance.
Fujishima et al. teach throughout the specification the importance of having specific distances and length of extensions of the field plates. The specific distances and length of extensions of the field plates are obtained by using routine experimentations.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first distance greater than the second distance, in Fujishima et al.’s device in order to improve the device characteristics by using conventional routine experimentations.
It is to be presumed also that skilled workers would as a matter of course, if they do not immediately obtain desired results, make certain experiments and adaptations, within the skill of the competent worker. The failures of experimenters who have no interest in succeeding should not be accorded great weight. In re Michalek, 162 F.2d 229, 232 (CCPA 1947); In re Reid, 179 F.2d 998, 1002 (CCPA 1950).
It is noted that a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 2, Fujishima et al. teach in figure 20 and related text the that field plate is a first field plate FP1,
wherein the transistor further comprises a second field plate FP2 that overlaps the first field plate, and
wherein the second field plate is electrically connected to the source electrode or the gate.
Regarding claim 3, Fujishima et al. teach in figure 20 and related text that the field plate FP1 is integral with the gate 9, and wherein the gate is in electrical contact with the active region.
Regarding claim 5, Fujishima et al. teach in figure 20 and related text that the second field plate FP2 is electrically connected to the source electrode 11 by a conductive path h1 that extends beyond a vertical projection of the active region (since the active region is located under gate 9), and
wherein the second field plate and the source electrode comprise a same metal material.
Regarding claim 7, Fujishima et al. teach in figure 20 and related text that the spacer layer 10 extends on opposing side surfaces of the gate and, wherein the spacer layer is between the first portion of the field plate and the active region, and between the second portion of the field plate and the active region.
Regarding claim 21, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first distance in a range from 0.2 to 5.0 microns, and wherein the second distance is in a range from 0.1 to 2.0 microns, in prior art’s device in order to adjust and optimize the device characteristics.
Regarding claim 24, Fujishima et al. teach in figure 20 and related text that the spacer layer is a first spacer layer 10, wherein the transistor further comprises a second spacer layer 25 between the first field plate FP1 and the second field plate FP2, wherein the second field plate FP2 extends a third distance on the second spacer layer from a vertical projection of the first vertical edge of the gate 9 toward the drain electrode, and wherein the third distance is greater than the first distance.
Regarding claim 25, Fujishima et al. teach in figure 18 and related text that, in a cross-sectional view, the second field plate (second field plate FP2 located to the left of via h1) is free of overlap with the second portion of the first field plate FP1 in a direction perpendicular to an upper surface of the active region.
Claims 8-9 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Fujishima et al. (2002/0145172) in view of Inokuchi et al. (6,294,801).Regarding claim 8, Fujishima et al. teach in figure 20 and related text substantially the entire claimed structure, as applied to claim 1 above, except at least a portion of the gate is in the active region.
Inokuchi et al. teach in figure 1 and related text that at least a portion of the gate 152 is in the active region.
Inokuchi et al. and Fujishima et al. are analogous art because they are directed to devices comprising field plates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fujishima et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form at least a portion of the gate in the active region, as taught by Inokuchi et al., in Fujishima et al.’s device in order to improve the device characteristics.
Regarding claims 9, when modifying Fujishima et al.’s device in view of Inokuchi et al., then the combined device comprises a buffer layer 104 (see figure 1 of Inokuchi et al.) and a barrier layer on a substrate 102, wherein the channel layer 112 is at a heterointerface between the buffer layer and the barrier layer, and wherein at least the portion of the gate 152 is in the barrier layer and is in electrical contact with the barrier layer.
Claims 14-16 and 26-27 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Inokuchi et al. (6,294,801) in view of Saito et al. (7,075,125).Regarding claim 14, Inokuchi et al. teach in figure 1 and related text a transistor, comprising:
an active region comprising a channel layer 112, the channel layer comprising a two dimensional electron gas (2DEG) region;
a source electrode 124 and a drain electrode 126 in electrical contact with the active region;
gate 150 (the bottom part) between the source and drain electrodes and on the active region;
a field plate (the top horizontal part of element 150) on the gate and electrically connected to the source electrode or the gate; and
wherein the date extends into the active region and is spaced apart from the channel laver 112.
Inokuchi et al. do not explicitly state using the top part of the gate as a field plate on the gate and electrically connected to the source electrode or the gate; and a spacer layer that extends between the source and drain electrodes on the active region.
Saito et al. teach in figure 4 and related text using the top part of the gate 17X as a field plate on the gate 13 and a spacer layer 19 that extends between the source and drain electrodes on the active region.
Inokuchi et al. and Saito et al. are analogous art because they are directed to devices comprising field plates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Inokuchi et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a field plate on the gate and electrically connected to the source electrode or the gate and a spacer layer that extends between the source and drain electrodes on the active region, as taught by Saito et al., in Inokuchi et al.’s device in order to improve the device electrical characteristics and in order to provide better protection to the device, respectively.
Regarding claim 15, Saito et al., and thus the combined device, teach in figure 4 and related text that the spacer layer 19 extends between the gate and the field plate 18X, and wherein the field plate comprises a conductive material.
Regarding claim 16, Saito et al., and thus the combined device, teach in figure 4 and related text that the field plate is electrically connected to the source electrode or the gate by a conductive path that extends beyond a vertical projection of the active region since the active region.
Regarding claim 26, Inokuchi et al. teach in figure 1 and related text that the gate comprises a first portion in the active region 118 and a second portion on top of the active region.
Regarding claim 27, Inokuchi et al. teach in figure 1 and related text that a width of the first portion (the portion inside layer 118) of the gate is substantially equal to a width of the second portion (the portion inside layer 120) of the gate.
Claims 17, 19-20 and 22-23 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tihanyi (6,445,038) in view of Saito et al. (6,940,090).Regarding claim 17, Tihanyi teaches in figure 4 and related text a transistor comprising
an active region comprising a channel layer (located inside element 2),
a source electrode 7 and a drain electrode 7 in electrical contact with the active region;
a gate 6 between the source and drain electrodes and on the active region;
a first field plate 12 on the gate and electrically connected to the source electrode or the gate;
a first spacer layer 1 on the active region, the first spacer layer comprising a first portion between the gate and the drain electrode and a second portion between the gate and the source electrode;
a second spacer layer (another portion of element 1) on the first field plate 12; and
a second field plate 12 (the top element 12) on the second spacer layer wherein the first field plate extends on the second portion of the first spacer layer, and
wherein, in across-sectional view, the first field plate 12 is laterally spaced apart from the source electrode by a first distance on the active region, and the second field plate (the top element 12) is laterally spaced apart from the source electrode by a second distance on the active region that is greater than the first distance.
Tihanyi does not teach that the channel layer comprising a two dimensional electron gas (2DEG) region.
Saito et al. teach in figure 21 and related text a channel layer comprising a two dimensional electron gas (2DEG) region.
Saito et al. and Tihanyi are analogous art because they are directed to devices comprising field plates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tihanyi because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use Tihanyi’s device in a channel layer comprising a two dimensional electron gas (2DEG) region, as taught by Saito et al., in order to expand the device capabilities.
The combination is motivated by the teaching of Saito et al. who point out that a channel region of a MOSFET can be used as a channel layer comprising a two dimensional electron gas (2DEG) region.
Regarding claim 19, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use the second field plate to extends from a vertical edge of the gate toward the drain electrode by a distance that is in a range from 0.2 to 5.0 microns in prior art’s device in order to adjust and optimize the device characteristics.
Regarding claim 20, Tihanyi teaches in figure 4 and related that the second field plate overlaps the first field plate 12, and wherein the second spacer layer (chosen as such) is on an entirety of an upper surface of the first field plate and an entirety of an upper surface of the first spacer layer. Tihanyi does not teach that the second field plate overlaps the gate. Saito et al. teach in figure 21 and related text that the second field plate overlaps the gate. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the second field plate overlaps the gate, as taught by Saito et al., in Tihanyi’s device in order to provide better connection to the source electrode.
Regarding claim 22, Tihanyi teaches in figure 4 and related that the second field plate is free of overlap with the second portion of the first spacer layer (arbitrarily chosen) in a direction perpendicular to an upper surface of the active region.
Claim 18 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tihanyi (6,445,038) and Saito et al. (6,940,090), as applied to claim 17 above, and further in view of Inokuchi et al. (6,294,801).Regarding claim 18, Tihanyi and Saito et al. teach substantially the entire claimed structure, as applied to claim 1 above, including the second field plate is electrically connected to the source electrode or the gate, but except at least a portion of the gate is in the active region.
Inokuchi et al. teach in figure 1 and related text a portion of the gate 150 is in the active region.
Saito et al., Inokuchi et al. and Tihanyi are analogous art because they are directed to devices comprising field plates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Tihanyi because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form at least a portion of the gate is in the active region, as taught by Inokuchi et al., in prior art’s device in order to improve the device characteristics.
Response to Arguments
1. Applicant argue that the portion of Claim 15 reciting that "the spacer layer extends between the gate and the field plate is supported by the elected embodiment of FIG. 7” according to the annotated figure 7.
1. Applicants do not explain how the annotated spacer layer in figure 7 is located between the gate and the field plate.
2. The rest of applicant arguments with respect to the claim(s) have been considered but are moot because of the new ground of rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
4/18/2025 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800