Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on September 19, 2023; August 22, 2024, & May 15, 2025 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7-8, 14-15, 19, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mauder et al. (Pub. No.: US 2012/0286355 A1).
Regarding Claim 1, Mauder et al. discloses a semiconductor device, comprising: an epitaxial layer disposed on a semiconductor substrate, the epitaxial layer including an active region, in which at least one active element is formed, and an edge termination region, in which at least one edge termination structure is formed, the edge termination region being laterally adjacent to the active region (Par. 0045-0059; Figs. 1-2 – epitaxial layer comprising n-type first semiconductor region 1; active region 210 (Fig. 2); edge termination region 220 (Fig. 2)); and
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a charged layer disposed on an upper surface of the epitaxial layer, the charged layer covering at least a portion of the active region and extending laterally over at least a portion of the edge termination region (Par. 0045-0059; Figs. 1-2 – charged layer comprising negatively charged dielectric portion 30 which extends laterally over at least a portion of the edge termination region 220 (Fig. 2); the charged layer also covers a portion of the active region (Fig. 1)).
Regarding Claim 2, Mauder et al., as applied to claim 1, discloses the semiconductor device, further comprising: a plurality of active trenches formed in the active region, each of the active trenches extending vertically through at least a portion of the epitaxial layer (Par. 0045-0059; Figs. 1-2 – active trenches 60, 61 & 62 (Fig. 1)), wherein the charged layer is formed on at least sidewalls of each of the plurality of active trenches (Par. 0045-0059; Figs. 1-2 – active trenches 60, 61 & 62 (Fig. 1) – formed at least on portions of each of the active trenches).
Regarding Claim 7, Mauder et al., as applied to claim 1, discloses the semiconductor device, wherein charged layer comprises a material having an inherent fixed charge of a first polarity type, and wherein the epitaxial layer comprises material doped with an impurity of the first polarity type at a prescribed concentration level (Par. 0045-0059; Figs. 1-2 – n-type polarity).
Regarding Claim 8, Mauder et al., as applied to claim 1, discloses the semiconductor device, wherein the charged layer is configured to function as a passivation layer in the semiconductor device (Par. 0045-0059; Figs. 1-2 – although this prior art does not explicitly teach that the charged layer is configured to function as a passivation layer, it is implied, at least under BRI ).
Regarding Claim 14, Mauder et al. discloses a method of forming a semiconductor device, the method comprising: forming an epitaxial layer on a semiconductor substrate, the epitaxial layer including an active region, in which at least one active element is formed, and an edge termination region, in which at least one edge termination structure is formed, the edge termination region being laterally adjacent to the active region (Par. 0045-0059; Figs. 1-2 – epitaxial layer comprising n-type first semiconductor region 1; active region 210 (Fig. 2); edge termination region 220 (Fig. 2)); and
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forming a charged layer on an upper surface of the epitaxial layer, the charged layer covering at least a portion of the active region and extending laterally over at least a portion of the edge termination region (Par. 0045-0059; Figs. 1-2 – charged layer comprising negatively charged dielectric portion 30 which extends laterally over at least a portion of the edge termination region 220 (Fig. 2); the charged layer also covers a portion of the active region (Fig. 1)).
Regarding Claim 15, Mauder et al., as applied to claim 14, discloses the method, further comprising: forming a plurality of active trenches in the active region, each of the active trenches extending vertically through at least a portion of the epitaxial layer (Par. 0045-0059; Figs. 1-2 – active trenches 60, 61 & 62 (Fig. 1)), and forming the charged layer on at least sidewalls of each of the plurality of active trenches (Par. 0045-0059; Figs. 1-2 – active trenches 60, 61 & 62 (Fig. 1) – formed at least on portions of each of the active trenches).
Regarding Claim 19, Mauder et al., as applied to claim 14, discloses the method, wherein the charged layer is formed using atomic layer deposition of a material having an inherent fixed charge of a first polarity type, wherein the epitaxial layer comprises material of the first polarity type (Par. 0045-0059 & 0070; Figs. 1-2 – n-type polarity).
Regarding Claim 25, Mauder et al., as applied to claim 14, discloses the method, wherein the charged layer extends laterally over the edge termination region for a prescribed length, the prescribed length being equal to a full lateral length of the edge termination region (Par. 0045-0060; Figs. 1-2 – charged layer comprising negatively charged dielectric portion 30 and positively/negatively charged dielectric portion 80).
Allowable Subject Matter
Claims 29-31 are allowed. The following is an examiner's statement of reasons for allowance:
Regarding Claim 29: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by a method of forming an edge termination structure in a semiconductor device, the semiconductor device including an active region, in which one or more active structures are formed, and an edge termination region, in which the edge termination structure is formed, the edge termination region being laterally adjacent to the active region, the method comprising: forming an epitaxial layer on a semiconductor substrate, the epitaxial layer extending laterally across the active and edge termination regions; forming a plurality of active trenches in the active region and at least one edge trench in the edge termination region, each of the at least one edge trench and the plurality of active trenches extending vertically through at least a portion of the epitaxial layer; forming a first charged layer on at least exposed sidewalls of each of the active trenches and the at least one edge trench in a same processing step; and at least partially filling each of the at least one edge trench and the plurality of active trenches with a fill material in a same processing step to form a trench fill layer. The most relevant prior art reference due to Mauder et al. (Pub. No.: US 2012/0286355 A1) substantially discloses a method of forming an edge termination structure in a semiconductor device, the semiconductor device including an active region, in which one or more active structures are formed, and an edge termination region, in which the edge termination structure is formed, the edge termination region being laterally adjacent to the active region (Par. 0106-0115; Fig. 20 – active region 310; edge termination region 320), the method comprising:
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forming an epitaxial layer on a semiconductor substrate, the epitaxial layer extending laterally across the active and edge termination regions (Par. 0106-0115; Fig. 20 – epitaxial layer comprising n-type first semiconductor region 1); forming a plurality of active trenches in the active region and at least one edge trench in the edge termination region, each of the at least one edge trench and the plurality of active trenches extending vertically through at least a portion of the epitaxial layer (Par. 0106-0115; Fig. 20 – this Fig. does not show any active structures but refers to Fig. 1 which shows transistors/diodes with active trenches ; edge trench 62); forming a first charged layer on at least exposed sidewalls of each of the active trenches and the at least one edge trench Par. 0106-0115; Fig. 20 – charged layer comprising negatively charged dielectric portion 30);
Additionally, the prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. See form PTO-892.
However, none of these prior art references indicated above or the prior arts made of record in form PTO-892, disclose all the limitations of claim 29 (the individual limitations may be found in a plurality of prior arts but there is no motivation to combine). Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, claim 29 is deemed patentable over the prior arts.
Regarding Claims 30-31: these claims are allowed because of their dependency status from claim 29.
Allowable Subject Matter
Claims 3-6, 9-10, 13, 16-18, 20-24, and 27-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yilmaz (Pub. No.: US 20170250173 A1) – This prior art teaches a semiconductor device, comprising: an epitaxial layer disposed on a semiconductor substrate, the epitaxial layer including an active region (14), in which at least one active element is formed, and an edge termination region, (15), in which at least one edge termination structure is formed, the edge termination region being laterally adjacent to the active region; and a 94) disposed on an upper surface of the epitaxial layer, the Par. 0032-0051; Figs. 1-2).
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02/19/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893