DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- 2, 5, 8-14, 21, 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fung et al (US 2017/0154958).
Regarding claim 1, Fung discloses a semiconductor structure, comprising: a plurality of nanostructures vertically stacked and separated from one another Fig 7-8; Fig 10A-10C; a source/drain feature ¶0043 adjacent to the plurality of nanostructures Fig 12; and an inner spacer layer Fig 11C, 70 and Fig 12, 70 including a vertical portion interposing between the plurality of nanostructures and the source/drain feature Fig 11-B and 11C and Fig 12 and a plurality of horizontal portions Fig 11B, 20 interposing between the nanostructures Fig 11B, 25 , wherein a source/drain junction is located in the vertical portion of the inner spacer layer and is spaced apart from the plurality of nanostructures by a distance Fig 14-16; a gate stack wrapping around the plurality of nanostructures ¶0055 Fig 15B-Fig 17; a contact etching stop layer Fig 16, 90 surrounding the source/drain feature; and a gate spacer layer Fig 17, 55 between the gate stack and the contact etching stop layer Fig 17, 90, wherein the gate spacer layer Fig 17, 55 has a first sidewall facing the gate stack and extending along a vertical direction and a second sidewall facing the contact etching stop layer and extending along the vertical direction Fig 17 and Fig 20A-20C, and the source/drain junction extends along the vertical direction and between the first sidewall and the second sidewall of the gate spacer layer Fig 17 and Fig 20A-20C.
Regarding claim 2, Fung discloses wherein the inner spacer layer is made of a semiconductor material 0042.
Regarding claim 5, Fung discloses wherein the gate spacer layer is in direct contact with the horizontal portions of the inner spacer layer Fig 9A-9C, 11A-11C.
Regarding claim 8, Fung discloses wherein the inner spacer layer Fig 11C, 70 and Fig 12, 70 further includes a bottom portion below the source/drain feature Fig 11A-20C.
Regarding claim 9, Fung discloses a semiconductor structure, comprising: a gate stack wrapping around a plurality of nanostructures Fig 20A-20C; a gate spacer layer Fig 20A-20C, 55 alongside the gate stack Fig 20A-20C, 104; a semiconductor inner spacer layer Fig 11C, 70 and Fig 12, 70 alongside the plurality of nanostructures below the gate spacer layer Fig 8-9C; and a source/drain feature alongside the semiconductor inner spacer layer Fig 11A-13, wherein the gate spacer layer Fig 20A-20C, 55 includes a portion of above the plurally of nanostructures Fig 20A-20C, the portion gate spacer layer includes a first sidewall interfaced with the gate stack and a second sidewall interfaced with the source/drain feature Fig 20A-20C, 55, and a source/drain junction vertically extends in the semiconductor inner spacer and between a first imaginary extension line extending along the first sidewall of the gate spacer layer and a second imaginary extension line extending along the second sidewall of the gate spacer layer Fig 20A-20C.
Regarding claim 10, Fung discloses wherein the source/drain junction extends through a topmost one of the nanostructures Fig 20A-20C.
Regarding claim 11, Fung discloses wherein the gate stack includes an interfacial layer, a high-k gate dielectric layer over the interfacial layer and a gate electrode layer over the high-k gate dielectric layer Fig 20A-20C ¶0056.
Regarding claim 14, Fung discloses a fin element below the plurality of nanostructures; and an isolation structure surrounding the fin element Fig 20A-20C ¶0035 and 0056.
Regarding claim 21, Fung discloses semiconductor structure, comprising: a fin element extending lengthwise along a first direction Fig 3-4; a plurality of nanostructures over the fin element Fig 3-4; a gate stack extending lengthwise along a second direction that is different from the first direction and wrapping around the plurality of nanostructures Fig 20A-20C;a source/drain feature over the fin element Fig 12-13; and a semiconductor layer Fig 11C, 70 and Fig 12, 70 ¶0042 including a first portion between the plurality of nanostructures and the source/drain feature and a plurality of second portions between the plurality of nanostructures Fig 20A-20C, wherein a dopant concentration of the semiconductor layer is less than a dopant concentration of the source/drain feature ¶0042-0043, wherein a source/drain junction is located in the first portion of the semiconductor layer and extends in a third direction that is different from the first direction and the second direction Fig 11A-20C and a gate spacer layer Fig 20A-20C, 55 alongside the gate stack, wherein in across-sectional view, first sidewalls of the plurality of nanostructures and a first sidewall of the first semiconductor layer are substantially coplanar Fig 20A-20C ¶0066, and the gate spacer layer is interfaced with the first sidewalls of the plurality of nanostructures and the first sidewall of a first semiconductor layer Fig 20B.
Regarding claim 26, Fung discloses, wherein the source/drain junction does not extend through the plurality of nanostructures Fig 11A-20C.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 6, 7, 12, 13, 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Fung et al (US 2017/0154958) in view of Chiang et al (US Patent No. 10,134,640).
Regarding claim 3, Fung discloses all the limitations but silent on the arrangement of the interfacial layer relative to the nanostructure. Whereas Chiang discloses : an interfacial layer including a first portion along a bottom surface of a first nanostructure in the plurality of nanostructures Fig IJ-2 (Column 7, lines 55-61) a second portion along a top surface of a second nanostructure in the plurality of nanostructures, and a third portion connecting the first portion of the interfacial layer to the second portion of the interfacial layer Fig IJ-2 (Column 7, lines 55-61). Fung and Chiang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fung because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Fung and incorporate the teachings of Chiang to provide an alternative arrangement to improve device isolation.
Regarding claim 4, Chiang discloses wherein the third portion of the interfacial layer is in direct contact with one of the horizontal portions of the inner spacer layer Fig IJ-2 (Column 7, lines 55-61).
Regarding claim 6, Chiang discloses wherein the inner spacer layer is doped(Column 6, lines 6-67).
Regarding claim 7, Chiang discloses a spacer concentration (Column 6, lines 6-67) but silent on having a range from about 1x 1019 cm-3 to about 9x 1019 cm3. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Regarding claim 12, Chiang discloses wherein the interfacial layer is spaced apart from the semiconductor inner spacer layer by a distance Fig IJ-2 (Column 7, lines 55-61).
Regarding claim 13, Chiang discloses wherein in a cross- sectional view, the interfacial layer has a closed-loop profile, and the high-k gate dielectric layer is located within the closed-loop profile of the interfacial layer Fig IJ-2 (Column 7, lines 55-61).
Regarding claim 22, Chiang discloses wherein the gate stack includes an interfacial layer surrounding the plurality of nanostructures, a high-k gate dielectric layer on the interfacial layer, and a gate electrode layer on the high-k gate dielectric layer, wherein the interfacial layer is interfaced with the second portions of the semiconductor layer Fig IJ-2 (Column 7, lines 55-61).
Regarding claim 23, Chiang discloses wherein the high-k gate dielectric layer is separated from the semiconductor layer by the interfacial layer Fig IJ-2 (Column 7, lines 55-61).
Regarding claim 24, Chiang discloses wherein the semiconductor layer is made of a semiconductor material (Column 6, lines 6-67), and the interfacial layer is made of the oxide of the semiconductor material (Column 7, lines 55-61).
Regarding claim 25, Fung and Chiang discloses source and spacer concentration but silent on having a dopant concentration of about two orders. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the value, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ (CCPA 1980).
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive. In response to applicants argument (Page 9-13) that the prior art of record does not teach the newly added limitations, the examiner disagrees and finds the argument unpersuasive. Fung et al (US 2017/0154958) discloses all the added limitations as described in the rejection above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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