DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 4/2/2026, has been entered. The Applicant has amended claims 1, 11, and 22-23. Accordingly, claims 1-23 remain pending in the application.
Applicant’s amendment to the title has overcome the title objection previously set forth in the Non-Final Office Action mailed on 1/2/2026.
Applicant' s amendment to claim 11 has also overcome the 25. U.S.C. 112(b) rejections made on claim 11 in the Non-Final Office Action mailed on 1/2/2026.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in in Korean Patent Application No. 10-2022-0140701, filed on 10/27/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11-13, 16-18, and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong (US 2021/0216157 A1).
Regarding claim 1, Jeong teaches a display device (display device 1, Fig. 1. [0062]) comprising:
a base layer (substrate SB, Fig. 6, [0070]) having a plurality of pixel regions (second pixel areas PA2, Fig. 4, [0076]) including:
a first pixel region (second pixel area PA2 on the left in Fig. 6 (the cross-section along A-A’ line of Fig. 5));
a second pixel region (second pixel area PA2 on the right in Fig. 6 (the cross-section along A-A’ line of Fig. 5) adjacent to the first pixel region (second pixel area PA2 on the left in Fig. 6); and
a non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Figs. 4-6, [0076]) surrounding the plurality of pixel regions (second pixel areas PA2 comprising pixels PX, Fig. 4-6);
a circuit layer (comprising first insulating layer IN1 ([0095]), second insulating layer IN2 ([0097]) and third insulating layer IN3 ([0099]) containing the capacitor CP ([0088] and the transistor TR ([0088]); labeled as circuit layer in Illustrative Fig. 1, which is an annotated version of Fig. 6) on the base layer (substrate SB, Illustrative Fig. 1) and including a plurality of insulating layers (first insulating layer IN1, second insulating layer IN2, and third insulating layer IN3, Illustrative Fig. 1) and plurality of conductive patterns (capacitor CP, transistor TR, data line DL, and parts of the common electrode E2; Illustrative Fig. 1, [0088]-[0089]);
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a light-emitting element layer (see light emitting-layer including emission layer EL, Illustrative Fig. 1, [0104]) on the circuit layer (circuit layer, Illustrative Fig. 1); and
an input sensing unit (touch electrode sections TES, Illustrative Fig. 1, [0113]) on the light-emitting element layer (light emitting-layer, Illustrative Fig. 1) and including a sensing pattern (touch electrode TE, Illustrative Fig. 1 and Fig. 5) overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, see Fig. 5 showing that the touch electrodes TE pass through the non-pixel area between transmissive areas (TA)),
wherein the light-emitting element layer (light emitting-layer, Illustrative Fig. 1) comprises:
a pixel defining structure (comprising fourth insulating layer IN4 and opening OP, Illustrative Fig. 1, [0102]) overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Illustrative Fig. 1: some portion of the fourth insulating layer IN4 is in the transmissive area TA) and having a plurality of pixel openings (opening OP, Illustrative Fig. 1, [0102]) corresponding to the plurality of pixel regions (second pixel areas PA2, Illustrative Fig. 1) respectively; and
a plurality of light-emitting elements (light emitting diodes LED, Illustrative Fig. 1 (see also Fig. 5), [0091]) at least partially in the plurality of pixel openings (opening OP, Illustrative Fig. 1),
wherein the pixel defining structure (fourth insulating layer IN4 and opening OP, Illustrative Fig. 1) includes a step pattern (the openings in fourth insulating layer IN4 at the edges of opening OPN, labeled as opening 2 in Illustrative Fig. 1 (see also Fig. 5 for to view), [0104]) overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Fig. 5 and Illustrative Fig. 1: opening OPN is in the transmissive area TA) and surrounding portions of each of the plurality of pixel regions (second pixel area PA2, Fig. 5: openings OPN surround the pixel regions PA2, therefore the step patterns surround the pixel regions), and
the plurality of conductive patterns (capacitor CP, transistor TR, data line DL, and parts of the common electrode E2; Illustrative Fig. 1) include a shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 1, [0106]: “The common electrode E2 may extend along a side surface of the fourth insulating layer IN4 to an edge of the transmissive area TA to sufficiently shield the data line DL.“ ) on at least one of the plurality of insulating layers (third insulating layer IN3, Illustrative Fig. 1) and overlapping (parts of the common electrode E2 is in the opening 2, Illustrative Fig. 1) and having a shape corresponding to at least a portion of the step pattern (see Fig. 5 and [0105]: the shielding portion of the common electrode E2 forms the portion of the non-pixel region around the transmissive areas TA, and therefore has the shape of the non-pixel areas around the transmissive regions TA) along a plurality of edges of a pixel region (Fig. 5: the shielding portion of the common electrode E2 surrounds second pixel regions PA2 along four sides/edges), from among the first and second pixel regions (see neighboring second pixel areas along A-A’ line) , in a plan view (Fig. 5 is a plan view), at least a portion of the shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 1) being configured to have a voltage applied thereto ([0107]: ”The common electrode E2 may be provided in common to all the pixels PX, and may receive a common voltage ELVSS“).
Regarding claim 11, Jeong teaches the display device of claim 1,
wherein the step pattern comprises (the openings in fourth insulating layer IN4 at the edges of opening OPN, labeled as opening 2 in Illustrative Fig. 1 (see also Fig. 5 for top view), [0104]):
a first step pattern (see first pattern as labeled in Illustrative Fig. 2, which is an annotated version of Fig. 5) surrounding a first portion (right and bottom portions of the first pixel region, Illustrative Fig. 2) of the first pixel region (first pixel region, Illustrative Fig. 2); and
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a second step pattern (second pattern, Illustrative Fig. 2) surrounding a second portion (left and bottom portions of second pixel region, Illustrative Fig. 2) of the second pixel region (second pixel, Illustrative Fig. 2),
wherein a first area (top and left portions of the first pixel region, Illustrative Fig. 2) which the first step pattern (first step pattern, Illustrative Fig. 2) does not surround the first pixel region (first pixel region, Illustrative Fig. 2) is defined as a first open portion (top and left sides of the first pixel region, Illustrative Fig. 2), and a second area (top and right portions of the second pixel region, Illustrative Fig. 2) at which the second step pattern (second step pattern, Illustrative Fig. 2) does not surround the second pixel region (second pixel region, Illustrative Fig. 2) is defined as a second open portion (top and right sides of the second pixel region, Illustrative Fig. 2), the first open portion (top and left sides of the first pixel region, Illustrative Fig. 2) and the second open portion (top and right sides of the second pixel region, Illustrative Fig. 2) do not face each other.
Regarding claim 12, Jeong teaches the display device of claim 11, wherein the shielding pattern (the extension of the common electrode E2 on the side surface of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Figs. 1-2) overlaps each of the first open portion (top and right sides of the second pixel region, Illustrative Fig. 2) and the second open portion (top and right sides of the second pixel region, Illustrative Fig. 2) of the step pattern (the openings in fourth insulating layer IN4 at the edges of opening OPN, Illustrative Figs. 1-2: common electrode E2 covers the sides of the pixels corresponding to first and second open portions) in the plan view (top view as illustrated in Illustrative Fig. 2).
Regarding claim 13, Jeong teaches the display device of claim 11, wherein the shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 1) further comprises:
a first shielding pattern (the portion of the shielding pattern corresponding to first step pattern, Illustrative Fig. 2) overlapping the first step pattern (first step pattern, Illustrative Fig. 2) in the plan view (Illustrative Fig. 2 shows the plan view); and
a second shielding pattern (the portion of the shielding pattern corresponding to second step pattern, Illustrative Fig. 2) overlapping the second step pattern (second step pattern, Illustrative Fig. 2) in the plan view,
wherein a first sub open portion (the portion of the shielding pattern around the first pixel region that is not covered by first shielding pattern, Illustrative Fig. 2) corresponding to the first open portion (first open portion, Illustrative Fig. 2) is defined in the first shielding pattern (the portion of the shielding pattern corresponding to first step pattern, Illustrative Fig. 2: while the shielding pattern is continuous around the first pixel region, the first shielding pattern is open on the top and left edges of the first pixel region), and a second sub open portion (the portion of the shielding pattern around the second pixel region that is not covered by first shielding pattern, Illustrative Fig. 2) corresponding to the second open portion (second open portion, Illustrative Fig. 2) is defined in the second shielding pattern (the portion of the shielding pattern corresponding to second step pattern, Illustrative Fig. 2: while the shielding pattern is continuous around the second pixel region, the second shielding pattern is open on the top and right edges of the second pixel region).
Regarding claim 16, Jeong teaches the display device of claim 1,
wherein the circuit layer (circuit layer, Illustrative Fig. 1) further includes a signal line (gate electrode GE, Illustrative Fig. 1, [0010]: “Each of the pixels PX may be electrically connected with a signal line such as a gate line” and gate electrode is connected to a gate line GL) electrically connected to a light-emitting element (light-emitting diode LED, Illustrative Fig. 1: gate electrode GE is electrically connected to pixel electrode E1 through the transistor TR) from among the light-emitting elements (light-emitting diode LEDs, Illustrative Fig. 1), and
the plurality of insulating layers (first insulating layer IN1, second insulating layer IN2, and third insulating layer IN3, Illustrative Fig. 1) include:
a first base insulating layer (second insulating layer IN2, Illustrative Fig. 1) in which the signal line (gate electrode GE and gate line GL, Illustrative Fig. 1) is arranged; and
a second base insulating layer third insulating layer IN3, Illustrative Fig. 1) on the first base insulating layer (second insulating layer IN2, Illustrative Fig. 1) and in which the shielding pattern (the extension of the common electrode E2 on the side surface of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 1: a portion of the shielding pattern is in the opening in the third insulating layer IN3) is arranged.
Regarding claim 17, Jeong teaches the display device of claim 1,
wherein the circuit layer (circuit layer, Illustrative Fig. 1) further includes a signal line (data line DL, Illustrative Fig. 1, [0065]: “Each of the pixels PX may be electrically connected with a signal line such as a gate line, a data line”) electrically connected to a light-emitting element (light-emitting diode LED, Illustrative Fig. 1:) from among the light-emitting elements (light-emitting diode LED, Illustrative Fig. 1), and
the signal line (data line DL, Illustrative Fig. 1) and the shielding pattern (the extension of the common electrode E2 on the side surface of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 1) are on a same layer (second insulating layer, Illustrative Fig. 1: a portion of the shielding pattern in on the second insulating layer IN2) among the plurality of insulating layers (first insulating layer IN1, second insulating layer IN2, and third insulating layer IN3, Illustrative Fig. 1).
Regarding claim 18, Jeong teaches the display device of claim 1,
wherein the plurality of pixel regions (second pixel regions PA2, Figs, 4-5) further include a third pixel region (see Illustrative Fig. 3, which is an annotated version of Fig. 4, for the first, second, and third pixel regions) adjacent to the second pixel region (second pixel region, Illustrative Fig. 3),
the first pixel region (first pixel region, Illustrative Fig. 3) is configured to display a first light (green G, Illustrative Fig. 3, [0089]: “second pixel area PA2 may include the pixels R, G, and B.”, and therefore each pixel region is configured to display all three wavelengths) having a first wavelength (green light corresponds to a specific wavelength range which is different than the wavelengths of other colors),
the second pixel region (second pixel region, Illustrative Fig. 3) is configured to display a second light (blue B, Illustrative Fig. 3, [0089]: “second pixel area PA2 may include the pixels R, G, and B.”, and therefore each pixel region is configured to display all three wavelengths) having a second wavelength different (blue light corresponds to a specific wavelength range which is different than the wavelengths of other colors) from the first wavelength (wavelength of green light), and
the third pixel region (third pixel region, Illustrative Fig. 3) is configured to display a third light (red R, Illustrative Fig. 3, [0089]: “second pixel area PA2 may include the pixels R, G, and B.”, and therefore each pixel region is configured to display all three wavelengths) having a third wavelength (red light corresponds to a specific wavelength range which is different than the wavelengths of other colors) different from the first wavelength (wavelength of green light) and the second wavelength (wavelength of blue light).
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Regarding claim 21, Jeong teaches the display device of claim 1, wherein the sensing pattern (touch electrode TE, Illustrative Fig. 1 and Fig. 5) overlaps at least a portion of the shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 1) in the plan view (See Fig. 5 as the plan view of Illustrative Fig. 1).
Regarding claim 22, Jeong teaches a display device (display device 1, Fig. 1. [0062]) comprising:
a base layer (substrate SB, Fig. 6, [0070]) having a plurality of pixel regions (second pixel areas PA2, Fig. 4, [0076]) including:
a first pixel region (second pixel area PA2 on the left in Fig. 6);
a second pixel region (second pixel area PA2 on the right in Fig. 6) adjacent to the first pixel region (second pixel area PA2 on the left in Fig. 6); and
a non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Figs. 4-6, [0076]) surrounding the plurality of pixel regions (second pixel areas PA2 comprising pixels PX, Fig. 4-6);
a plurality of insulating layers (first insulating layer IN1, second insulating layer IN2, and third insulating layer IN3, Fig. 6) on the base layer (substrate SB, Fig. 6);
a shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Fig. 6, [0106]: “The common electrode E2 may extend along a side surface of the fourth insulating layer IN4 to an edge of the transmissive area TA to sufficiently shield the data line DL.“) on the plurality of insulating layers (first insulating layer IN1, second insulating layer IN2, and third insulating layer IN3, Fig. 6) and overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Fig. 6: a portion of the common electrode E2 (shielding pattern) is in the transmissive area TA ), at least a portion of the shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Fig. 6) being configured to have a voltage applied thereto ([0107]: ”The common electrode E2 may be provided in common to all the pixels PX, and may receive a common voltage ELVSS“);
a pixel defining structure (fourth insulating layer IN4 and opening OP, Fig. 6) overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Fig. 6: a portion of the fourth insulating layer IN4 is in the transmissive area TA) and having a plurality of pixel openings (opening OP, Fig. 6, [0102])) corresponding to the plurality of pixel regions (second pixel areas PA2, Fig. 6) respectively; and
a light-emitting element (light emitting diode LED, Fig. 6, [0091]) on the plurality of insulating layers (first insulating layer IN1, second insulating layer IN2, and third insulating layer IN3, Fig. 6) and including an organic layer (fourth insulating layer IN4, Fig. 6, [0102]: “A fourth insulating layer IN4, which may include an organic insulating material”) and an upper electrode (common electrode E2, Fig. 6) on the organic layer (fourth insulating layer IN4, Fig. 6),
wherein the pixel defining structure (fourth insulating layer IN4 and opening OP, Fig. 6) includes a step pattern (the openings in fourth insulating layer IN4 at the edges of opening OPN, Fig. 6 (see also Fig. 5 for to view), [0104]) overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Figs. 5-6: opening OPN is in the transmissive area TA) and surrounding a portion of each of the plurality of pixel regions (second pixel area PA2, Fig. 5: openings OPN surround the pixel regions PA2, therefore the step patterns surround the pixel regions),
a portion of the organic layer (the portion of the fourth insulating layer IN4 that is on the side surface of the third insulating layer IN3 is on the step pattern, Fig. 6) and the upper electrode (common electrode E2, Fig. 6) is on the step pattern (the openings in fourth insulating layer IN4 at the edges of opening OPN, Fig. 6), and
the step pattern (the openings in fourth insulating layer IN4 at the edges of opening OPN, Fig. 6) overlaps at least a portion of the shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Fig. 6) in a plan view (shielding pattern is on the step pattern, and therefore shielding pattern and step pattern overlap in plan view), the at least the portion of the shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Fig. 6) having a shape corresponding to the step pattern (the openings in fourth insulating layer IN4 at the edges of opening OPN, Fig. 6: a portion of the shielding pattern (common electrode E2) covers the step pattern (side surface of the fourth insulating layer IN4), and therefore shielding pattern and step pattern have the same shape) along a plurality of edges of a pixel region (second pixel area PA2, Figs. 5-6), from among the first (second pixel area PA2 on the left in Fig. 6, which is a cross-section along A-A’ line of Fig. 5) and second (second pixel area PA2 on the right in Fig. 6, which is a cross-section along A-A’ line of Fig. 5) pixel regions , in the plan view (Fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2021/0216157 A1) as applied to claims 1, 11-13, 16-18, 21, and 23 above, and further in view of Lee-248 (US 2021/0351248 A1).
Jeong teaches the display device of claim 1, wherein a light-emitting element (light emitting diode LED, Illustrative Fig. 1, [0101]) from among the light-emitting elements (Fig. 5: each second pixel area PA2 has at least one LED) comprises:
a first electrode (pixel electrode E1, Illustrative Fig. 1, [0100]) on the circuit layer (circuit layer, Illustrative Fig. 1);
a layer (emission layer EL, Illustrative Fig. 1, [0104]: “The emission layer EL may include material layers that may uniquely or individually emit light of primary colors such as red, green, and blue.”) on the first electrode (pixel electrode E1, Illustrative Fig. 1) and the pixel defining structure (fourth insulating layer IN4, Illustrative Fig. 1) and including an emission layer (emission layer EL include material layer for emitting light at a primary color); and
a second electrode (common electrode E2, Illustrative Fig. 1, [0105]) on the layer (emission layer EL, Illustrative Fig. 1),
wherein the second electrode (common electrode E2, Illustrative Fig. 1) is on the step pattern (the openings in fourth insulating layer IN4 at the edges of opening OPN, labeled as opening 2 in Illustrative Fig. 1).
Jeong, however, is silent on that
the layer on the first electrode is an organic layer; and
a portion of the organic layer is on the step pattern.
Lee-248 (US 20200235172 A1), on the other hand, teaches a display device (display apparatus 500, Fig. 5), wherein the light-emitting elements (light emitting diode 120, Fig. 5, [0057]) are organic light-emitting diodes ([0049]), and comprise an anode 121, an organic layer 122, and a cathode 123 (Fig. 5, [0090]), wherein the organic layer 122 includes a light emitting layer and a common layer ([0095]), and common layer and the cathode follow the same pattern on the surface of the display ([0097]-[0098]) and formed together ([0105]), as they are shared by all the pixels ([0097]-[0098]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to obtain an organic display device would realize that the display device structures of Jeong (Figs. 1-6) and Lee-248 (Figs. 4-7) are analogous, and the LEDs in Jeong can be replaced by the organic LEDs of Lee-248. Therefore, such a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to obtain a display device with organic LEDs would be motivated to replace the LEDs in Jeong with the organic LEDs of Lee-172 such that the layer on the first electrode and below the second electrode (common electrode E2 of Jeong, Illustrative Fig. 1, [0109]: “the common electrode E2 may be a cathode”) is an organic layer, and organic layer is follows the pattern of the cathode (common electrode E2 of Jeong, Illustrative Fig. 1). Thus, the combination of Jeong and Lee-258 leads to an organic display device wherein
the layer on the first electrode is an organic layer, and
a portion of the organic layer is on the step pattern.
Regarding claim 3, Jeong in view of Lee-248 teaches the display device of claim 2, wherein
Jeong further teaches that
the pixel defining structure (fourth insulating layer IN4 and opening OP, Illustrative Fig. 1) further includes a pixel defining layer (fourth insulating layer IN4) overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA (Figs. 4-6), Illustrative Fig. 1: parts of the fourth insulating layer in the transmissive area TA),
the step pattern (opening 2, Illustrative Fig. 1) has a shape recessed (opening 2 is formed by gradual recessing the edges of fourth insulating layer IN4, Illustrative Fig. 1) from an upper surface of the pixel defining layer (upper surface of the fourth insulating layer IN4, Illustrative Fig. 1) in a thickness direction (vertical direction in Illustrative Fig. 1) of the pixel defining layer (fourth insulating layer IN4, Illustrative Fig. 1), and
the step pattern (opening 2, Illustrative Fig. 1) includes:
a lower surface (see lower surface in Illustrative Fig. 1) that is parallel with the upper surface (see upper surface in Illustrative Fig. 1) of the pixel defining layer (fourth insulating layer IN4, Illustrative Fig. 1); and
an inner side surface (see inner side surface in Illustrative Fig. 1) connecting the lower surface (lower surface, Illustrative Fig. 1) and the upper surface (upper surface, Illustrative Fig. 1) of the pixel defining layer (fourth insulating layer IN4, Illustrative Fig. 1).
Regarding claim 4, disclosing Jeong and Lee-248 teaches the display device of claim 3, wherein
the combination of Jeong and Lee-248 further teaches that the organic layer (organic layer 122 of Lee-248 is located everywhere under common electrode E2 (Illustrative Fig. 1) after the display device of Jeong is modified by the teachings of Lee-248, [0095]) further comprises:
a first portion (the portion on the top surface of the fourth insulating layer IN4, Illustrative Fig. 1) arranged on the upper surface of the pixel defining layer (top surface of fourth insulating layer IN4, Illustrative Fig. 1: the organic layer 122 is under the common electrode E2 after the display device of Jeong is modified by the teachings of Lee-248); and
a second portion (the portion on the side surface of the fourth insulating layer IN4 in the opening OPN, Illustrative Fig. 1) arranged on the inner side surface of the step pattern (the side surface of the fourth insulating layer IN4, Illustrative Fig. 1),
wherein a thickness of the second portion (the portion on the side surface of the fourth insulating layer IN4 in the opening OPN) is smaller than a thickness of the first portion (the portion on the top surface of the fourth insulating layer IN4, Illustrative Fig. 1, Lee-248, [0156]: the deposition of the organic layer is not conformal and therefore the thickness at the side surface of the fourth insulating layer IN4 will be slightly larger than the thickness side on the side surface of the fourth insulating layer IN4).
Regarding claim 9, Jeong in view of Lee-258 teaches the display device of claim 2,
wherein the first electrode (pixel electrode E1, Illustrative Fig. 1, [0100]) is applied with a first power supply voltage ([0101]: “The pixel electrode E1 may be electrically connected to the drain electrode DE of the transistor TR through an opening of the third insulating layer IN3”, and therefore, first electrode is connected to driving voltage ELVDD through the pixel circuit (see Fig.11, [0146]), and
the shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 1) is applied with a second power supply voltage ([0107]: ”The common electrode E2 may be provided in common to all the pixels PX, and may receive a common voltage ELVSS“) different from the first power supply voltage (driving voltage ELVDD).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2021/0216157 A1) in view of Lee-248 (US 2021/0351248 A1) as applied to claims 2-4, and 9 above, and further in view of Youn (US 2018/0166644 A1).
Regarding claim 10, Jeong in view pf Lee-248 teaches the display device of claim 2, wherein
the combination of Jeong and Lee-248 (see claim 2 rejection above) further teaches that the organic layer (organic layer 122, Lee-248, [0095]) comprises:
a first light-emitting stack (organic layer 122, Lee-248, [0095]: “The organic layer 122 includes a light emitting layer and a common layer”) on the first electrode (pixel electrode E1, Illustrative Fig. 1) and the pixel defining structure (fourth insulating layer IN4 and opening OP, Illustrative Fig. 1: the organic layer 122 is also on the fourth insulating layer IN4 and on the edge of the opening OP after the display device of Jeong is modified by Lee-248) and including a first emission layer (light emitting layer, [0095]: “The organic layer 122 includes a light emitting layer and a common layer”).
Jeong and Lee-248 are, however, silent on that the organic layer further comprises
a first charge generation layer on the first light-emitting stack; and
a second light-emitting stack between the first charge generation layer and the second electrode and including a second emission layer.
Youn, on the other hand, teaches a tandem type organic light emitting device (tandem OLED 100, Fig. 1, [0025]) wherein the organic light emitting device comprises
a first light-emitting stack (first organic light-emitting layer 140, Fig. 1, [0031]) on the first electrode (first electrode 120, Fig. 1, [0031]) including a first emission layer (first emissive layer 141, Fig. 1, [0032]),
a first charge generation layer (first charge generation layer (CGL) 170, Fig. 1, [0031])on the first light-emitting stack (first organic light-emitting layer 140, Fig. 1); and
a second light-emitting stack (second organic light-emitting layer 150, Fig. 1, [0031]) between the first charge generation layer (first charge generation layer (CGL) 170, Fig. 1) and the second electrode (second electrode 130, Fig. 1, [0031]) and including a second emission layer (second emissive layer 151, Fig. 1, [0031]).
Youn further discloses that the tandem OLED structure disclosed by Youn lowers the driving voltage and improves the power efficiency of the OLED ([0017]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the light emitting structure in the display device of Jeong in view of Lee-248 analogous to the light emitting structure of Youn, and therefore a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the organic layer in the display device of Jeong in view of Lee-248 with the organic layer stacks of Youn to obtain a display device with improved power efficiency and lower driving voltage.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2021/0216157 A1) as applied to claims 1, 11-13, 16-18, 21, and 23 above, and further in view of Kwon (US 2019/0207150 A1).
Regarding claim 19, while Jeong teaches the display device of claim 1,
Jeong is silent about the location of an active voltage line, and therefore, does not teach that
the circuit layer further includes an active voltage line overlapping a portion of the plurality of pixel regions in the plan view, and
the shielding pattern is electrically connected to the active voltage line through a shielding contact hole defined in at least one of the plurality of insulating layers.
Kwon, on the other hand, teaches a display device (light emitting display device, Figs. 1-2, [0012]-[0013]), wherein
the circuit layer (comprising buffer layer 112 ([0037], insulating interlayer 113, [0037], passivation film 114, [0064], Fig. 2) further includes an active voltage line (cathode power line CPL, which is analogous to the common voltage ELVSS connected to common electrode E2 of Jeong, Fig. 2, [0059]) overlapping a portion of the plurality of pixel regions (sub pixel area PA, Fig. 2, [0035]) in the plan view, and
the shielding pattern (cathode electrode CE, which is analogous to common electrode E2 of Jeong ([0109]: common electrode is a cathode) as cathode electrode is a power line not connected to the transistor) is electrically connected to the active voltage line (cathode power line CPL, Fig. 2) through a shielding contact hole (cathode contact hole CH2, Fig. 2, [0066]) defined in at least one of the plurality of insulating layers (through the planarization layer 120 and the passivation film 114, Fig. 2, [0066]).
Kwon further teaches that luminescence uniformity may be degraded due to voltage drop of a cathode voltage caused by high resistance cathode electrode ([0007]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to deliver the voltage to the cathodes of the LEDs in the display device of Jeong by forming a voltage/power line under each pixel area, as taught by Kwon, which would reduce the voltage drop in the cathode electrode (common electrode E2) and provide luminescence uniformity. Thus, the combination of Jeong and Kwon further meets the limitations of the display device of claim 1, wherein
the circuit layer further includes an active voltage line overlapping a portion of the plurality of pixel regions in the plan view, and
the shielding pattern is electrically connected to the active voltage line through a shielding contact hole defined in at least one of the plurality of insulating layers.
Regarding claim 20, Jeong in view of Kwon teaches the display device of claim 19, wherein
the combination of Jeong and Kwon further teaches that
a first region (a region within a pixel area chosen around a shielding contact hole, Jeong’s Fig. 6 modified according to Kwon’s Fig. 2) having a first unit area size and a second region (a region of the same size in the non-pixel area nor containing a hole, Fig. 6) having a second unit area size that is equal to the first unit area size and spaced apart from the first region are defined in the base layer (substrate SB, Fig. 6 of Jeong), and
a number of shielding contact holes (one) defined in the first region (first region as defined above) and a number of shielding contact holes (zero) defined in the second region (second region as defined above) are different from each other.
Claims 23 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2021/0216157 A1) in view of Lee (US 2020/0235172 A1).
Regarding claim 23, Jeong teaches an electronic device (display device 1, Fig. 1. [0062]) comprising:
a display module (second display area DA2, Fig. 3, [0066]) having a plurality of pixel regions (second pixel areas PA2, Figs. 3-4, [0076]) including:
a first pixel region (second pixel area PA2 on the left in Fig. 6) configured to display a first light (green G, Fig. 4, [0089]: “second pixel area PA2 may include the pixels R, G, and B.”, and therefore each pixel region is configured to display all three wavelengths) having a first wavelength (green light corresponds to a specific wavelength range which is different than the wavelengths of other colors);
a second pixel region (second pixel area PA2 on the right in Fig. 6) adjacent to the first pixel region (second pixel area PA2 on the left in Fig. 6) and configured to display a second light (blue B, Fig. 4, [0089]: “second pixel area PA2 may include the pixels R, G, and B.”, and therefore each pixel region is configured to display all three wavelengths) having a second wavelength different (blue light corresponds to a specific wavelength range which is different than the wavelengths of other colors) from the first wavelength (wavelength of green light); and
a non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Figs. 4-6, [0076]) surrounding the plurality of pixel regions (second pixel areas PA2 comprising pixels PX, Fig. 4-6);
a window (while Jeong does not explicitly disclose a window, Jeong discloses that the display area DA corresponds to a screen in the display device 1 (Fig. 1) taught by Jeong ([0064]: “The display area DA may correspond to a screen.”). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the display device 1 comprises a window as a display screen)) on the display module (second display area DA2); and
wherein the display module (second display area DA2, Figs. 4-6) comprises:
a base layer (substrate SB, Fig. 6, [0070]) having a plurality of pixel regions (second pixel areas PA2, Figs. 4-6) including:
a first pixel region (second pixel area PA2 on the left in Fig. 6);
a second pixel region (second pixel area PA2 on the right in Fig. 6) adjacent to the first pixel region (second pixel area PA2 on the left in Fig. 6); and
a non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Figs. 4-6, [0076]) surrounding the plurality of pixel regions (second pixel areas PA2 comprising pixels PX, Fig. 4-6);
a circuit layer (comprising first insulating layer IN1 ([0095]), second insulating layer IN2 ([0097]) and third insulating layer IN3 ([0099]) containing the capacitor CP ([0088] and the transistor TR ([0088]); labeled as circuit layer in Illustrative Fig. 4, which is an annotated version of Fig. 6) on the base layer (substrate SB, Illustrative Fig. 4) and including a plurality of insulating layers (first insulating layer IN1, second insulating layer IN2, and third insulating layer IN3; Illustrative Fig. 4) and a plurality of conductive patterns (capacitor CP, transistor TR, data line DL, and parts of the common electrode E2; Illustrative Fig. 4, [0088]-[0089]);
a light-emitting element layer (see light emitting-layer including emission layer EL, Illustrative Fig. 4, [0104]) on the circuit layer (circuit layer, Illustrative Fig. 4); and
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an input sensing unit (touch electrode sections TES, Illustrative Fig. 4, [0113]) on the light-emitting element layer (light emitting-layer, Illustrative Fig. 4) and including a sensing pattern (touch electrode TE, Illustrative Fig. 4 and Fig. 5) overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, see Fig. 5 showing that the touch electrodes TE pass through the non-pixel area between transmissive areas (TA)),
wherein the light-emitting element layer (light emitting-layer, Illustrative Fig. 1) comprises:
a pixel defining structure (fourth insulating layer IN4 and opening OP, Illustrative Fig. 4, [0102]) overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Illustrative Fig. 4: some portion of the fourth insulating layer IN4 is in the transmissive area TA) and having pixel openings (opening OP, Illustrative Fig. 4, [0102]) corresponding to the plurality of pixel regions (second pixel areas PA2, Illustrative Fig. 4) respectively; and
light-emitting elements (light emitting diodes LED, Illustrative Fig. 4 (see also Fig. 5), [0091]) at least partially in the pixel openings (opening OP, Illustrative Fig. 4),
wherein the pixel defining structure (fourth insulating layer IN4 and opening OP, Illustrative Fig. 4) includes a step pattern (the openings in fourth insulating layer IN4 at the edges of opening OPN, labeled as opening 2 in Illustrative Fig. 4 (see also Fig. 5 for to view), [0104]) overlapping the non-pixel region (comprising areas surrounding the pixel regions PA2, which includes transmissive areas TA and regions between transmissive areas TA, Fig. 5 and Illustrative Fig. 4: opening OPN is in the transmissive area TA) and surrounding a portion of each of the plurality of pixel regions (second pixel area PA2, Fig. 5: openings OPN surround the pixel regions PA2, therefore the step patterns surround the pixel regions), and
the plurality of conductive patterns (capacitor CP, transistor TR, data line DL, and parts of the common electrode E2; Illustrative Fig. 4) include a shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 4, [0106]: “The common electrode E2 may extend along a side surface of the fourth insulating layer IN4 to an edge of the transmissive area TA to sufficiently shield the data line DL.“) overlapping the step pattern (parts of the common electrode E2 is in the opening 2, Illustrative Fig. 4) in a plan view (see Fig. 5 for plan view), at least a portion of the shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 4) being configured to have a voltage applied thereto ([0107]: ”The common electrode E2 may be provided in common to all the pixels PX, and may receive a common voltage ELVSS“), the at least the portion of the shielding pattern (the extension of the common electrode E2 on the side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Fig. 4) having a shape corresponding to the step pattern (see Fig. 5 and [0105]: the shielding portion of the common electrode E2 forms the portion of the non-pixel region around the transmissive areas TA, and therefore has the shape of the non-pixel areas around the transmissive regions TA) along a plurality of edges of a pixel region (Fig. 5: the shielding portion of the common electrode E2 surrounds second pixel regions PA2 along four sides/edges), from among the first (second pixel area PA2 on the left in Illustrative Fig. 4 and on the cross-section line A-A’ in Fig. 5) and second pixel regions (second pixel area PA2 on the right in Illustrative Fig. 4 and on the cross-section line A-A’ in Fig. 5), in the plan view (see Fig. 5 for plan view).
Jeong, however, does not teach
an external case under the display module.
Lee-172, on the other hand, teaches an electronic device (light emitting display device, Fig. 1, [0069]) comprising a display module (display unit, Figs. 3-8, [0039]) including:
an external case under the display module ([0070]: “The display device may be used in portable electronic devices such as a mobile phone, a smartphone, a tablet personal computer (PC), a smart watch, …”, therefore it would have an external case under the display module to cover the electronics).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the display modules of Jeong is analogous to the display module of Lee-172, and therefore a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use the display module of Jeong in portable electronic devices such as a mobile phone, a smartphone, a tablet personal computer (PC), a smart watch, and therefore include an external case under the display module.
Thus, the combination of Jeong and Lee-172 meets all the limitations of claim 23.
Allowable Subject Matter
Claims 5-8 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5, disclosing the limitation that “a thickness of the second electrode portion is smaller than a thickness of the first electrode portion”, would be allowable if this limitation is incorporated in a claim combining claims 1-3 and 5.
Regarding the closest prior art, the combination of Jeong and Lee-248 teaches all the limitations of the display device of claim 3 (see claim 1-3 rejections above) and further teaches the second electrode (common electrode E2, Illustrative Fig. 1) comprises:
a first electrode portion on the upper surface of the pixel defining layer (fourth insulating layer IN4, Illustrative Fig. 1); and
a second electrode portion on the inner side surface of the step pattern (the side surface of the fourth insulating layer IN4, Illustrative Fig. 1).
The combination of Jeong and Lee-248, however, fail to teach that
a thickness of the second electrode portion is smaller than a thickness of the first electrode portion.
There has been no prior art identified that can modify Jeong in view of Lee-248 further to teach the limitation that “a thickness of the second electrode portion is smaller than a thickness of the first electrode portion”.
Therefore, claim 5 is objected as it depends on rejected claims 1-3.
Claim 6, disclosing the limitation that “the pixel defining structure further includes a dummy portion on the pixel defining layer and partially overlapping the step pattern in the plan view”, would be allowable if this limitation is incorporated in a claim combining claims 1-3 and 6.
Regarding the closest prior art, the combination of Jeong and Lee-248 teaches all the limitations of the display device of claim 3 (see claim 1-3 rejections above), but fails to teach the limitation above.
There has been no prior art identified that can modify Jeong in view of Lee-248 further to teach the limitation that “the pixel defining structure further includes a dummy portion on the pixel defining layer and partially overlapping the step pattern in the plan view”.
Therefore, claim 6 is objected as it depends on rejected claims 1-3.
Claim 7, disclosing the limitation that “step pattern includes a side surface on the pixel defining layer and having an inversely tapered shape from an upper surface of the pixel defining layer”, would be allowable if this limitation is incorporated in a claim combining claims 1-2 and 7.
Regarding the closest prior art, the combination of Jeong and Lee-248 teaches all the limitations of the display device of claim 3 (see claim 1-3 rejections above), and further teaches that
the pixel defining structure (comprising fourth insulating layer IN4 and opening OP, Illustrative Fig. 1) further includes a pixel defining layer (fourth insulating layer IN4, Illustrative Fig. 1) overlapping the non-pixel region (Illustrative Fig. 1: a portion of the fourth insulating layer IN4 is in the non-pixel region).
The combination of Jeong and Lee-248, however, fail to teach that
the step pattern includes a side surface on the pixel defining layer and having an inversely tapered shape from an upper surface of the pixel defining layer.
The current application provides a rationale for forming an inversely tapered structure which the reduction of leakage current ([0212]). Therefore, the inversely tapered shape is not a design choice or an arbitrary form. There has been no rationale to form the step pattern in inversely tapered form in Jeong in view of Lee-248. Furthermore, there has been no prior art identified that can modify Jeong in view of Lee-248 due to any reason to teach the limitation that “the step pattern includes a side surface on the pixel defining layer and having an inversely tapered shape from an upper surface of the pixel defining layer”.
Therefore, claim 7 is objected as it depends on rejected claims 1-2.
Claim 8 is also objected because claim 8 depend on claim 7.
Claim 14, disclosing the limitation that “the circuit layer further includes a dummy shielding pattern in a same layer as the shielding pattern, spaced apart from the shielding pattern, and surrounding any one of the plurality of pixel regions”, would be allowable if this limitation is incorporated in a claim combining claims 1, 11, and 14.
Regarding the closest prior art, Jeong teaches all the limitations of the display device of claim 11 (see claim 1 and claim 11 rejections above), but fails to teach the limitations that
the circuit layer further includes a dummy shielding pattern in a same layer as the shielding pattern, spaced apart from the shielding pattern, and surrounding any one of the plurality of pixel regions.
There has been no prior art identified that can modify Jeong further to teach the limitation that the circuit layer further includes a dummy shielding pattern in a same layer as the shielding pattern, spaced apart from the shielding pattern, and surrounding any one of the plurality of pixel regions. Therefore, claim 14 is objected as it depends on rejected claim 11.
Claim 15, disclosing the limitation that “the shielding pattern … does not overlap the second step pattern in the plan view”, would be allowable if this limitation is incorporated in a claim combining claims 1, 11, and 15.
Regarding the closest prior art, Jeong teaches all the limitations of the display device of claim 11 (see claim 1 and claim 11 rejections above), and further teaches that
the shielding pattern (the extension of the common electrode E2 on the top and side surfaces of fourth insulating layer IN4 and on the top surface of second insulating layer IN2, Illustrative Figs. 1-2) overlaps the first step pattern (first step pattern, Illustrative Fig. 2).
Jeong, however, fails to teach that the shielding pattern does not overlap the second step pattern in the plan view.
There has been no prior art identified that can modify Jeong further to teach the limitation that the shielding pattern does not overlap the second step pattern in the plan view. Therefore, claim 15 is objected as it depends on rejected claim 11.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 11, and 22-23 per response dated on 4/2/2026.
Applicant's arguments with respect to claims have been fully considered. The Examiner agrees with the Applicant on that the amendments to independent claims 1, 22, and 23 overcame the rejections made on these claims previously based on the prior art Lee-172 (US 2020/0235172 A1) and Lee-733 (US 2021/0132733 A1).
However, amended claims 1 and 22 are now rejected under new grounds based on a new prior-art, Jeong (US 2017/0287784 A1), and claim 23 is rejected based on Jeong and Lee-172 in the current office action. Rejections are also made on claims 2-4, 9-13 and 16-23 based on Jeong or its combination with other prior art. The rejection on claim 5-8 and 14-15, however, are withdrawn, because there is no prior-art identified that made these claims anticipated or obvious after amending the claim 1. Claims 5-8 and 14-15 are now objected due to their direct or indirect dependency on claim 1 as detailed in the office action above.
For the purpose of compact prosecution, the Examiner notes that incorporating limitations of objected claims with independent claim 1 will render claim 1 allowable. Regarding independent claims 22-23, incorporating limitations describing the structure and organization of layers, such as the ones disclosed in objected claims, might also render claims 22 and 23 to overcome their corresponding rejections based on prior art of record.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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