Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to Applicant’s claim of priority to Chinese application CN202310150318.7 filed February 21, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed December 8, 2025. Claims 1, 5, 7-9 and 11 are amended. Claims 2-4 and 10 are cancelled. The Examiner notes that claims 1, 5-9, and 11 are examined.
Drawings
The drawings were received on December 8, 2025. These drawings are acceptable. Objections to the drawing are withdrawn.
Specification
The substitute specification filed December 8, 2025 has been entered. The objection to the specification is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 is rejected under 35 U.S.C. 103 as being unpatentable over Boher (Thin Solid Films, 1997) in view of Hiroshi (US 6025596 A), An (Applied Surface Science, 2021) and Kang (US 2012/0171797 A1).
With respect to claim 1, Boher teaches:
A method for measuring a thickness of a silicon epitaxial layer, comprising:
step 1: providing a first wafer having a first silicon substrate (first Si of an Si/SiGe/Si structure),
and performing epitaxial growth to grow a first semiconductor material layer on a surface of the first wafer in a first epitaxy equipment (SiGe layer, referred to as an epitaxial structure in the conclusion and introduction, using epitaxy equipment to deposit an epitaxial layer is implicit),
wherein a material of the first semiconductor material layer is optically distinguishable from a silicon film (Boher teaches spectroscopic ellipsometry and grazing X-ray reflectance to distinguish thicknesses of the SiGe and top Si layer, both of which are optical measurements);
wherein the material of the first semiconductor material layer comprises SiGe (SiGe layer of the Si/SiGe/Si heterostructure)
step 2: performing an epitaxial growth to grow a first silicon epitaxial layer on a surface of the first semiconductor material layer in the first epitaxy equipment (top Si layer, structure referred to as an epitaxial structure in introduction and conclusion);
step 3: measuring a first thickness of the first silicon epitaxial layer by using the first semiconductor material layer as a backing layer to obtain a first thickness of the first silicon epitaxial layer (section 3.2, “Analysis of bilayer structure” teaches the use of GXR (Fig. 2) and SE (Fig. 3) to measure the thickness of the top silicon layer on SiGe);
Boher fails to teach:
performing an epitaxial growth to grow a first silicon epitaxial layer on a surface of the first semiconductor material layer in the first epitaxy equipment (Boher does not specify whether or not the SiGe and Si are deposited in the same epitaxial equipment
step 4: performing epitaxial growth in a second epitaxy equipment to form a second silicon epitaxial layer on a surface of the first silicon epitaxial layer,
wherein the second silicon epitaxial layer is the silicon epitaxial layer;
and step 5: measuring a second thickness by using the first semiconductor material layer as a backing layer, wherein the second thickness is a superimposed thickness of the first silicon epitaxial layer and the second silicon epitaxial layer,
and subtracting the first thickness from the superimposed thickness to obtain the thickness of the silicon epitaxial layer.
Hiroshi teaches in Fig. 16:
step 3: measuring a first thickness of silicon by using the first semiconductor material layer as a backing layer to obtain a first thickness of the first silicon epitaxial layer (col. 3, lns. 28-30 “only a first layer is epitaxially grown and then the film thickness thereof is measured as the thickness of the first layer by the FTIR method”)
step 4: performing epitaxial growth in a to form a second silicon epitaxial layer on a surface of the first silicon epitaxial layer (col. 3 “30-32“a first layer and a second layer are continuously epitaxially grown under the same condition as the case where only the first layer is formed”),
wherein the second silicon epitaxial layer is the silicon epitaxial layer;
and step 5: measuring a second thickness of silicon by using the first semiconductor material layer as a backing layer, wherein the second thickness is a superposed thickness of the first silicon epitaxial layer and the second silicon epitaxial layer (col. 3 ln. 33-34, “the total film thickness of the first layer and the second layer are measured by the FTIR method”)
and subtracting the first thickness from the superimposed thickness to obtain the thickness of the silicon epitaxial layer (col. 3, ln 34-36 “and the subtraction of the film thickness between the above two samples is calculated as the film thickness of the second layer”).
Boher discloses the claimed invention except for the adding a second silicon layer and measuring it by measuring the two silicon layer combined and subtracting the thickness of the first one. Hiroshi teaches that it is known to find the thickness of a silicon layer in a multilayer stack of silicon layers by measuring one layer on its own, measuring two layers together, and subtracting them. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to measure the thickness of the silicon layer as taught by Hiroshi, since Hiroshi states at column 3, lines 30-36 that such a modification would allow for the measurement of silicon layers that are otherwise optically indistinguishable. See MPEP 2144.
An teaches:
performing an epitaxial growth to grow a first silicon epitaxial layer on a surface of the first semiconductor material layer in the first epitaxy equipment (Section 2 “Experiments” III. “In the third engineering method an interfacial heteroepitaxial SiGe layer was grown in the same PECVD reactor prior to bulk epitaxial Si growth, where 1 SCCM of GeH4 with a dilution of 1 at.% in H2 is added to the same growth condition as for the bulk Si epitaxy, for a growth time of 2 min followed by PECVD epitaxial growth (sample E). “)
It would have been obvious to one of ordinary skill in the art at the time of the invention to grow SiGe and first Si epitaxial layers on an Si substrate in-situ with the same equipment because the known technique taught by An was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Boher/Hiroshi/An does not teach that the second silicon epitaxial layer is grown in a second epitaxy equipment.
Kang teaches that it is known to deposit first and second epitaxial layers in different deposition chambers in order to avoid cross contamination. Therefore, it would be obvious over Kang:
performing epitaxial growth in a second epitaxy equipment to form a second silicon epitaxial layer on a surface of the first silicon epitaxial layer (para. 14 “In an embodiment, a multi-chambered growth process separates or "splits" growths of different LED film stack layers into different chambers, for example, to avoid cross contamination between dopant species, such as between In and Mg and between Mg and Si.” Para. 17 “Embodiments of multi-chambered deposition systems include a first deposition chamber to grow a first epitaxial layer over a substrate, the first epitaxial layer containing a dopant, a second deposition chamber to grow second epitaxial layer over the substrate”)
It would have been obvious to one of ordinary skill in the art at the time of the invention to grow the second Si layer in a second epitaxial equipment in order to avoid contamination of Ge in the first chamber because the known technique taught by Kang to transfer epitaxial layered stacks to a second chamber to avoid contamination from the materials in the first chamber was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Boher (Thin Solid Films, 1997), Hiroshi (US 6025596 A), An (Applied Surface Science, 2021) and Kang (US 2012/0171797 A1) as applied to claim 1 above and further in view of Jung (Materials, 2021) as evidenced by Ogawa (Japanese Journal of Applied Physics, 2002).
With respect to claim 5, Boher/Hiroshi/An/Kang teach all limitations of claim 4 upon which claim 5 depends. Boher/Hiroshi/An/Kang fail to teach:
the second epitaxy equipment comprises a pre-cleaning chamber and an epitaxial growth chamber, and
wherein, before performing the epitaxial growth of the second silicon epitaxial layer,
the method further comprises a step of placing the first wafer into the pre-cleaning chamber for a dry chemical pre-cleaning,
wherein during the dry chemical pre-cleaning,
the first silicon epitaxial layer covers the first semiconductor material layer and prevents the Ge in the first semiconductor material layer from contaminating the pre-cleaning chamber.
Jung teaches:
the Si epitaxy equipment comprises a pre-cleaning chamber and an epitaxial growth chamber (see Fig. 1, Ex-situ Dry cleaning and process chamber are different chambers);
wherein before performing the epitaxial growth of the second silicon epitaxial layer,
the method further comprises a step of placing the first wafer into the pre-cleaning chamber for a dry chemical pre-cleaning (ex-situ dry cleaning chamber),
Ogawa shows in Fig. 7 that the process of using hot NH3 and NF3 to clean an epitaxial surface removes an oxide from an exposed silicon surface and only acts on the exposed surface. Applying the method of Jung to the heterostructure of Boher/Hiroshi/An to preclean before depositing would result in the first epitaxial layer covering the first semiconductor material layer to prevent Ge from contaminating the precleaning chamber. Therefore, Boher/Hiroshi/An modified by Jung teaches:
wherein during the dry chemical pre-cleaning,
the first silicon epitaxial layer (top Si layer of the Si/SiGe/Si heterostructure of Boher) covers the first semiconductor material layer (SiGe layer) and prevents the Ge in the first semiconductor material layer from contaminating the pre-cleaning chamber (method of Jung applied to stack of Boher).
Boher/Hiroshi/An/Kang discloses the claimed invention except for the use of ex-situ precleaning that does not contaminate the precleaning chamber. Jung teaches that it is known to use a Si deposition chamber with separate precleaning and process chambers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to ex-situ preclean as taught by Jung as evidence by Ogawa for the purpose of removing oxide from the Si layer prior to further epitaxial growth. See MPEP 2144.
With respect to claim 6, Jung further teaches:
wherein reactants for the dry chemical pre-cleaning comprise NF3 and NH3 (pg. 3 “The ex-situ dry cleaning process was performed using NF3/NH3 plasma.”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Boher in view of Hiroshi, An, Kang, and Jung as explained above.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Boher (Thin Solid Films, 1997), Hiroshi (US 6025596 A), An (Applied Surface Science, 2021), Kang (US 2012/0171797 A1), and Jung (Materials, 2021) as evidenced by Ogawa (Japanese Journal of Applied Physics, 2002) as applied to claim 5 above and further in view of Thompson-048 (US 8,796, 048 B1).
With respect to claim 7, Boher/Hiroshi/An/Kang/Jung teaches all limitations of claim 5 upon which claim 7 depends. Boher/Hiroshi/An/Kang/Jung fail to teach:
further comprising providing a second wafer in the second epitaxy equipment
wherein, in step 5,
in a case that the second thickness meets a product thickness requirement,
an epitaxial growth is directly performed on the second wafer in the second epitaxy equipment to form a third silicon epitaxial layer on the second wafer,
wherein epitaxial growth parameters for the third silicon epitaxial layer are the same as epitaxial growth parameters for the second silicon epitaxial layer,
and wherein the first wafer is a measurement wafer and the second wafer is a product wafer.
Thompson-048 teaches a method of calibrating epitaxial processes by measuring thickness on a test substrate and applying data during the production phase in col. 11, lns. 50-64:
“Accordingly in these embodiments, other techniques can be utilized at steps 420 and 425 to obtain thickness information. For example, measurement wafers with features that can be measured via ellipsometry or profilometry, as previously described, can be run concurrently with the test substrates or using a same process as a test substrate to obtain thickness data for the correlation. Any other methods can also be used in the various embodiments. In particular, destructive and time-consuming methods can be used during this calibration. After the completion of the calibration phase, the collected data can be used during an estimation or production phase, as described below with respect to FIG. 4B.”
Applying the teachings of Thompson-048 to the process of Boher/Hiroshi/An/Jung to use the wafer of Boher/Hiroshi/An/Kang/Jung as a measurement wafer that is used to calibrate a production wafer renders obvious:
further comprising providing a second wafer in the second epitaxy equipment (“production substrate” of Thompson-048)
Wherein, in step 5,
in a case that the second thickness meets a product thickness requirement (using the process to obtain a target thickness on a precursor substrate, step 410, see Fig. 4A),
an epitaxial growth is directly performed on the second wafer in the second epitaxy equipment to form a third silicon epitaxial layer on the second wafer,
wherein epitaxial growth parameters for the third silicon epitaxial layer are the same as epitaxial growth parameters for the second silicon epitaxial layer (Fig. 4B, step 430 “applying the process for a target thickness to a production substrate”),
and wherein the first wafer is a measurement wafer (measurement wafer of Thompson-048) and the second wafer is a product wafer (“production substrate”).
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the substrate as a measurement substrate to calibrate a process and apply the method to a product substrate because the known technique taught by Thompson-048 was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 8, the above teaching of Thompson-048 teaches that calibration can involve measuring multiple substrates to evaluate a process window in col. 11, lns. 36-40:
“As a result of step 420, a set of test wafers is produced that can be used to evaluate a process window to the thin film. More importantly, the test substrates can be used to evaluate the effects on process variations on the filling or closing of the trenches in the identified trench line structure.”
The above teaching of Thompson-048 teaches that multiple test wafers are used to evaluate a process window, implicitly teaching that if thicknesses are unacceptable additional wafers will be tested, therefore Thompson-048 renders obvious:
in a case that the second thickness does not meet the product thickness requirement,
the epitaxial growth parameters of the second epitaxy equipment are adjusted,
and the step 1 to the step 5 are repeated until the second thickness meets the product thickness requirement.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Boher/Hiroshi/An/Kang/Jung in view of Thompson-048 as explained above.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Boher (Thin Solid Films, 1997), Hiroshi (US 6025596 A), An (Applied Surface Science, 2021), Kang (US 2012/0171797 A1), Jung (Materials, 2021) and Thompson-048 (US 8,796,048 B1) as evidenced by Ogawa (Japanese Journal of Applied Physics, 2002) as applied to claim 7 above and further in view of Thompson-498 (US 2011/0074498 A1).
With respect to claim 9, Boher/Hiroshi/An/Kang/Jung/Thompson-048 teaches all limitations of claim 7 upon which claim 9 depends. Boher/Hiroshi/An/Kang/Jung/Thompson-048 fails to teach:
wherein a well region is formed in a surface area of the second wafer,
and wherein the third silicon epitaxial layer is a forming layer of a channel region of a semiconductor device.
Thompson-498 teaches in Fig. 14:
wherein a well region (shallow P-well 1408 and/or shallow N-well 1410) is formed in a surface area of the second wafer,
and wherein the third silicon epitaxial layer is a forming layer of a channel region (of a semiconductor device (para. 149 “Undoped regions or low doped regions 1420, 1422 are then deposited on each of the threshold voltage tuning regions, which are doped over the NMOS V.sub.T tuning region 1416 and PMOS V.sub.T tuning region 1418. The method of epitaxial growth or other similar techniques may be used to deposit these un-doped or low-doped regions. Through the above steps, a channel complying with DDC is formed”.)
It would have been obvious to one of ordinary skill in the art at the time of the invention to adapt the epitaxial structure of Boher/Hiroshi/An/Kang/Jung/Thompson-048 to make a NMOS and PMOS with well and channel layers as taught by Thompson-498 because the market place reflects the reality that the use of multilayer silicon epitaxial structures to form PMOS and NMOS is commonplace and the invention as claimed would result from the application of the prior knowledge or known processes as demonstrated by Thompson-498 in a predictable manner. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Boher (Thin Solid Films, 1997), Hiroshi (US 6025596 A), An (Applied Surface Science, 2021), and Kang (US 2012/0171797 A1) as applied to claim 1 above and in view of theta-SE (J.A. Woollam brochure, 2022).
With respect to claim 11, Boher/Hiroshi/An/Kang teaches all limitations of claim 1 upon which claim 11 depends. Boher/Hiroshi/An/Kang fails to teach:
wherein in step 3,
a plurality of points is selected on the first wafer to measure the first thickness,
and wherein in step 5,
the plurality of points is selected on the first wafer to measure the superimposed thickness and obtain the second thickness at the plurality of points.
The theta-SE brochure teaches on the “Features” page that the ellipsometer is configured to scan the film thickness at points across the entire wafer theta-SE brochure therefore renders obvious:
wherein in step 3,
a plurality of points is selected on the first wafer to measure the first thickness,
and wherein in step 5,
the plurality of points is selected on the first wafer to measure the superimposed thickness and obtain the second thickness at the plurality of points.
It would have been obvious to one of ordinary skill in the art at the time of the invention to measure a plurality of points in able to measure the uniformity of the epitaxial layers as taught in the theta-SE brochure because measuring substrate thickness uniformity was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s arguments with respect to claim 1 and its dependents have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897