Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objection
Claims 1 and 5 are objected for claim language “focused in a region of a greater length beam…… and perpendicular to the advancing direction of the laser beam:” . Examiner suggests the applicant amend the claim by clarifying “and perpendicular to the advancing direction of the laser beam”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Harada et al. (US 2021/0074588, hereinafter Harada) in view of Marjanovic et al. (US 2015/0166395, hereinafter Marjanovic).
With respect to claim 1, Harada discloses a processing method of a substrate (Para 0001; processing method), the method performing processing of the substrate with use of a laser beam (Para 0003; applying laser beam to the wafer) having a wavelength that transmits through a material constituting the substrate (Para 0007; laser beam having a transmission wavelength to the wafer), the method comprising: a shield tunnel forming step of forming shield tunnels (Fig. 8B-C; Para 0033-0034; forming plurality of shield tunnels), each of which includes a fine pore opening in at least one of a front surface or a back surface of the substrate (Fig. 8B-8C) and an amorphous portion surrounding the fine pore (Para 0003; 0053; and 0060; This shield tunnel includes a fine hole extending along a thickness direction of the wafer and an amorphous region shielding the fine hole), by applying the laser beam to the substrate such that at least a part of the region is positioned inside the substrate (Para 0007; 0035); and a function layer (9 &11 of Fig. 10A – Para 0039; according to applicant’s specs para 0003; a functional layer can comprise of a conductor, semiconductor or insulating material) forming step of, after the shield tunnel forming step, forming a function layer on the front surface of the substrate (Para 0007; 0066; 0069 – the plural shield tunnels have already formed prior to forming 11).
Harada does not explicitly disclose that the laser beam is focused in a region of a greater length along a thickness direction of the substrate than a width along a direction perpendicular to the thickness direction and perpendicular to the advancing direction of the laser beam.
In an analogous art, Marjanovic discloses that the laser beam is focused in a region of a greater length along a thickness direction of the substrate than a width along a direction perpendicular to the thickness direction and perpendicular to the advancing direction of the laser beam (Para 0014, 0016 and 0071 - Fig. 2A-2B – length along a thickness direction is more than the width perpendicular to the thickness).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada’s method by having Marjanovic’s disclosure in order to improve the precision of the singulation process.
With respect to claim 11, Harada discloses wherein the function layer is part of a light-emitting diode (Para 0002 – LED).
With respect to claim 13, Harada discloses wherein the function layer includes a film selected from a list consisting of a conductive film, a semiconductor film, an insulation film, or any combination thereof (9 &11 of Fig. 10A – Para 0035-0036; polyolefin sheet is an insulator).
Claims 2, 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Harada/Marjanovic in view of Morikazu et al. (US 2016/0260630, hereinafter Morikazu).
With respect to claim 2, Harada/Marjanovic discloses the processing method according to claim 1.
Harada/Marjanovic does not explicitly disclose that the processing method further comprising: between the shield tunnel forming step and the function layer forming step, an etching step of etching the shield tunnels from the at least one of the front surface or the back surface, the at least one having the fine pore opening therein.
In an analogous art, Morikazu discloses between the shield tunnel forming step and the function layer forming step, an etching step of etching the shield tunnels from the at least one of the front surface or the back surface, the at least one having the fine pore opening therein.
In an analogous art, Morikazu discloses between the shield tunnel forming step (Fig. 9C-9D and the function layer (400 of Fig. 10) forming step, an etching step of etching the shield tunnels from the at least one of the front surface or the back surface, the at least one having the fine pore opening therein (Fig. 4C & 4D Fig. 10; Para 0090; etching happens after forming shield tunnel but before forming layer 400).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada’s method by having Morikazu’s disclosure in order to divide the substrate reliably into individual chips.
With respect to claim 5, Harada discloses a manufacturing method of chips (Para 0001; processing method), the method performing manufacture of the chips from a substrate (Para 0001-0002 and 0004) with use of a laser beam (Para 0003; applying laser beam to the wafer) having a wavelength that transmits through a material constituting the substrate (Para 0007; laser beam having a transmission wavelength to the wafer) and focused in a region of a greater length along a thickness direction of the substrate than a width along a direction perpendicular to the thickness direction (Fig. 8B ; Para 0061– laser beam is focused along thickness direction which is longer than the width of the slit perpendicular to the thickness), the method comprising:
a shield tunnel forming step of forming shield tunnels (Fig. 8B-C; Para 0033-0034; forming plurality of shield tunnels), each of which includes a fine pore opening in at least one of a front surface or a back surface of the substrate (Fig. 8B-8C) and an amorphous portion surrounding the fine pore (Para 0003; 0053; and 0060; This shield tunnel includes a fine hole extending along a thickness direction of the wafer and an amorphous region shielding the fine hole), by applying the laser beam to the substrate such that at least a part of the region is positioned inside the substrate (Para 0003; 0007; 0035); and
forming a function layer (9 & 11 of Fig. 10A; Para 0007; 0066 and 0069) on the front surface of the substrate (9 &11 of Fig. 10A – Para 0039; according to applicant’s specs para 0003; a functional layer can comprise of a conductor, semiconductor or insulating material); and a dividing step of, after the function layer forming step, dividing the substrate by applying an external force to the substrate (Para 0067).
Harada does not explicitly disclose that the laser beam is focused in a region of a greater length along a thickness direction of the substrate than a width along a direction perpendicular to the thickness direction and perpendicular to the advancing direction of the laser beam.
In an analogous art, Marjanovic discloses that the laser beam is focused in a region of a greater length along a thickness direction of the substrate than a width along a direction perpendicular to the thickness direction and perpendicular to the advancing direction of the laser beam (Para 0014, 0016 and 0071 - Fig. 2A-2B – length along a thickness direction is more than the width perpendicular to the thickness).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada’s method by having Marjanovic’s disclosure in order to improve the precision of the singulation process.
Harada/Marjanovic does not explicitly disclose an etching step of, after the shield tunnel forming step, etching the shield tunnels from the at least one of the front surface or the back surface, the at least one having the fine pore opening therein; a function layer forming step of, after the etching step.
In an analogous art, Morikazu discloses an etching step of, after the shield tunnel forming step, etching the shield tunnels from the at least one of the front surface or the back surface (Fig. 4C & 4D, Fig. 10; Para 0090; etching happens after forming shield tunnel but before forming layer 400), the at least one having the fine pore opening therein (Para 0010 and 0013); a function layer (400 of Fig. 10) forming step of, after the etching step (layer 400 is formed in the etched regions which implies that layer 400 is formed after etching).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic’s method by having Morikazu’s disclosure in order to divide the substrate reliably into individual chips.
With respect to claim 12, Harada/Marjanovic discloses the processing method according to claim 1.
Harada/Marjanovic does not explicitly disclose wherein the function layer is part of a laser diode.
In an analogous art, Morikazu discloses wherein the function layer is part of a laser diode (Para 0004 – laser diode).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic’s method by having Morikazu’s disclosure in order to manufacture a light emitting diode.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over
Harada/Marjanovic in view of Hiroshi Morikazu (US 2017/0221763, hereinafter Hiroshi).
With respect to claim 3, Harada/Marjanovic discloses the processing method according to claim 1.
Harada/Marjanovic does not explicitly disclose wherein the fine pore opens in only one of the front surface or the back surface of the substrate.
In an analogous art, Hiroshi discloses wherein the fine pore opens in only one of the front surface or the back surface of the substrate (Para 0134).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic’s method by having Hiroshi’s disclosure in order to improve the dicing process to minimize the damage to the dies.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Harada/Marjanovic/Morikazu in view of Hiroshi Morikazu (US 2017/0221763, hereinafter Hiroshi).
With respect to claim 4, Harada/Marjanovic/Morikazu discloses the processing method according to claim 2.
Harada/Marjanovic/Morikazu does not explicitly disclose wherein the fine pore opens in only one of the front surface or the back surface of the substrate.
In an analogous art, Hiroshi discloses wherein the fine pore opens in only one of the front surface or the back surface of the substrate (Para 0134).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic/Morikazu’s method by having Hiroshi’s disclosure in order to improve the dicing process to minimize the damage to the dies.
With respect to claim 6, Harada/Marjanovic/Morikazu discloses the processing method according to claim 5.
Harada/Marjanovic/Morikazu does not explicitly disclose wherein the fine pore opens in only one of the front surface or the back surface of the substrate.
In an analogous art, Hiroshi discloses wherein the fine pore opens in only one of the front surface or the back surface of the substrate (Para 0134).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic/Morikazu’s method by having Hiroshi’s disclosure in order to improve the dicing process to minimize the damage to the dies.
Claim 7-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Harada/Marjanovic in view of Takeda et al. (US 2014/0334511, hereinafter Takeda).
With respect to claim 7, Harada/Marjanovic discloses the processing method according to claim 1.
Harada/Marjanovic does not explicitly disclose wherein the function layer is made of a single metal film.
In an analogous art, Takeda discloses wherein the function layer is made of a single metal film (Para 0004 – functional layer comprises of ICs, it’s obvious to one of any ordinary skilled in the art that IC can comprise of a metal). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic’s method by having Takeda’s disclosure in order to manufacture different semiconductor devices.
With respect to claim 8, Harada/Marjanovic discloses the processing method according to claim 1.
Harada/Marjanovic does not explicitly disclose wherein the function layer is made of a plurality of thin metal films.
In an analogous art, Takeda discloses wherein the function layer is made of a plurality of thin metal films (Para 0004 – functional layer comprises of ICs, it’s obvious to one of any ordinary skilled in the art that IC can comprise of layers of thin metal films). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic’s method by having Takeda’s disclosure in order to manufacture different semiconductor devices.
With respect to claim 10, Harada/Marjanovic discloses the processing method according to claim 1.
Harada/Marjanovic does not explicitly disclose wherein the function layer is part of an integrated circuit.
In an analogous art, Takeda discloses wherein the function layer is part of an integrated circuit. (Para 0004 – functional layer comprises of ICs). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic’s method by having Takeda’s disclosure in order to manufacture different semiconductor devices.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Harada/Marjanovic/Takeda in view of Kishimoto (US 2022/0093579, hereinafter Kishimoto).
With respect to claim 9, Harada/Marjanovic/Takeda discloses the processing method according to claim 8.
Harada/Marjanovic/Takeda does not explicitly disclose wherein the plurality of thin metal films are patterned using at least one of photolithography or etching.
In an analogous art, Kishimoto discloses wherein the plurality of thin metal films are patterned using at least one of photolithography or etching (Para 0133, 0150, 0165-0166). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic/Takeda’s method by having Kishimoto’s disclosure in order to improve the precision of patterning process.
Claims 14-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Harada/Marjanovic/Morikazu in view of Takeda.
With respect to claim 14, Harada/Marjanovic/Morikazu discloses the processing method according to claim 5.
Harada/Marjanovic/Morikazu does not explicitly disclose wherein the function layer is part of an integrated circuit.
In an analogous art, Takeda discloses wherein the function layer is part of an integrated circuit. (Para 0004 – functional layer comprises of ICs). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic/Morikazu’s method by having Takeda’s disclosure in order to manufacture different semiconductor devices.
With respect to claim 15, Harada/Marjanovic/Morikazu discloses the manufacturing method according to claim 5.
Harada/Marjanovic/Morikazu does not explicitly disclose wherein the function layer is made of a single metal film.
In an analogous art, Takeda discloses wherein the function layer is made of a single metal film (Para 0004 – functional layer comprises of ICs, it’s obvious to one of any ordinary skilled in the art that IC can comprise of a metal). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic/Morikazu’s method by having Takeda’s disclosure in order to manufacture different semiconductor devices.
With respect to claim 16, Harada/Marjanovic/Morikazu discloses the manufacturing method according to claim 5.
Harada/Marjanovic/Morikazu does not explicitly disclose wherein the function layer is made of a plurality of thin metal films.
In an analogous art, Takeda discloses wherein the function layer is made of a plurality of thin metal films (Para 0004 – functional layer comprises of ICs, it’s obvious to one of any ordinary skilled in the art that IC can comprise of layers of thin metal films). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic’s method by having Takeda’s disclosure in order to manufacture different semiconductor devices.
With respect to claim 18, Harada/Marjanovic/Morikazu discloses the manufacturing method according to claim 5.
Harada/Marjanovic/Morikazu does not explicitly disclose wherein: the function layer comprises a metal layer; and in the dividing step, both the substrate and the metal layer are divided by applying the external force.
In an analogous art, Takeda discloses wherein: the function layer comprises a metal layer (Para 0004 – functional layer comprises of ICs, it’s obvious to one of any ordinary skilled in the art that IC can comprise of a metal); and in the dividing step, both the substrate and the metal layer are divided by applying the external force (Para 0005; 0029 – it’s obvious if there is IC comprising a metal on the wafer then during cutting substrate and metal layer will be diving by applying external force). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic/Morikazu’s method by having Takeda’s disclosure in order to manufacture different semiconductor devices.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Harada/Marjanovic/Morikazu/Takeda in view of Kishimoto (US 2022/0093579, hereinafter Kishimoto).
With respect to claim 17, Harada/Marjanovic/Morikazu/Takeda discloses the manufacturing method according to claim 16.
Harada/Marjanovic/Morikazu/Takeda does not explicitly disclose wherein the plurality of thin metal films are patterned using at least one of photolithography or etching.
In an analogous art, Kishimoto discloses wherein the plurality of thin metal films are patterned using at least one of photolithography or etching (Para 0133, 0150, 0165-0166). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Harada/Marjanovic/Morikazu/Takeda’s method by having Kishimoto’s disclosure in order to improve the precision of patterning process.
Response to Arguments
Based on new ground of rejection, applicant’s arguments regarding amended claims are moot.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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