DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/465,451, application filed on 09/12/2023. Claims 1-14 are currently pending in this application.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 09/12/2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Matsumoto (US Patent No. 6,295,634).
7. With respect to independent claims 1 and 8, Matsumoto teaches:
reading, by a processor, a plurality of pin information and a plurality of lead rule information of the circuit board stored in a memory (see pin information; see reading design information including disposition of pins on a IC package, Abstract, Col 12, lines 50-67; see information for wiring/leads connecting edge pins to bonding pad, Col 19, lines 15-25, Col 2, lines 60-67; Col 19);
selecting, by the processor, a plurality of outer row pins located on an outer edge of the circuit board among a plurality of pins on the circuit board according to the plurality of pin information (see selecting routes/pins for edge of triangular crossing, Col 5, lines 55-65; see selection/identification of pins of semiconductor package with are at triangular edge, Col 24, lines 1-7);
generating, by the processor, a plurality of outer row leads from the plurality of outer row pins along a direction perpendicular to the outer edge (see classifying/identifying sink pins at edge for triangularization of wiring routes at BGA package, Col 4, lines 1-15; see edges which have crossed/perpendicular to wirings connected to a sink/pin, Col 4, lines 25-35);
establishing, by the processor, a plurality of triangles with the pins as vertices through an algorithm (providing triangularization by providing triangles, Col 6, lines 5-15; see triangles connecting pins to bonding pads, Col 2, lines 55-65; see triangulated edges of delaunay triangles connecting pins to pads, Col 3, lines 1-10), and
selecting a plurality of first pins respectively located in the same triangle as the plurality of outer row pins (selecting pins to connect wiring in same one of triangles, Col 4, lines 55-65; see selecting/classifying pins in same triangles, Col 6, lines 20-27; connecting edges in same one of triangles, Col 11, lines 1-10);
coupling, by the processor, the plurality of outer row leads from the plurality of outer row pins to the plurality of first pins according to a plurality of lead limiting areas, the plurality of triangles and the plurality of lead rule information (see rules for connecting/wiring leads/routes to outer/edge pins based on delaunay triangularization, Col 6, lines 6-61); and
generating, by the processor, a lead data according to a coupling relationship between the plurality of first pins coupled to the plurality of outer row leads (see information for classification of routes and levels for delaunay triangularization of pins and lead/routes on BGA package, Col 6, lines 6-61).
8. With respect to claims 2 and 9, Matsumoto teaches:
calculating, by the processor, a pin average distance between the plurality of adjacent pins according to the pin information (see criteria for determining evaluation for wiring route and/or detouring based on calculation for triangularization of routes and based on length/search, Col 31, lines 1-10); and
obtaining, by the processor, the plurality of lead limiting areas respectively corresponding to the plurality of pins are according to the pin average distance (see criteria for determining evaluation for wiring route and/or detouring based on calculation for triangularization of routes and based on length/search, Col 31, lines 1-10).
9. With respect to claim 3 and 10, Matsumoto teaches:
taking, by the processor, each of the plurality of pins as a center and extending the pin average distance of the plurality of pins toward the direction and two opposite directions perpendicular to the direction to form the rectangular lead limiting area (see selecting routes/pins for edge of triangular crossing, Col 5, lines 55-65; see selection/identification of pins of semiconductor package with are at triangular edge, Col 24, lines 1-7).
10. With respect to claim 4 and 11, Matsumoto teaches:
calculating, by the processor, a plurality of lead turning points on boundaries of the triangles within the lead limiting area according to the lead rule information (see criteria for determining evaluation for wiring route and/or detouring based on calculation for triangularization of routes and based on length/search, Col 31, lines 1-10); and
coupling, by the processor, the plurality of outer row leads to the plurality of first pins via the plurality of lead turning points (coupling, see rules for connecting/wiring leads/routes to outer/edge pins based on delaunay triangularization, Col 6, lines 6-61).
11. With respect to claim 5 and 12, Matsumoto teaches:
determining, by the processor, whether one of the plurality of first pins is able to be coupled to the outer edge through the plurality of lead turning points (see plurality of turning points in delaunay triangularization, Col 4, lines 1-15);
when the processor determines that one of the plurality of first pins is not able to be coupled to the outer edge through the plurality of lead turning points, the one of the first pins is coupled to one of the plurality of outer rows of pins with the same pin type (see same identification number used for pins to routes/leads to bonding pad, Col 6, lines 60-67).
12. With respect to claim 6 and 13, Matsumoto teaches:
dividing, by the processor, the plurality of pin areas into a plurality of areas according to the number of outer edges of the circuit board (dividing wiring plane of semiconductor package into plurality of virtual triangles each having pin and bonding pad, routes/leads for connections, Col 6, lines 5-15).
13. With respect to claim 7 and 14, Matsumoto teaches:
wherein the algorithm is a Delaunay Triangulation algorithm ((providing triangularization by providing triangles, Col 6, lines 5-15; see triangles connecting pins to bonding pads, Col 2, lines 55-65; see triangulated edges of delaunay triangles connecting pins to pads, Col 3, lines 1-10).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
Prosecution Insights