DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6, & 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. US 20230023883 A1 to Chung et al. (hereinafter “Chung”) in view of U.S. Pat. Pub. No. US 20200395339 A1 to Chen et al. (hereinafter “Chen”).
Regarding claim 1, Chung teaches a method comprising:
forming a redistribution line (redistribution line within package substrate 100; fig. 12) [0020] over a carrier (2000; fig. 11) [0087], wherein the forming the redistribution line (100) comprises forming a via (external pad 130; fig. 6) [0023] and a metal trace (substrate wiring pattern 120; fig. 6) [0022] over and joined to the via (130), and wherein the forming the redistribution line (100) comprises:
depositing a first metal layer (metal of 130; fig. 11) [0090];
de-bonding (the carrier substrate 2000 being removed resulting in the structure of fig. 1 or fig. 6; see fig. 17) [0110] the redistribution line (100) from the carrier (2000); and
bonding a package component (chip 500; fig. 6) [0036] to the redistribution line (100), wherein a metal bump (connection terminal 330; fig. 6) [0053] bonds the package component (500) to the via (130).
Chung does not teach:
depositing a barrier layer over the first metal layer; and
depositing a second metal layer over the barrier layer;
Chen, however, teaches:
depositing a barrier layer (122; fig. 2) [0024] over the first metal layer (first active pad 114; fig. 2) [0015]; and
depositing a second metal layer (124; fig. 2) [0024] over the barrier layer (122);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the formation of the redistribution line to comprise a barrier layer deposited between a first and second metal layer to prevent metal diffusion as taught by Chen [0018]. To further clarify, Chen teaches the use of a barrier layer to prevent diffusion of a metal layer into a device layer. The Applicant may notice that para. [0018] does not explicitly describe the same benefit/purpose as it relates to barrier layer 122, but Chen recites the same materials for the barrier layer 122 and the optional barrier layer. In light of this, it is interpreted that Chen intends this teaching i.e., barrier layers preventing diffusion of a metal, to be applicable to any barrier layer taught therein.
Regarding claim 2, Chung in view of Chen teaches the method of claim 1, wherein the forming the redistribution line (100) comprises: forming an embedded via (one of external pads 130, embedded in the layer coplanar to 130; fig. 6) [0023] depositing an additional metal layer (one of wiring pattern 120; fig. 6) [0020] on the embedded via (one of 130).
Chung does not teach wherein the embedded via comprises the first metal layer, the barrier layer, and the second metal layer.
Chen, however, teaches wherein the embedded via (active bonding via 120; fig. 3) [0022] comprises the first metal layer (first active pad 114; fig. 2) [0015], the barrier layer (122; fig. 2) [0024], and the second metal layer (124; fig. 2) [0024].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the formation of the embedded via of Chung to comprise a barrier layer deposited between a first and second metal layer to prevent metal diffusion as taught by Chen [0018].
Regarding claim 3, Chung in view of Chen teaches the method of claim 2 further comprising: forming a dielectric layer (layer surrounding 130; fig. 6); and forming an opening in the dielectric layer (wherein one of 130 is disposed), wherein the embedded via (one of 130) is formed in the opening.
Regarding claim 4, Chung in view of Chen teaches the method of claim 1, wherein the barrier layer (122 of Chen modified to be added to Chung) is fully embedded in the via (130 of Chung, meaning that the barrier layer is contained within the via which is at least the space which 130 of Chung takes up).
Regarding claim 6, Chung in view of Chen teaches the method of claim 1, wherein the metal bump (330) comprises a solder [0033] layer (layer of 330) contacting (at least electrically) the via (130).
Regarding claim 9, Chung in view of Chen, as currently modified, does not teach the method of claim 1, wherein the forming the redistribution line further comprises depositing an additional barrier layer over the second metal layer, wherein the barrier layer and the additional barrier layer have corresponding edges vertically aligned to each other.
Chen, however, teaches depositing an additional barrier layer (222; fig. 2) [0030] over the second metal layer (124), wherein the barrier layer (122) and the additional barrier layer (222) have corresponding edges (edges which meet at the junction between the first die 101 and the second die 201) vertically aligned to each other.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the formation of the redistribution line of Chung to comprise an additional barrier layer over the second metal layer to allow for the formation of an upper and lower device (101 and 201; fig. 2), both comprising barrier layers in vias, decreasing footprint and increasing circuit density (thus forming a 3DIC) as taught by Chen [0002].
Furthermore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the formation of the redistribution line of Chung to comprise vertically aligned edges to further prevent metal diffusion as taught by Chen [0018].
Regarding claim 10, Chung in view of Chen the method of claim 1 further comprising forming an additional redistribution line (second redistribution layer 650; fig. 6) [0066] over and electrically connecting to the redistribution line (100).
Regarding claim 11, Chung teaches a structure comprising:
a redistribution structure (package substrate 100; fig. 12) [0020] comprising a redistribution line (redistribution line within package substrate 100; fig. 12) [0020], wherein the redistribution line (line within 100) comprises:
a via (external pad 130; fig. 6) [0023] comprising:
a first metal layer (metal of 130; fig. 11) [0090];
a metal trace (substrate wiring pattern 120; fig. 6) [0022] over and joined to the via (130); and
a package component (chip 500; fig. 6) [0036] comprising a metal bump (connection terminal 330; fig. 6) [0053] bonding to the via (130), wherein the metal bump (330) comprises a solder region (region of bump 330) [0033] physically joined (connected) to the via (130).
Chung does not teach:
a barrier layer over the first metal layer; and
a second metal layer over the barrier layer;
Chen, however, teaches:
depositing a barrier layer (122; fig. 2) [0024] over the first metal layer (first active pad 114; fig. 2) [0015]; and
depositing a second metal layer (124; fig. 2) [0024] over the barrier layer (122);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the formation of the redistribution line to comprise a barrier layer between a first and second metal layer to prevent metal diffusion as taught by Chen [0018]. To further clarify, Chen teaches the use of a barrier layer to prevent diffusion of a metal layer into an insulating layer [0018]. The Applicant may notice that para. [0018] does not explicitly describe the same benefit/purpose as it relates to barrier layer 122, but Chen recites the same materials for the barrier layer 122 and the optional barrier layer. In light of this, it is interpreted that Chen intends this teaching i.e., barrier layers preventing diffusion of a metal, to be applicable to any barrier layer taught therein.
Regarding claim 12, Chung in view of Chen teaches the structure of claim 11, wherein the barrier layer (122 of Chen modified to be added to Chung) is fully enclosed in the via (130 of Chung, meaning that the barrier layer is contained within the via which is at least the space which 130 of Chung takes up).
Regarding claim 13, Chung in view of Chen, as currently modified, does not teach the structure of claim 11 further comprising an additional barrier layer over the second metal layer, wherein edges of the additional barrier layer are vertically aligned to respective edges of the barrier layer.
Chen, however, teaches depositing an additional barrier layer (222; fig. 2) [0030] over the second metal layer (124), wherein the barrier layer (122) and the additional barrier layer (222) have corresponding edges (edges which meet at the junction between the first die 101 and the second die 201) vertically aligned to each other.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the formation of the redistribution line of Chung to comprise an additional barrier layer over the second metal layer to allow for the formation of an upper and lower device (101 and 201; fig. 2), both comprising barrier layers in vias, decreasing footprint and increasing circuit density (thus forming a 3DIC) as taught by Chen [0002].
Furthermore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the formation of the redistribution line of Chung to comprise vertically aligned edges to further prevent metal diffusion as taught by Chen [0018].
Regarding claim 14, Chung in view of Chen teaches the structure of claim 11, wherein the barrier layer (122) comprises a second metallic material different (layer 122 having no common materials possible with layers 124 and 224) [0024] from the first metallic material (material of layers 124 and 224).
Chung in view of Chen does not explicitly teach the first metal layer and the second metal layer comprise a first metallic material (the same material).
It is noted that while Chung in view of Chen does not explicitly teach that each of the first and second metal layer comprise the same material, Chen establishes a finite list of options for these materials and reaching the combination of claim 14 (the metal layers comprising the same material) would have been obvious to try because the use of the metals listed (e.g., copper [0024]) as a metal layer yields predictable solutions e.g., reliable conductivity. M.P.E.P. 2143 I (E).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Chen as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20230063127 A1 to Huang et al. (hereinafter “Huang”).
Regarding claim 7, Chung in view of Chen teaches the method of claim 1, wherein the depositing the first metal layer (Chen 114), the barrier layer (Chen 122), and the second metal layer (Chen 124) comprises depositing a first copper layer (0020], a nickel layer, and a second copper layer [0024], respectively.
It is noted that while Chung in view of Chen does not explicitly teach that each of the first and second metal layer comprise copper, Chen establishes a finite list of options for these materials and reaching the combination of claim 7 (copper and copper) would have been obvious to try because the use of copper as a metal layer yields predictable solutions like reliable conductivity. M.P.E.P. 2143 I (E).
Chung in view of Chen does not teach that the barrier layer comprises nickel.
Huang, however, teaches a method of forming a redistribution layer (structure of fig. 1J) [0027]-[0041] with conductive pillars (1222, 128a, and 130, for example; fig. 1J) [0057] comprising a barrier layer (122; fig. 1J) [0043], [0052] comprising nickel.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the barrier layer of Chung in view of Chen to comprise nickel to prevent ion diffusion as taught by Huang [0052].
Claims 8 & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Chen as applied to claims 1 & 11 above, and further in view of Influence of the electrical resistance and wire size on the current carrying capacity of connectors to Blauth et al. (hereinafter “Blauth”).
Regarding claim 8, Chung in view of Chen teaches the method of claim 1, wherein the first metal layer has a thickness smaller than about 5 µm.
Blauth, however, teaches that the thickness of a conductor effects its resistance (section V sub-section A).
It would have been obvious to a person of ordinary skill in the art to modify the thickness of the first metal layer to modify its resistance. Given this reason and expectation of success, arriving at the thickness value of claim 8 would have been a matter of routine optimization. M.P.E.P. 2144.05 II (A).
Regarding claim 15, Chung in view of Chen teaches the structure of claim 11, wherein the first metal layer has a first thickness smaller than a second thickness of the second metal layer.
Blauth, however, teaches that the thickness of a conductor effects its resistance (section V sub-section A).
It would have been obvious to a person of ordinary skill in the art to modify the thickness relationship between the first and second metal layers to modify the resistance of each. Given this reason and expectation of success, arriving at the thickness relationship of claim 15 would have been a matter of routine optimization. M.P.E.P. 2144.05 II (A).
Allowable Subject Matter
Claims 18-20 allowed.
Regarding claim 18, it is not found a barrier layer embedded in (i.e., surrounding) a copper region. Furthermore, a modification of Chung in view of Chen (used to reject other claims in this Official Action) would render Chen unsatisfactory for its intended purpose. In specific, Chen teaches that barrier layers are used to prevent diffusion of copper, for example, into dielectric layers. Allowing the copper region to surround the barrier layer would defeat this purpose i.e, allow the copper to diffuse into the dielectric layers. M.P.E.P. 2143.01 V. Claims 19-20 are allowed by virtue of their dependence on an allowable claim.
Claims 5, 16, & 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, it is not found the performing an etching process on the via to remove a portion of a metal seed layer, such etching occurring after the de-bonding. The closest art found is U.S. Pat. Pub. No. US 20230154880 A1 to Tsai et al. but Tsai does not teach a de-bonding process prior to etching a metal seed layer.
Regarding claim 16, a modification of Chung in view of Chen to meet the elements of claim 11 would require that the structure of Chung shift the region of 330 down into the via. Such a modification may interfere with active devices in the same plane as 330. For this reason, such a modification would render Chung unsatisfactory for its intended purpose. M.P.E.P. 2143.01 V.
Regarding claim 17, a modification of Chung in view of Chen to meet the limitations of claim 17 would defeat the purpose of the barrier layer, which is to prevent metal diffusion. Such a modification thus would render Chung unsatisfactory for its intended purpose. M.P.E.P. 2143.01 V.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Pat. Pub. No. US 20170207197 A1 to Yu et al. teaches vias with metal layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892