Office Action Predictor
Last updated: April 15, 2026
Application No. 18/465,686

DEVICE HAVING CFET WITH POWER GRID RAILS IN SECOND METALLIZATION LAYER AND METHOD OF MANUFACTURING SAME

Non-Final OA §103
Filed
Sep 12, 2023
Examiner
ASSOUMAN, HERVE-LOUIS Y
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, LTD.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
94%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
590 granted / 648 resolved
+23.0% vs TC avg
Minimal +3% lift
Without
With
+2.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
42 currently pending
Career history
690
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
54.2%
+14.2% vs TC avg
§102
21.2%
-18.8% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 648 resolved cases

Office Action

§103
Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0233834 A1). Regarding independent claim 1: Chen teaches (e.g., Figs. 1-4) a device comprising: an active region ([0019]: Fig. 1; active region 310) extending in a first direction (Fig. 1; 310 extending in the horizontal direction); a first metal-to-S/D (MD) contact structure (Fig. 1; [0019]: “embedded conductor 230 to some conductive features (e.g., source, drain …) of the transistors”; element 230 is the first metal-to-S/D [0021] and [0027]; hidden in Fig. 4 for purpose of clarity) extending in a second direction (Fig. 4; vertical direction) perpendicular to the first direction (horizontal direction), and over and coupled to the active region ([0019]: (e.g., source, drain) of the transistors”; Fig. 5; [0027]); a first layer of metallization ([0028]: first level 410) over the first MD contact structure and having segments (Fig. 5; first level 410 have M_1st segments) extending in the first direction (horizontal direction) and each having a substantially same width relative to the second direction (same thickness in the vertical direction), the M_1st segments including: M_1st routing segments configured for routing signals (first level 410 includes wiring connected to the second level 410, see Fig. 5; the wirings are capable or routing signals); and an M_1st power grid (PG) segment ([0018]-[0019] and [0028]: “The conductors 410 may also provide power rails and ground planes for the device 100”) having a portion over and coupled to the first MD contact structure (230); a second layer of metallization (Fig. 2; [0028]: middle level and last level 410 represent the second layer of metallization) over the first layer of metallization and having segments (M_2nd segments) that extend in the second direction (Fig. 2; [0028]: last level 410 has segments (M_2nd segments) extending in the vertical direction), the second layer of metallization (Fig. 2; [0028]: the middle layer 410) extending across multiple cell regions (Fig. 1; [0019] and [0027]: left side device cell and the right side device cell are shown separated by a dash line). Although, Chen does not expressly teach that the second layer of metallization includes an M_2nd PG rail configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment; and the M_2nd PG rail extending across multiple cell regions. Chen does teach that the second layer of metallization 410 includes power rails (PG rail) ([0028]); in addition, conductors may be used for routing other signals in addition to power rails or ground planes ([0025]). Therefore, it would have been obvious to a person of ordinary skill at the time of the effective filing date to include enable the disclosure of Chen and arrive at “the second layer of metallization includes an M_2nd PG rail configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment; and the M_2nd PG rail extending across multiple cell regions” because the second layer of metallization will thus include PG rails”, for the benefits of reducing the power rail interconnection length for adjacent devices, and thus, reduce power loss during device operation. Regarding claim 4: Chen teaches the claim limitation of the device of claim 1, on which this claim depends, wherein: relative to the first direction, the M_2nd PG rail (410) is substantially aligned to the first MD contact structure (230). Regarding claim 5: Chen teaches the claim limitation of the device of claim 1, on which this claim depends, wherein: relative to the second direction, the M_1st PG segment ([0018]-[0019] and [0028]: “The conductors 410 may also provide power rails and ground planes for the device 100”) is substantially free from overlapping the active region ([0019] and [0031]: there is no overlapping on the projection of the vertical plan with active region 310). Regarding claim 6: Chen teaches the claim limitation of the device of claim 1, on which this claim depends, wherein: relative to the second direction, the M_1st PG segment ([0018]-[0019] and [0028]: “The conductors 410 may also provide power rails and ground planes for the device 100”) is substantially overlapped by the active region. Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0233834 A1) in view of Peng et al. (US 2018/0019207 A1). Regarding claim 2: Chen teaches the claim limitation of the device of claim 1, on which this claim depends; Chen does not expressly teach that the device further comprises a via-to-MD (VD) contact structure between the active region and the first MD contact structure; and a via-to-M_1st (VIA_1st) contact structure between the M_1st PG segment and the M_2nd PG rail. Peng teaches (e.g., Figs. 3A-3F) a device comprising an active region ([0044]: 326) and a first MD contact structure ([0037]: 304); Peng further teaches a via-to-MD (VD) contact structure ([0038]: 314) between the active region ([0044]: 326) and the first MD contact structure ([0037]: 304); and a via-to-M_1st (VIA_1st) contact structure ([0037]: 306a/306b) between a M_1st PG segment ([0033]: 206a) and a M_2nd PG rail ([0033]: 208a). It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Chen, the via-to-MD (VD) contact structure between the active region and the first MD contact structure; and the via-to-M_1st (VIA_1st) contact structure between the M_1st PG segment and the M_2nd PG rail, as taught by Peng, for the benefits of more effectively transferring power to the selected device based on threshold voltage or electrical characteristics of the device to be powered. Regarding claim 3: Chen teaches the claim limitation of the device of claim 2, on which this claim depends; wherein: relative to the first direction, the VIA_1st contact structure (Peng: [0037]: 306a/306b) is substantially aligned to the first MD contact structure (Peng: [0037]: 304). Allowable Subject Matter Claims 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 7: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a device comprising: “wherein: the M_1st PG segment is an intra-cell PG segment that does not extend outside a corresponding cell region”. Regarding claim 8: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a device comprising: “second and third MD contact structures extending in the second direction, and over and correspondingly coupled to second and third portions of the active region; and a second M_2nd PG rail configured for the first reference voltage, a portion thereof being over the M_1st PG segment; and wherein: the second and third MD contact structures are also included in the cell region; and relative to the first direction, the cell region is free from having another MD contact structure between a first side boundary of the cell region and the first MD contact structure, and the second MD contact structure is between the first and third MD contact structures”. Claims 9-10 depend from claim 8, and therefore, are allowable for the same reason as claim 8. Claims 11-20 are allowable. The following is an examiner’s statement of reasons for allowance: Regarding claim 11: the most relevant prior art references (e.g., Figs. 1-4 of US 2021/0233834 A1 to Chen et al., and Figs. 3A-3F of US 2018/0019207 A1 to Peng et al.) substantially teach the device as shown above. However, none of the prior art references either singly or in proper combination discloses or fairly suggests, along with the other claimed features, a device comprising: “a second layer of metallization over the first layer of metallization and having segments (M_2nd segments) that extend in the second direction and include an M_2nd PG rail configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment; a second buried layer of metallization under the first buried layer of metallization and having segments (BM_2nd segments) that extend in the second direction and include a BM_2nd PG rail configured for a second reference voltage, a portion thereof being under and coupled to the BM_1st PG segment; and each of the M_2nd PG rail and the BM_2nd PG rail extending correspondingly across multiple cell regions”. Claims 12-17 depend from claim 11, and therefore, are allowable for the same reason as claim 11. Regarding claim 18: the most relevant prior art references (e.g., Figs. 1-4 of US 2021/0233834 A1 to Chen et al., and Figs. 3A-3F of US 2018/0019207 A1 to Peng et al.) substantially teach the method of forming a device having a complimentary field-effect transistor (CFET) architecture. However, none of the prior art references either singly or in proper combination discloses or fairly suggests, along with the other claimed features, a method of forming a device having a complimentary field-effect transistor (CFET) architecture comprising: “forming a second layer of metallization over the first layer of metallization and having segments (M_2nd segments) that extend in the second direction and include a M_2nd PG rail extending across multiple cell regions and being configured for a first reference voltage, a portion thereof being over and coupled to the M_1st PG segment; forming a second buried layer of metallization under the first buried layer of metallization and having segments (BM_2nd segments) that extend in the second direction and include a BM_2nd PG rail extending across multiple cell regions and being configured for a second reference voltage, a portion thereof being under and coupled to the BM_1st PG segment”. Claims 19-20 depend from claim 18, and therefore, are allowable for the same reason as claim 18. Note: It appears that canceled claim 64 was a typographical error. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812
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Prosecution Timeline

Sep 12, 2023
Application Filed
Jan 26, 2024
Response after Non-Final Action
Dec 23, 2025
Non-Final Rejection — §103
Apr 06, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
94%
With Interview (+2.6%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 648 resolved cases by this examiner. Grant probability derived from career allow rate.

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