CTNF 18/465,748 CTNF 99016 DETAILED ACTION Notice of AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Invention I, direct to Claims 1-14, and 21-26 in the reply filed on 03/10/2026 is acknowledged and is under consideration. Information Disclosure Statement The Information Disclosure Statement (IDS) submitted on 09/12/2023 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner. Response to Amendment The original claims 1-14 and the new claims 21-26 filed on 03/10/2026 have been fully considered for examination based on their merits. Claims 15-20 are canceled. Response to Arguments The Election of claims 1-15 and 21-26 without traverse are acknowledged and entered. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-2, 4-6, 8, and 10-11 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kangguo Cheng et al, (hereinafter CHENG1), US 20220044973 A1 . Regarding Claim 1 , CHENG1 teaches a method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) comprising: forming a fin structure (Figs. 10/11, 100, structure, step 1102, form a structure) over a bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) and a substrate (Fig. 10B, 102) , wherein the fin structure (Fig. 10, 100, structure) comprises a bottom channel layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) , a sacrificial layer (Figs. 1A/3B, 112/312, top layer is one of the sacrificial layers, [0051]/312, dielectric layer) , over the bottom channel layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) , and a top channel layer (Fig. 10B, 106, pFET device stack; 110, nanaosheet (channel) layers) over the sacrificial layer (Figs. 1A/10B, 112/312, top layer is one of the sacrificial layers, [0051]/312, dielectric layer) ; forming (Fig. 11, 1102, a disposable gate structure formed, [0053]) a dummy gate (Fig. 4B, 302, dummy/disposable gate structure) across the fin structure (Fig. 10, 100, structure) ; removing portions (from Fig. 3B to Fig. 4B; Fig. 11, 1104, remove the first and second nanosheet stacks, [0076]) of the fin structure (Fig. 10, 100, structure) not covered by the dummy gate (Fig. 3B, 302, disposable gate structure) to expose a top surface of the bottom dielectric isolator (from Fig. 3B to Fig. 4B, 314, bottom isolation layer) ; epitaxially growing first source/drain epitaxial structures (Fig. 5B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) over the bottom dielectric isolator (Fig. 4B, 314, bottom isolation layer) and connected to the bottom channel layer (Fig. 5B, 104, nFET device stack; 110, nanaosheet (channel) layers) ; epitaxially growing second source/drain epitaxial structures (Fig. 6B, 606/608, source portions and drain portions, may be epitaxially aligned, [0063]) over the first source/drain epitaxial structures (Fig. 6B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) and connected to the top channel layer (Fig. 6B, 106, pFET device stack) ; and replacing (Fig. 10B, a gate cavity, 702, may be formed in the volume from which the disposable gate structure, 302 was removed, [0065]) the dummy gate (Fig. 4B, 302, dummy/disposable gate structure) and the sacrificial layer (Fig. 4B, 108, sacrificial layer may be removed, [0058]) with a gate structure (Figs. 10A/10B, 1002/1004/802/308, work function layer/gate conductor/gate dielectric layer/spacer, Fig. 11, step 1106, [0077]) . Regarding Claim 2 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 1, wherein epitaxially growing the first source/drain epitaxial structures (Fig. 5B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) is such that the first source/drain epitaxial structures (Fig. 5B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) are in contact with the top surface of the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) . Regarding Claim 4 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 1, wherein after replacing the dummy gate (Fig. 4B, 302, dummy/disposable gate structure) and the sacrificial layer (Fig. 4B, 108, sacrificial layer may be removed, [0058]) with the gate structure (Figs. 10A/10B, 1002/1004/802/308, work function layer/gate conductor/gate dielectric layer/spacer, Fig. 11, step 1106, [0077]) , a bottom surface of the gate structure (Figs. 10A/10B, 1002/1004802/308, work function layer/gate conductor/gate dielectric layer/spacer, Fig. 11, step 1106, [0077]) is higher (annotated Figure 10B) than a bottom surface of the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) . PNG media_image1.png 948 1284 media_image1.png Greyscale Regarding Claim 5 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 1, wherein forming the fin structure (Figs. 10/11, 100, structure, step 1102, form a structure) over the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) comprises: forming a first bonding layer (Fig. 10B, 314, bottom isolation layer) over the substrate (Fig. 10B, 102) ; forming a second bonding layer (Figs. 1A/3B, 112, top layer is one of the sacrificial layers, [0051]/312, dielectric layer) over an epitaxial stack (Fig. 5B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) ; bonding the first bonding layer (Fig. 10B, 314, bottom isolation layer) and the second bonding layer (Figs. 1A/3B, 112, top layer is one of the sacrificial layers, [0051]/312, dielectric layer) to form the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) , wherein the epitaxial stack (Fig. 5B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) is over the substrate (Fig. 10B, 102) ; and patterning the epitaxial stack (Figs. 2-2A, patterned to form a plurality of vertical stacks (nanosheet stacks), [0051]) to form the fin structure (Figs. 10/11, 100, structure, step 1102, form a structure) . Regarding Claim 6 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 5, further comprising patterning the bottom dielectric isolator by using the fin structure as an etch mask (Figs. 1-1B, a hardmask layer, 114 may be formed on and in contact with a top layer of the pFET device stack, 106; a nFET device stack, 104, and a pFET device stack, 106, isolated from each other by the patterned insulating layer, 112, [0051]; the etching process of the vertical stacks, 202-204, exposes one or more portion of the top surface layers, 108; and ends of the bottom isolation layer, 314, [0057]) . Regarding Claim 8 , CHENG1 teaches a method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) comprising: forming a first dielectric layer (Fig. 10B, 314, bottom isolation layer) over a substrate (Fig. 10B, 102) ; forming a second dielectric layer (Figs. 1A/3B, 112/12, top layer is one of the sacrificial layers, [0051]/312, dielectric layer) over an epitaxial stack (Fig. 5B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) ; bonding the second dielectric layer (Figs. 1A/3B, 112/12, top layer is one of the sacrificial layers, [0051]/312, dielectric layer) to the first dielectric layer to form a bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) , wherein the epitaxial stack (Figs. 5B/6B, 504/506/606/608, source portions and drain portions, may be epitaxially aligned, [0061], [0063]) is over the substrate (Fig. 10B, 102) and comprises a first channel layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) , a sacrificial layer (Figs. 1A/3B, 112/12, top layer is one of the sacrificial layers, [0051]/312, dielectric layer) , and a second channel layer (Fig. 10B, 106, pFET device stack; 110, nanaosheet (channel) layers) from bottom to top (Fig. 10B, 104 (bottom), 312 (middle) and 106 (top)) ; and forming a complementary field-effect transistor (CFET) (Figs. 10B/11, vertical stacked nanosheet CMOST transistor, [0076]) over the substrate (Fig. 10B, 102) and the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) , wherein the CFET comprises (Figs. 10B/11, vertical stacked nanosheet CMOST transistor, [0076]) the first channel layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) and the second channel layer (Fig. 10B, 106, pFET device stack; 110, nanaosheet (channel) layers) of the epitaxial stack (Figs. 5B/6B, 504/506/606/608, source portions and drain portions, may be epitaxially aligned, [0061], [0063]) . Regarding Claim 10 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 8, wherein forming the CFET (Fig. 1, semiconductor structure comprising stacked nFET and pFET, [0009]) over the substrate comprises: patterning the epitaxial stack (Figs. 2-2A, patterned to form a plurality of vertical stacks (nanosheet stacks), [0051]) to form a fin structure (Figs. 10/11, 100, structure, step 1102, form a structure) comprising the first channel layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) , the sacrificial layer (Figs. 1A/3B, 112/312, top layer is one of the sacrificial layers, [0051]/312, dielectric layer) , and the second channel layer (Fig. 10B, 106, pFET device stack; 110, nanaosheet (channel) layers) ; patterning (from Fig. 3B to Fig. 4B; Fig. 11, 1104, remove the first and second nanosheet stacks, [0076]) the fin structure (Figs. 10/11, 100, structure, step 1102, form a structure) to expose the bottom dielectric isolator (from Fig. 3B to Fig. 4B, 314, bottom isolation layer) ; forming first source/drain epitaxial structures (Fig. 5B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) on opposite sides of the first channel layer and layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) in contact with the first channel layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) ; forming second source/drain epitaxial structures (Fig. 6B, 606/608, source portions and drain portions, may be epitaxially aligned, [0063]) on opposite sides of the second channel layer (Fig. 10B, 106, pFET device stack; 110, nanaosheet (channel) layers) and in contact with the second channel layer (Fig. 10B, 106, pFET device stack; 110, nanaosheet (channel) layers) ; and replacing (Fig. 10B, a gate cavity, 702, may be formed in the volume from which the disposable gate structure, 302 was removed, [0065]) the sacrificial layer (Fig. 4B, 108, sacrificial layer may be removed, [0058]) with a gate structure (Figs. 10A/10B, 1002/1004/802/308, work function layer/gate conductor/gate dielectric layer/spacer, Fig. 11, step 1106, [0077]) . Regarding Claim 11 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 10, wherein the gate structure (Figs. 10A/10B, 1002/1004/802/308, work function layer/gate conductor/gate dielectric layer/spacer, Fig. 11, step 1106, [0077]) is in contact with the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHENG1 as applied to claim(s) 1-2, 4-6, 8, 10-11, above, in view of Alexander Reznicek et al, (hereinafter REZNICEK), US 11315938B1 . Regarding Claim 3 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 1. CHENG1 does not explicitly disclose the method, wherein the bottom dielectric isolator has a thickness in a range from about 50 angstroms to about 70 angstroms. REZNICEK teaches the method, (Figs. 1-20, method including forming a nanosheet stack on a substrate, vertically aligned, [Col. 2, Lines 5-25]) , wherein the bottom dielectric isolator (Figs. 4-6, 12/52, the lower isolation, 52 may be formed where the stack sacrificial layer, 12 has been removed, [Col. 9, Lines 40-45]) has a thickness in a range from about 50 angstroms to about 70 angstroms (Figs. 4-6, 12/52, stack sacrificial layer/lower isolation, may have a thickness ranging from 5 nm to about 15 nm, [Col. 7, Lines 5-15]; 1nm = 10 angstroms; therefore 5 nm = 50 angstroms and 15 nm = 150 angstroms) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified CHENG1 to incorporate the teachings of REZNICEK, such that the method, wherein the bottom dielectric isolator has a thickness in a range from about 50 angstroms to about 70 angstroms, so that the stacked nanosheet FETs with identical thickness would provide more integrated circuitry, (REZNICEK, [Col. 1, Lines 25-30]) . 07-21-aia AIA Claim (s) 7, 9, and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHENG1 as applied to claim(s) 1-2, 4-6, 8, and 10-11, above, in view of Wei-Hao Wu et al, (hereinafter WU), US 20190097011 A1 . Regarding Claim 7 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 1. CHENG1 does not explicitly disclose the method, further comprising forming an isolation structure over the substrate prior to forming the fin structure. WU teaches the method (method for manufacturing a semiconductor device at various stages, [0003]) , further comprising: forming an isolation structure (Fig. 2, 220, isolation structures) over the substrate (Fig. 2, 110) prior to forming the fin structure (Fig. 2, 210, semiconductor strip) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified CHENG1 to incorporate the teachings of WU such that the method, further comprising forming an isolation structure over the substrate prior to forming the fin structure, so that the isolation structures, 220, which may be shallow trench solation (STI) regions, the isolation structure, 220 is disposed between the first metal gate stack, 1220 and the substrate and serve as an insulation layer (WU, [0062]) . Regarding Claim 9 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 8. CHENG1 does not explicitly disclose the method, further comprising: forming an isolation structure over the substrate prior to forming the first dielectric layer. WU teaches the method (method for manufacturing a semiconductor device at various stages, [0003]) , further comprising: forming an isolation structure (Fig. 5, 220, isolation structures) over the substrate (Fig. 5, 110) prior to forming the first dielectric layer (Fig. 5, 510, insulation layer, [0034]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified CHENG1 to incorporate the teachings of WU such that the method, further comprising: forming an isolation structure over the substrate prior to forming the first dielectric layer, so that the isolation structures, 220, which may be shallow trench solation (STI) regions, the isolation structure, 220 is disposed between the first metal gate stack, 1220 and the substrate and the insulation layer, 510, made of dielectric materials serve as bottom dielectric isolation between the semiconductor strip and the substrate (WU, Figure 5) . Regarding Claim 12 , CHENG1 teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) of claim 10. CHENG1 does not explicitly disclose the method, wherein forming the CFET over the substrate further comprises: forming a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer to cover the first source/drain epitaxial structures prior to forming the second source/drain epitaxial structures. WU teaches the method (method for manufacturing a semiconductor device at various stages, [0003]) , wherein forming the CFET (Fig. 1, active components, pFET/nFET, 130/150, semiconductor stacks, [0014-0020]) over the substrate (Fig. 1, 110) further comprises: forming a contact etch stop layer (CESL) (Figs. 8A/9A, 320) and an interlayer dielectric (ILD) layer (Figs. 8A/9A, 910, [0041]) to cover the first source/drain epitaxial structures (Figs. 8A/9A, 810, first epitaxy structures) prior to forming the second source/drain epitaxial structures (Figs. 8A/9A, 930, second epitaxy structures) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified CHENG1 to incorporate the teachings of WU such that the method, wherein forming the CFET over the substrate further comprises: forming a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer to cover the first source/drain epitaxial structures prior to forming the second source/drain epitaxial structures. The above arrangements wherein the bottom ILD, 910 surrounds the first epitaxy structures, 810 in contact with the semiconductor layers, 134 and exposes the first epitaxy structures, 810 in contact with the semiconductor layers, 154 (WU, Figure 8A, [0041]) . Regarding Claim 13 , CHENG1 as modified by WU teaches the method of claim 12. WU further teaches the method (method for manufacturing a semiconductor device at various stages, [0003]) , wherein the CESL (Figs. 8A/9A, 320) is in contact with the bottom dielectric isolator (Figs. 8A/9A. 510, insulation layer made of dielectric materials, [0034]) . 07-21-aia AIA Claim (s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHENG1 as applied to claim(s) 1-2, 4-6, 8, and 10-11, above, in view of WU as applied to claim(s) 7, 9, and 12-13, and further in view of Cezar Bogdan Zota et al, (hereinafter ZOTA), US 20220302269 A1 . Regarding Claim 14 , CHENG1 as modified by WU teaches method of claim 9. CHENG1 as modified by WU does not explicitly disclose a method, wherein after removing the substrate to expose a bottom surface of the bottom dielectric isolator. ZOTA teaches a method (Fig. 13, 1300, flow of the inventive method of forming heterogeneous complimentary FETs using a compact stacked nanosheet process, [0022]) , wherein after removing (From Fig. 10, 128, with substrate to Fig. 11, with no substrate, 128) the substrate (Figs. 10/11, 128) to expose a bottom surface of the bottom dielectric isolator (Fig. 11, 126, optional oxide layer’s backside opposite to the frontside facing the sacrificial layer, 124) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have CHENG1 as modified by WU to incorporate the teachings of ZOTA, such that a method, wherein after removing the substrate to expose a bottom surface of the bottom dielectric isolator, to facilitate for the fabrication of the backside power rail or via or contact for electrical connections (ZOTA, Figure 11, [0077]) . 07-21-aia AIA Claim (s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHENG1 as applied to claim(s) 1-2, 4-6, 8, 10-11, above, in view of ZOTA as applied to Clam(s) 14, and further in view of Kangguo Cheng et al, (hereinafter CHENG2), US 20230187551 A1 . Regarding Claim 21 , CHENG1 teaches a method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) comprising: forming a bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) over a substrate (Fig. 10B, 102) ; forming a fin structure (Figs. 10/11, 100, structure, step 1102, form a structure) over the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) and spaced apart from the substrate (Fig. 10B, 102) by the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) , the fin structure (Figs. 10/11, 100, structure, step 1102, form a structure) comprising a first channel layer (Fig. 10B, 110, nanaosheet (channel) layers) and a second channel layer (Fig. 10B, 110, nanaosheet (channel) layers) over the first channel layer (Fig. 10B, 110, nanaosheet (channel) layers) ; forming a bottom nanostructure transistor (Fig. 10B, 104, nFET device stack) , comprising the first channel layer (Fig. 10B, 110, nanaosheet (channel) layers) , a first source/drain epitaxial structure (Figs. 5B/10B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) connected to the first channel layer (Fig. 10B, 110, nanaosheet (channel) layers) , and a first gate structure (Fig. 10B, 804, work function layer/1004, gate metal/802, gate dielectric, 308, spacers) wrapping (Fig. 10B, [0053], [0067], [0069]) around the first channel layer (Fig. 10B, 110, nanaosheet (channel) layers) ; forming a top nanostructure transistor (Fig. 10B, 106, pFET device stack) over the bottom nanostructure transistor (Fig. 10B, 104, nFET device stack) , the top nanostructure transistor (Fig. 10B, 106, pFET device stack) comprising the second channel layer (Fig. 10B, 110, nanaosheet (channel) layers) ; CHENG1 does not explicitly disclose a method comprising: removing the substrate to expose a bottom surface of the bottom dielectric isolator. ZOTA teaches a method (Fig. 13, 1300, flow of the inventive method of forming heterogeneous complimentary FETs using a compact stacked nanosheet process, [0022]) comprising: removing (From Fig. 10, 128, with substrate to Fig. 11, with no substrate, 128) the substrate (Figs. 10/11, 128) to expose a bottom surface of the bottom dielectric isolator. (Fig. 11, 126, optional oxide layer’s backside opposite to the frontside facing the sacrificial layer, 124). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have modified CHENG1 to incorporate the teachings of ZOTA, such that a method comprising: removing the substrate to expose a bottom surface of the bottom dielectric isolator, to facilitate for the fabrication of the backside power rail or via or contact for electrical connections (ZOTA, Figure 11, [0077]) . CHENG1 as modified by ZOTA does not explicitly disclose a method comprising: forming a backside via electrically connected to the first source/drain epitaxial structure. CHENG2 teaches a method (Figs. 2-17, method for fabricating a semiconductor integrated circuit device comprising a stacked complementary transistor structure comprising first and second transistors, [0016]) comprising: forming a backside via (Fig. 17, 193, source/drain contact, [0043]) electrically connected to the first source/drain epitaxial structure (Fig. 17, 160-2, the second source/drain element of first transistor, 101, [0043]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA) to have CHENG1 as modified by ZOTA to incorporate the teachings of CHENG2, such that a method comprising: forming a backside via electrically connected to the first source/drain epitaxial structure, so that the second interconnect structure, 210 along with the source/drain contact structure, 193 provides a backside power distribution, and backside I/O signal network (CHENG2, [0043]) . Regarding Claim 22 , CHENG1 as modified by WU and CHENG2, teaches the method of claim 21. CHENG1 further teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) , wherein forming the bottom nanostructure transistor layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) comprises forming the first source/drain epitaxial structure (Fig. 5B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) directly over the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) such that the first source/drain epitaxial structure (Fig. 5B, 504/506, source portions and drain portions, may be epitaxially aligned, [0061]) is in contact with the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) . Regarding Claim 23 , CHENG1 as modified by WU and CHENG2, teaches the method of claim 21. CHENG1 further teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) , wherein forming the bottom nanostructure transistor (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) comprises forming the first gate structure (Figs. 10A/10B, 1002/1004/802/308, work function layer/gate conductor/gate dielectric layer/spacer, Fig. 11, step 1106, [0077]) in contact with the bottom dielectric isolator (Fig. 10B, 314, bottom isolation layer) . Regarding Claim 24 , CHENG1 as modified by WU and CHENG2, teaches the method of claim 21. CHENG2 further teaches a method (Figs. 2-17, method for fabricating a semiconductor integrated circuit device comprising a stacked complementary transistor structure comprising first and second transistors, [0016]) wherein forming the backside via (Fig. 17, 193, source/drain contact, [0043]) comprises: forming a dielectric isolation layer (Fig. 17, 205, backside insulating layer, [0032]) covering the exposed (Fig. 16, [0031]) bottom surface of the bottom dielectric isolator (Fig. 17, 205, backside insulating layer, [0032]) ; forming an opening (Fig. 17, via opening, [0101]) extending through the dielectric isolation layer (Fig. 17, 176/205, ILD/dielectric layers) and the bottom dielectric isolator (Fig. 17, 205, backside insulating layer, [0032]) to expose the first source/drain epitaxial structure (Fig. 17, 160-2, second source/drain elements, [0109]) ; and filling the opening (Fig. 17, via opening, [0101]) with a conductive material to form the backside via (Fig. 17, 193, source/drain contact, [0043-0044]) . Regarding Claim 25 , CHENG1 as modified by WU and CHENG2, teaches the method of claim 21. CHENG1 further teaches the method (Figs. 11-12, operational flow diagram for forming a semiconductor device, [0037-0038]) , further comprising forming a middle dielectric isolator (Figs. 1A/3B, 112/312, top layer is one of the sacrificial layers, [0051]/312, dielectric layer) between the first channel layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) and the second channel layer (Fig. 10B, 106, pFET device stack; 110, nanaosheet (channel) layers) to isolate the first channel layer (Fig. 10B, 104, nFET device stack; 110, nanaosheet (channel) layers) from the second channel layer (Fig. 10B, 106, pFET device stack; 110, nanaosheet (channel) layers) . Regarding Claim 26 , CHENG1 as modified by WU and CHENG2, teaches the method of claim 21. ZOTA teaches a method (Fig. 13, 1300, flow of the inventive method of forming heterogeneous complimentary FETs using a compact stacked nanosheet process, [0022]) , wherein the bottom dielectric isolator (Fig. 11, 126, optional oxide layer’s backside opposite to the frontside facing the sacrificial layer, 124) is utilized as an etch stop layer (Fig. 13, 1310, [0088]) during removing the substrate (Figs. 10/11, 128) , such that the first gate structure (Fig. 11, 1108, metal gate stack, [0077-0079]) and the first source/drain epitaxial structure are not damaged (Fig. 11, 702/704) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20230238436 A1 – Figure 2D STATEMENT OF RELEVANCE – Cross-sectional view of the device with a source-drain-gate structure with conductor backside via, spacers and conductor contact. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817 /MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817 Application/Control Number: 18/465,748 Page 2 Art Unit: 2817 Application/Control Number: 18/465,748 Page 3 Art Unit: 2817 Application/Control Number: 18/465,748 Page 4 Art Unit: 2817 Application/Control Number: 18/465,748 Page 5 Art Unit: 2817 Application/Control Number: 18/465,748 Page 6 Art Unit: 2817 Application/Control Number: 18/465,748 Page 7 Art Unit: 2817 Application/Control Number: 18/465,748 Page 8 Art Unit: 2817 Application/Control Number: 18/465,748 Page 9 Art Unit: 2817 Application/Control Number: 18/465,748 Page 10 Art Unit: 2817 Application/Control Number: 18/465,748 Page 11 Art Unit: 2817 Application/Control Number: 18/465,748 Page 12 Art Unit: 2817 Application/Control Number: 18/465,748 Page 13 Art Unit: 2817 Application/Control Number: 18/465,748 Page 14 Art Unit: 2817 Application/Control Number: 18/465,748 Page 15 Art Unit: 2817 Application/Control Number: 18/465,748 Page 16 Art Unit: 2817 Application/Control Number: 18/465,748 Page 17 Art Unit: 2817 Application/Control Number: 18/465,748 Page 18 Art Unit: 2817 Application/Control Number: 18/465,748 Page 19 Art Unit: 2817
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