DETAILED ACTION
This office action is in response to amendment filed 7/3/2026.
Claims 1-12 are pending. Claims 7-11 have been withdrawn. Claims 1 and 3 have been amended.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-6 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. US 2011/0304016 A1 (cited in IDS filed 1/27/2026, hereinafter Nakamura).
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In re claim 1, Nakamura discloses (e.g. FIGs. 1-4) a semiconductor package structure, comprising:
a package layer 44, a first device layer (structure above layer 16), a first insulation layer 16,19, a conductive copper pillar 17,20 (¶ 77), and a second device layer (structure below layer 19); wherein the package layer 44 covers the first device layer; the first device layer (structure above 16), the first insulation layer 16,19, and the second device layer (structure below 19) are sequentially stacked; the conductive copper pillar 17,20 extends through the first insulation layer 16,19; the first device layer (structure above 16) and the second device layer (structure below 19) are electrically connected through the conductive copper pillar 17,20;
wherein the first device layer (structure above 16) comprises a first circuit layer 12, a trench DP, and an embedded device 31; the embedded device 31 is connected to the first circuit layer 12; the trench DP is arranged within the first circuit layer 12 (DP is located in a space defined by circuit layer 12; being inside or “within” does not require the trench to complete occupy the space; a trench that is present inside a portion of the space defined by the circuit layer is considered “within” the circuit layer; furthermore, the “first circuit layer” can be interpreted to include both the metal 12 and the insulating layer 13; as such, the trench DP is completely occupying the entire space within the “circuit layer” 12+13) and located below the embedded device 31; the trench DP is partially or completely overlapped with a projection of the embedded device DP in a mounting direction of the embedded device 31 (see FIG. 3B); and
wherein the second device layer (structure below 19) comprises a second circuit layer 21, a first solder mask layer 22, and a solder ball 45; the first solder mask layer 22 partially covers the second circuit layer 21; and the solder ball 45 is connected to the second circuit layer 21.
In re claim 4, Nakamura discloses (e.g. FIG. 4) wherein a quantity of the embedded device 31 is one or more; and a quantity of the trench DP is one or more.
In re claim 5, Nakamura discloses (e.g. FIG. 4) wherein the embedded device 31 comprises an active device or a passive device (¶ 48).
In re claim 6, Nakamura discloses (e.g. FIG. 4) wherein a depth of the trench DP is greater than or equal to a thickness of the first circuit layer 12.
In re claim 12, Nakamura discloses (e.g. FIG. 4) an integrated circuit system, comprising at least one semiconductor package structure according to claim 1. No specific integrated circuit system has been claimed that would structurally distinguish over Nakamura’s device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura as applied to claim 1 above, and further in view of Kawamoto et al. US 2005/0051358 (Kawamoto).
In re claim 2, Nakamura discloses the claimed invention including a first solder mask layer 22 covering the bottom circuit layer 21 on the lower side of the wiring board to protect the bottom circuit layer 21 (¶ 42). Nakamura does not explicitly disclose the first/top device layer further comprises a second solder mask layer; and the second solder mask layer partially covers the first/top circuit layer 12. However, Kawamoto discloses a semiconductor package structure (FIG. 2) comprising solder resist 106 formed on both front and rear surfaces of the wiring board 102, wherein the solder mask layer 106 partially covers the first/top circuit layer 111. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form solder mask layer on both the top and bottom sides of the wiring board as taught by Kawamoto to provide protection to the circuit layers on both sides and to prevent short circuit.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura as applied to claim 1 above, and further in view of Kim et al. US 2021/0174177 A1 (Kim).
In re claim 3, Nakamura discloses the claimed invention including a semiconductor package structure comprising insulation layer 16,19. Nakamura further discloses the insulating layer is formed of an epoxy-based resin, polyimide-based resin, or the like (¶ 73). Nakamura does not explicitly disclose the first insulation layer comprises a polypropylene (PP) material or an aromatic benzocyclobutene Film (ABF) material.
However, Kim discloses (e.g. FIG. 1A) a semiconductor package comprising insulating layer 112 having circuit layers on both top and bottom sides connected by conductive structures 111 extending through the insulation layer 112. Kim discloses the insulation layer 112 comprises a polypropylene (PP) material or an aromatic benzocyclobutene Film (ABF) material (¶ 25).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Nakamura’s insulation layer 16,19 comprising a polypropylene (PP) material or an aromatic benzocyclobutene Film (ABF) material as taught by Kim as being known insulation material suitable for providing insulation between wiring layers in a wiring substrate.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Response to Arguments
Applicant's arguments filed 7/3/2026 have been fully considered but they are not persuasive.
Regarding Nakamura, Applicant argues the recessed portion DP is formed on the insulating layer 13, not in the pads 12 (Remark, pages 7-8).
This is not persuasive. The recess DP is located in a space defined by circuit layer 12. Being inside or “within” does not require the trench to complete occupy the space. A trench that is present inside a portion of the space defined by the circuit layer is considered to be “within” the circuit layer. The claim does not exclude other material, e.g. Nakamura’s insulating layer material 13, to be also present “within” the first circuit layer.
Furthermore, the “first circuit layer” can be interpreted to include both the metal 12 and the insulating layer 13. I.e. the metal 12 and the insulating layer 13 together forms a layer of circuit that routes electrical signal through the metal portion. As such, the trench DP is completely occupying the entire space within the “circuit layer” 12+13.
Applicant further argues the invention being different as characterized by the challenges faced during the manufacturing process of device pre-embedded inside the package body (Remark, pages 8-10). As best understood, the difference argued appears to be directed to manufacturing process. The claims are directed to the semiconductor package structure, not its manufacturing process. No specific structural difference has been specifically recited in the claims.
In regard to the product by process language, since a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao and Sato et al., 190 USPQ 15 at 17 (CCPA 1976) (footnote 3). “[T]he lack of physical description in a product-by-process claim makes determination of the patentability of the claim more difficult, since in spite of the fact that the claim may recite only process limitations, it is the patentability of the product claimed and not of the recited process steps which must be established. We are therefore of the opinion that when the prior art discloses a product which reasonably appears to be either identical with or only slightly different than a product claimed in a product-by-process claim, a rejection based alternatively on either section 102 or section 103 of the statute is eminently fair and acceptable. As a practical matter, the Patent Office is not equipped to manufacture products by the myriad of processes put before it and then obtain prior art products and make physical comparisons therewith.” In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the final product per se which must be determined for patentability in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not, is not patentable. Note that Applicant has the burden of proof in such cases, as the above case law makes clear. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based upon the product itself. The patentability of a product does not depend on its method of production. If the product in product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product is made by a different process. In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
In response to applicant's argument that the references fail to show certain features of the invention (Remark, page 10), it is noted that the features upon which applicant relies are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Furthermore, Applicant argues Nakamura as belonging to different technical subfields and solving a different problem from Applicant’s invention (Remark, pages 8-11).
The question of whether a reference is analogous art is not relevant to whether that reference anticipates. A reference may be directed to an entirely different problem than the one addressed by the inventor, or may be from an entirely different field of endeavor than that of the claimed invention, yet the reference is still anticipatory if it explicitly or inherently discloses every limitation recited in the claims. See MPEP 2131.05. Arguments that the alleged anticipatory prior art is ‘nonanalogous art’ or ‘teaches away from the invention’ or is not recognized as solving the problem solved by the claimed invention, [are] not ‘germane’ to a rejection under section 102.” Twin Disc, Inc.v. United States, 231 USPQ 417, 424 (Cl. Ct. 1986) (quoting In re Self, 671 F.2d 1344, 213 USPQ 1, 7 (CCPA 1982)). See also State Contracting & Eng’ g Corp. v. Condotte America, Inc., 346 F.3d 1057, 1068, 68 USPQ2d 1481, 1488 (Fed. Cir. 2003)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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