Prosecution Insights
Last updated: July 05, 2026
Application No. 18/465,889

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREFOR

Non-Final OA §102§103§112
Filed
Sep 12, 2023
Priority
Sep 29, 2022 — CN 2022112015341
Examiner
CHEN, YU
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
ZHUHAI ACCESS SEMICONDUCTOR CO., LTD.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
726 granted / 1069 resolved
At TC average
Strong +30% interview lift
Without
With
+29.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
80 currently pending
Career history
1175
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
77.0%
+37.0% vs TC avg
§102
12.2%
-27.8% vs TC avg
§112
5.5%
-34.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1069 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of invention Group I (claims 1-6 and 12) in the reply filed on 1/27/2026 is acknowledged. Claims 7-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/27/2026. Claim Objections Claim 3 is objected to because of the following informalities: Claim 3 reciting “a Polypropylene (PP) material or an Aromatic Benzocyclobutene Film (ABF) material” should be amended to avoid use of capital letters in naming the material. The material claimed are chemical names, but are not understood to be trademark. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 reciting “a semiconductor package structure configured to connect to an external functional circuit, configured to implement an electrical connection between the second circuit layer and the external functional circuit” renders the claim indefinite. It is unclear if the “external functional circuit” is intended to be a required structural element of the semiconductor package claim 1 is directed toward. Or is the connection to “external functional circuit” and the “external functional circuit” itself intended use only. Other claims are rejected for depending on a rejected claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 4-6 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. US 2011/0304016 A1 (cited in IDS filed 1/27/2026, hereinafter Nakamura). PNG media_image1.png 432 938 media_image1.png Greyscale In re claim 1, as best understood, Nakamura discloses (e.g. FIGs. 1-4) a semiconductor package structure “configured to connect to an external functional circuit” (¶ 55), comprising: a package layer 44, a first device layer (structure below layer 19), a first insulation layer 13,16,19, a conductive copper pillar 14,17,20 (¶ 77), and a second device layer (structure above layer 13); wherein the package layer 44 covers the first device layer; the first device layer (structure above 13), the first insulation layer 13,16,19, and the second device layer (structure below 19) are sequentially stacked; the conductive copper pillar 14,17,20 extends through the first insulation layer 13,16,19; the first device layer (structure above 13) and the second device layer (structure below 19) are electrically connected through the conductive copper pillar 14,17,20; wherein the first device layer (structure above 13) comprises a first circuit layer 12, a trench DP, and an embedded device 31; the embedded device 31 is connected to the first circuit layer 12; the trench DP is arranged below the embedded device 31; the trench DP is partially or completely overlapped with a projection of the embedded device DP in a mounting direction of the embedded device 31 (see FIG. 3B); and wherein the second device layer (structure below 19) comprises a second circuit layer 21, a first solder mask layer 22, and a solder ball 45; the first solder mask layer 22 partially covers the second circuit layer 21; and the solder ball 45 is “configured to implement an electrical connection between the second circuit layer and the external functional circuit” (¶ 55). In re claim 4, Nakamura discloses (e.g. FIG. 4) wherein a quantity of the embedded device 31 is one or more; and a quantity of the trench DP is one or more. In re claim 5, Nakamura discloses (e.g. FIG. 4) wherein the embedded device 31 comprises an active device or a passive device (¶ 48). In re claim 6, Nakamura discloses (e.g. FIG. 4) wherein a depth of the trench DP is greater than or equal to a thickness of the first circuit layer 12. In re claim 12, Nakamura discloses (e.g. FIG. 4) an integrated circuit system, comprising at least one semiconductor package structure according to claim 1. No specific integrated circuit system has been claimed that would structurally distinguish over Nakamura’s device. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura as applied to claim 1 above, and further in view of Kawamoto et al. US 2005/0051358 (Kawamoto). In re claim 2, Nakamura discloses the claimed invention including a first solder mask layer 22 covering the bottom circuit layer 21 on the lower side of the wiring board to protect the bottom circuit layer 21 (¶ 42). Nakamura does not explicitly disclose the first/top device layer further comprises a second solder mask layer; and the second solder mask layer partially covers the first/top circuit layer 12. However, Kawamoto discloses a semiconductor package structure (FIG. 2) comprising solder resist 106 formed on both front and rear surfaces of the wiring board 102, wherein the solder mask layer 106 partially covers the first/top circuit layer 111. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form solder mask layer on both the top and bottom sides of the wiring board as taught by Kawamoto to provide protection to the circuit layers on both sides and to prevent short circuit. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura as applied to claim 1 above, and further in view of Kim et al. US 2021/0174177 A1 (Kim). In re claim 3, Nakamura discloses the claimed invention including a semiconductor package structure comprising insulation layer 13,16,19. Nakamura further discloses the insulating layer is formed of an epoxy-based resin, polyimide-based resin, or the like (¶ 73). Nakamura does not explicitly disclose the first insulation layer comprises a Polypropylene (PP) material or an Aromatic Benzocyclobutene Film (ABF) material. However, Kim discloses (e.g. FIG. 1A) a semiconductor package comprising insulating layer 112 having circuit layers on both top and bottom sides connected by conductive structures 111 extending through the insulation layer 112. Kim discloses the insulation layer 112 comprises a Polypropylene (PP) material or an Aromatic Benzocyclobutene Film (ABF) material (¶ 25). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Nakamura’s insulation layer 13,16,19 comprising a Polypropylene (PP) material or an Aromatic Benzocyclobutene Film (ABF) material as taught by Kim as being known insulation material suitable for providing insulation between wiring layers in a wiring substrate. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896
Read full office action

Prosecution Timeline

Sep 12, 2023
Application Filed
Apr 03, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
97%
With Interview (+29.5%)
2y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1069 resolved cases by this examiner. Grant probability derived from career allowance rate.

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