DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments, see page 9, filed 06/29/2026, with respect to the specification have been fully considered and are persuasive. The objections of the drawings has been withdrawn.
Applicant’s arguments, see pages 10-16, filed 06/29/2026, with respect to the rejection(s) of claim(s) 1 and 15 under 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hsieh et al. (US 20190252294 A1).
Claim Objections
Claims 1 and 15 are objected to because of the following informalities: Both claims recite “the first height is substantially equal to the second height” but the examiner does not see how this could be possible. The claim requires “a first height comprises (i) a height of the FC IPD die and (ii) a height of the at least one first mechanical support; a second height comprises (i) a height of the second component and (ii) a height of the at least one second mechanical support;” but with the addition of “the height of the FC IPD die is different that the height of the second component;” the examiner does not see how the “the first height is substantially equal to the second height” since the mechanical supports appear to have the same height throughout all of the applicants’ figures. The examiner does see other components (i.e. the top-side cooling structure) which make the overall height of the devices appear equal but currently that is not being claimed in the independents. Appropriate correction or explanation is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-11, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (US 20190206839 A1) in view of Hsieh et al. (US 20190252294 A1).
Regarding claim 1, Balakrishnan discloses a package including an integrated passive device (IPD), (100) the package comprising:
a circuit board (101); (Fig. 1A)
a flip chip (FC) IPD die (100 per [0031]) comprising a substrate material (110) and a capacitor (120) (the examiner is treating to limitation past or as optional) or inductor, the FC IPD die (100) mounted so that the capacitor (120) or inductor face an upper surface of the circuit board (101); (Fig. 1A)
a top-side cooling structure (102) thermally connected to a first planar surface of the FC IPD die (100), the first planar surface of the FC IPD die (100) comprising the substrate material (110); (Fig. 1A)
at least one first mechanical support (111) thermally connecting (by use of copper) the circuit board (101) to a second planar surface of the FC IPD die (100), the second planar surface of the FC IPD (100) comprising the at least one capacitor (120) or inductor. (Fig. 1A)
Balakrishnan does not disclose:
a second component positioned laterally adjacent to the FC IPD die and comprising a first planar surface and an opposite second planar surface, the second component mounted so the first planar surface of the second component faces the upper surface of the circuit board and at least one second mechanical support thermally connecting the circuit board to the opposite second planar surface of the second component;
a first height comprises (i) a height of the FC IPD die and (ii) a height of the at least one first mechanical support;
a second height comprises (i) a height of the second component and (ii) a height of the at least one second mechanical support;
the height of the FC IPD die is different that the height of the second component;
However, Hsieh discloses:
a second component (110b) positioned laterally adjacent to the FC IPD die (110a) and comprising a first planar surface and an opposite second planar surface, the second component (110b) mounted so the first planar surface of the second component faces the upper surface of the circuit board (102) and at least one second mechanical support (104) thermally connecting the circuit board (102) to the opposite second planar surface of the second component (110b); ([0079], Fig. 21)
a first height comprises (i) a height of the FC IPD die and (ii) a height of the at least one first mechanical support (104); ([0078], Fig. 21)
a second height comprises (i) a height of the second component and (ii) a height of the at least one second mechanical support; ([0078], Fig. 21)
the height of the FC IPD die (110a) is different that the height of the second component (110b); (Fig. 21) and
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Balakrishnan and Hsieh to arrive at the claimed invention in order to “accommodate multiple package heights on the same substrate or PCB 102 within the system 131.” (Hsieh, [0078])
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Hsieh Fig. 21 does not disclose:
the first height is substantially equal to the second height.
However, Hsieh Fig. 17 discloses:
the first height is substantially equal to the second height. (Fig. 17)
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It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Hsieh Fig. 21 and Fig. 17 to arrive at the claimed invention in order to “accommodate multiple package heights on the same substrate or PCB 102 within the system 131.” (Hsieh, [0078])
Regarding claim 2, Hsieh discloses the package of Claim 1, wherein a first height includes a height of the FC IPD die (110a), a height of the at least one first mechanical support (104), and a height of a thermally conductive bonding material (116 in Fig. 17 or 132 in Fig. 21).
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Hsieh for similar reasons mentioned beforehand.
Regarding claim 3, Hsieh discloses the package of Claim 2. Hsieh does not explicitly disclose wherein the first height is between 50 microns and 500 microns.
However, Balakrishnan does disclose:
“A layer 131 of thermally conductive material can have any suitable thickness, such as from about 50 μm to about 130 μm in one embodiment.” Per [0041]
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Balakrishnan for the first height is between 50 microns and 500 microns with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990) so as to “provide a relatively large heat transfer area to effectively move heat from the electronic component 220 outward toward a periphery of the package 200.” (Balakrishnan, [0049])
Regarding claim 4, Balakrishnan discloses the package of Claim 1. Balakrishnan does not explicitly disclose wherein the substrate material of the FC IPD die comprises silicon carbide (SiC).
However, Balakrishnan does disclose:
“For example, a substrate can be formed primarily of any suitable semiconductor material (e.g., a silicon, gallium, indium, germanium, or variations or combinations thereof, among other substrates)” per [0033])
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Balakrishnan for the substrate material of the FC IPD die comprises silicon carbide (SiC) since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 5, Balakrishnan discloses the package of Claim 1. Balakrishnan does not explicitly disclose wherein the substrate material of the FC IPD die comprises gallium nitride (GaN).
However, Balakrishnan does disclose:
“For example, a substrate can be formed primarily of any suitable semiconductor material (e.g., a silicon, gallium, indium, germanium, or variations or combinations thereof, among other substrates)” per [0033])
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Balakrishnan for the substrate material of the FC IPD die comprises gallium nitride (GaN) since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 6, Balakrishnan discloses the package of Claim 1, wherein the substrate material (110) of the FC IPD die (100) comprises at least one silicon substrate (per [0033], Fig. 1A).
Regarding claim 7, Balakrishnan discloses the package of Claim 1, wherein the substrate material (110) of the FC IPD die (100) at least partially fills a space between the at least one mechanical support (111) and the top-side cooling structure (102). (Fig. 1A)
Regarding claim 8, Balakrishnan discloses the package of Claim 7, wherein the substrate material (110) of the FC IPD die (100) extends across at least a major first surface of the FC IPD die (100). (Fig. 1A)
Regarding claim 9, Balakrishnan discloses the package of Claim 1, wherein the top-side cooling structure (102) is thermally connected to the FC IPD die (100) either directly or through a thermally conductive bonding material (103). ([0029], Fig. 1A)
Regrading claim 10, Balakrishnan discloses the package of Claim 1, wherein the top-side cooling structure (102) includes a planar portion that extends in parallel to the circuit board (101) along a length of the first planar surface of the FC IPD die (100). ([0029], Fig. 1A)
Regarding claim 11, Balakrishnan discloses the package of Claim 1, further comprising a gold (Au) backside layer (160) that at least partially fills a space between the first planar surface of the FC IPD die (100) and a thermally conductive bonding material (103) connecting the Au backside layer (160) to the top-side cooling structure (102). ([0044], Fig. 1A)
Regarding claim 13, Balakrishnan discloses the package of Claim 1. Balakrishnan does not disclose wherein the at least one mechanical support comprises at least one copper (Cu) pillar thermally connecting the FC IPD die and the circuit board.
However, Hsieh discloses:
at least one mechanical support (104) comprises at least one copper (Cu) pillar thermally connecting the FC IPD die (100a) and the circuit board (102). ([0041], Fig. 21)
Regarding claim 14, Balakrishnan discloses the package of Claim 1, wherein the at least one mechanical support (111) comprises at least one solder ball or solder bump thermally connecting FC IPD die (100) and the circuit board (101). ([0036], Fig. 1A)
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 20190252294 A1) in view of Balakrishnan et al. (US 20190206839 A1) as applied to claim 1 above, and further in view of Yeh et al. (US 20220310532 A1).
Regarding claim 12, Balakrishnan discloses the package of Claim 1. Balakrishnan does not disclose wherein the at least one mechanical support is a non-electrical component, and the at least one mechanical support is bonded to an electrical node of the circuit board for heat transfer.
However, Yeh discloses:
wherein the at least one mechanical support (520) is a non-electrical component (can be thermally conductive instead of electrically conductive per [0131]), and the at least one mechanical support (520) is bonded (by 510) to an electrical node (324c in Fig. 12A, [0106]) of the circuit board (300A) for heat transfer (per [0134]). (Fig. 17)
It would have been obvious to one skilled in the art to combine the teachings of Balakrishnan and Yeh for the at least one mechanical support is a non-electrical component, and the at least one mechanical support is bonded to an electrical node of the circuit board for heat transfer so that “the heat dissipation of the semiconductor device P1 in the package structure 1000B is improved.” (Yeh, [0134])
Claims 15-25 and 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan (US 20170084596 A1) in view of Hsieh et al. (US 20190252294 A1).
Regarding claim 15, Scanlan discloses a package comprising:
a circuit board (210); (Fig. 2A-4)
a flip chip (FC) radio-frequency (RF) power die (114a or 114b) comprising one or more transistors (per 0039]) on a first substrate material (112 per [0038]), and
at least one second mechanical support (182+184+186) thermally connecting the circuit board (210) to a second planar surface (bottom) of the FC RF power die (114a or 114b), the second planar surface (bottom) of the FC RF power die (114a or 114b) (Fig. 2A-4)
a FC IPD die (114a or 114b) comprising a second substrate material (112 per [0038]) and at least one capacitor (per [0039]) (the examiner is treating the limitation past or as optional) or inductor and the FC IPD die (114a or 114b) mounted so that the at least one capacitor (per [0039]) or inductor face the upper surface of the circuit board (210); (Fig. 2A-4)
at least one first mechanical support (182+184+186) thermally connecting the upper surface of the circuit board (210) to a second planar surface (bottom) of the FC IPD die (114a or 114b) comprising the at least one capacitor (per [0039]) or inductor; and
a top-side cooling structure (242) thermally connected to a first planar surface (top) of the FC IPD die (114a or 114b) comprising the second substrate material (212 per [0038]) and to a first planar surface (top) of the FC RF power die (114a or 114b) comprising the first substrate material.
a first height (annotated below) comprises (i) a height of the FC IPD die (114a or 114b) and (ii) a height of the at least one first mechanical support (182+184+186); (Fig. 4)
a second height (annotated below) comprises (i) a height of the FC RF power die (114a or 114b) and (ii) a height of the at least one second mechanical support (182+184+186); (Fig. 4)
and the first height is substantially equal to the second height. (Fig. 4)
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Scanlan does not explicitly disclose:
wherein the FC RF power die includes a gate terminal, a drain terminal, and a source terminal, the FC RF power die mounted so that the gate terminal, the drain terminal, and the source terminal face an upper surface of the circuit board; and
comprising the gate terminal, the drain terminal, and the source terminal;
However, these are inherent components of a transistor which is disclosed ion [0039].
Therefore, it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Scanlan to arrive at the claimed invention because transistors “control the flow of electrical current” ([0006]) which “enable the semiconductor device to perform high-speed calculations and other useful functions.” (Scanlan, [0006])
Scanlan does not disclose:
the height of the FC IPD die is different that the height of the FC RF power die;
However, Hsieh discloses:
the height of the FC IPD die (110a) is different that the height of the FC RF power die (110b); ([0078], Fig. 21)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Scalan and Hsieh to arrive at the claimed invention in order to “accommodate multiple package heights on the same substrate or PCB 102 within the system 131.” (Hsieh, [0078])
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Regarding claim 16, Scanlan discloses the package of Claim 15, wherein:
a first height (annotated above) includes a height of the FC IPD die (114a or 144b), a height of the at least one first mechanical support (182+184+186), and a height of a thermally conductive bonding material (224); ([0073], Fig. 4)
a second height (annotated above) includes a height of the FC RF power die (114a or 144b), a height of the at least one second mechanical support (182+184+186), and a height of a thermally conductive bonding material (224); ([0073], Fig. 4) and
the first height is about equal to the second height. (Fig. 4)
Regarding claim 17, Scanlan discloses the package of Claim 16. Scanlan does not explicitly disclose wherein the first height and second height are between 50 microns and 500 microns.
However, Scanlan does disclose, “The molded core units 200 can comprise a thickness or height T2 in a range of 0.15-1.1 millimeters (mm), with the maximum thickness of about 1.1 mm and a minimum thickness of about 0.15 mm” in [0065].
Therefore, It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Scanlan for the first height and second height are between 50 microns and 500 microns with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990) so as to “produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products.” (Scanlan, [0008])
Regarding claim 18, Scanlan discloses the package of Claim 15, wherein the second substrate material (112) of the FC IPD die (114a or 144b), and the first substrate material (112) of the transistor die (114a or 144b) comprise silicon carbide (SiC). ([0038], Fig. 2A)
Regarding claim 19, Scanlan discloses the package of Claim 15. Scanlan does not explicitly disclose wherein the second substrate material of the FC IPD die and the first substrate material of the transistor die comprise gallium nitride (GaN).
Scanlan does disclose:
“a base substrate material 112, such as, without limitation, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support.” In [0038]
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Scanlan for the second substrate material of the FC IPD die and the first substrate material of the transistor die comprise gallium nitride (GaN) since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 20, Scanlan discloses the package of Claim 15, wherein the second substrate material (112) of the FC IPD die (114a or 114b) and the first substrate material (112) of the transistor die (114a or 114b) comprise at least one silicon substrate. ([0038])
Regarding claim 21, Scanlan discloses the package of Claim 15, wherein the second substrate material (112) of the FC IPD die (114a or 114b) at least partially fills a space between the at least one mechanical support (182+184+186) of the FC IPD die (114a or 114b) and the top-side cooling structure (242). (Fig. 2A-4)
Regarding claim 22, Scanlan discloses the package of Claim 21, wherein the second substrate material (112) of the FC IPD die (114) extends across at least a major first surface of the FC IPD die (114). (Fig. 2A)
Regarding claim 23, Scanlan discloses the package of Claim 15, wherein the top-side cooling structure (242) is thermally connected to the first planar surface (top) of the FC IPD die (114a or 114b) either directly or through a thermally conductive bonding material (224). ([0074], Fig. 4)
Regarding claim 24, Scanlan discloses the package of Claim 15, wherein the top-side cooling structure (242) is thermally connected to the first planar surface (top) of the FC RF power die (114a or 114b) either directly or through a thermally conductive bonding material (224). ([0074], Fig. 4)
Regarding claim 25, Scanlan discloses the package of Claim 15, wherein the top-side cooling structure (242) includes a planar portion (bottom) that extends in parallel to the circuit board (210) along a length of the first planar surface (top) of the FC IPD die (114a or 114b) and a length of the first planar surface (top) of the FC RF power die (114a or 114b). (Fig. 4)
Regarding claim 29, Scanlan discloses the package of Claim 15, wherein the at least one mechanical support (182+184+186) of the FC IPD die (114a or 114b) comprises at least one copper (Cu) pillar (per [0062]) thermally connecting the FC IPD die (114a or 114b) and the circuit board (210). (Fig. 4)
Regarding claim 30, Scanlan discloses the package of Claim 15, wherein the at least one mechanical support (182+184+186) of the FC IPD die (114a or 114b) comprises at least one solder ball (per [0062]) or solder bump (per [0062]) thermally connecting the first planar surface of the FC IPD die (114a or 114b) and the upper surface of the circuit board (210). (Fig. 4)
Regarding claim 31, Scanlan discloses the package of Claim 15, further comprising an overmold material (220) extending from the circuit board (210) to the top-side cooling structure (242) and laterally across a region between the FC RF power die (114a or 114b) and FC IPD die (114a or 114b). (Fig. 4)
Claims 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan (US 20170084596 A1) in view of Hsieh et al. (US 20190252294 A1) as applied to claim 15 above, and further in view of Balakrishnan et al. (US 20190206839 A1).
Regarding claim 26, Scanlan in view of Hsieh discloses the package of Claim 15. Scanlan in view of Hsieh do not disclose further comprising a gold (Au) backside layer that at least partially fills a space between the first planar surface of the FC IPD die and the top-side cooling structure.
However, Balakrishnan discloses:
further comprising a gold (Au) backside layer (160) that at least partially fills a space between the first planar surface of the FC IPD die (100) and the top-side cooling structure (102). ([0044], Fig. 1A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Scanlan, Hsieh and Balakrishnan to have a gold (Au) backside layer that at least partially fills a space between the first planar surface of the FC IPD die and the top-side cooling structure in order to “provide a thermal path away from the substrate 110 (e.g., about a periphery of the package 100 to the top of the electronic device 121) where heat can be dissipated more effectively (e.g., by the thermal solution 102). As a result, thermal headroom for the electronic component 120 can be increased, which can allow the electronic component 120 to operate at higher performance for longer duration using passive heat dissipation techniques. (Balakrishnan, [0040])
Regarding claim 27, Scanlan in view of Hsieh discloses the package of Claim 15. Scanlan in view of Hsieh do not disclose further comprising a gold (Au) backside layer that at least partially fills a space between the first planar surface of the FC RF power die and a thermally conductive bonding material connecting the Au backside layer to the top-side cooling structure.
However, Balakrishnan discloses:
further comprising a gold (Au) backside layer (160) that at least partially fills a space between the first planar surface of the FC RF power die (100) and a thermally conductive bonding material (103) connecting the Au backside layer (160) to the top-side cooling structure (102). ([0044], Fig. 1A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Scanlan, Hsieh and Balakrishnan to have a gold (Au) backside layer that at least partially fills a space between the first planar surface of the FC RF power die and a thermally conductive bonding material connecting the Au backside layer to the top-side cooling structure in order to “provide a thermal path away from the substrate 110 (e.g., about a periphery of the package 100 to the top of the electronic device 121) where heat can be dissipated more effectively (e.g., by the thermal solution 102). As a result, thermal headroom for the electronic component 120 can be increased, which can allow the electronic component 120 to operate at higher performance for longer duration using passive heat dissipation techniques. (Balakrishnan, [0040])
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Scanlan (US 20170084596 A1) in view of Hsieh et al. (US 20190252294 A1) as applied to claim 15 above, and further in view of Yeh et al. (US 20220310532 A1).
Regarding claim 28, Scanlan in view of Hsieh discloses the package of Claim 15. Scanlan in view of Sieh do not disclose wherein the at least one mechanical support of the FC IPD die is a non-electrical component, and the at least one mechanical support of the FC IPD die is bonded to an electrical node of the circuit board for heat transfer.
However, Yeh discloses:
wherein the at least one mechanical support (520) of the FC IPD die (230 or 240) is a non-electrical component (can be thermally conductive instead of electrically conductive per [0131]), and the at least one mechanical support (520) of the FC IPD die (230 or 240) is bonded (by 510) to an electrical node (324c in Fig. 12A, [0106]) of the circuit board (300A) for heat transfer (per [0134]). (Fig. 17)
It would have been obvious to one skilled in the art to combine the teachings of Scanlan, Hsieh and Yeh for the at least one mechanical support of the FC IPD die is a non-electrical component, and the at least one mechanical support of the FC IPD die is bonded to an electrical node of the circuit board for heat transfer so that “the heat dissipation of the semiconductor device P1 in the package structure 1000B is improved.” (Yeh, [0134])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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