DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of 03/10/2026 in the reply filed on 09/13/2023 is acknowledged. The traversal is on the ground(s) that “the application provides teaching of common aspects between species”. This is found persuasive. In response, the examiner will examiner claims 1-31 accordingly.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “mechanical support 116” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 16 objected to because of the following informalities: The examiner is unsure what value relates to “the first height is about equal to the second height”. The examiner requests an explanation for the record.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6-11 and 14 are rejected under 35 U.S.C. 102(A)(1)/(a)(2) as being anticipated by Balakrishnan et al. (US 20190206839 A1).
Regarding claim 1, Balakrishnan discloses a package including an integrated passive device (IPD), (100) the package comprising:
a circuit board (101); (Fig. 1A)
a flip chip (FC) IPD die (100 per [0031]) comprising a substrate material (110) and at least one capacitor (120) (the examiner is treating to limitation past or as optional) or inductor, the FC IPD die (100) mounted so that the at least one capacitor (120) or inductor face an upper surface of the circuit board (101); (Fig. 1A)
a top-side cooling structure (102) thermally connected to a first planar surface of the FC IPD die (100), the first planar surface of the FC IPD die (100) comprising the substrate material (110); (Fig. 1A) and
at least one first mechanical support (111) thermally connecting (by use of copper) the circuit board (101) to a second planar surface of the FC IPD die (100), the second planar surface of the FC IPD (100) comprising the at least one capacitor (120) or inductor. (Fig. 1A)
Regarding claim 2, Balakrishnan discloses the package of Claim 1, wherein a first height includes a height of the FC IPD die (100), a height of the at least one first mechanical support (111), and a height of a thermally conductive bonding material (103). ([0029], Fig. 1A)
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Regarding claim 6, Balakrishnan discloses the package of Claim 1, wherein the substrate material (110) of the FC IPD die (100) comprises at least one silicon substrate (per [0033], Fig. 1A).
Regarding claim 7, Balakrishnan discloses the package of Claim 1, wherein the substrate material (110) of the FC IPD die (100) at least partially fills a space between the at least one mechanical support (111) and the top-side cooling structure (102). (Fig. 1A)
Regarding claim 8, Balakrishnan discloses the package of Claim 7, wherein the substrate material (110) of the FC IPD die (100) extends across at least a major first surface of the FC IPD die (100). (Fig. 1A)
Regarding claim 9, Balakrishnan discloses the package of Claim 1, wherein the top-side cooling structure (102) is thermally connected to the FC IPD die (100) either directly or through a thermally conductive bonding material (103). ([0029], Fig. 1A)
Regrading claim 10, Balakrishnan discloses the package of Claim 1, wherein the top-side cooling structure (102) includes a planar portion that extends in parallel to the circuit board (101) along a length of the first planar surface of the FC IPD die (100). ([0029], Fig. 1A)
Regarding claim 11, Balakrishnan discloses the package of Claim 1, further comprising a gold (Au) backside layer (160) that at least partially fills a space between the first planar surface of the FC IPD die (100) and a thermally conductive bonding material (103) connecting the Au backside layer (160) to the top-side cooling structure (102). ([0044], Fig. 1A)
Regarding claim 14, Balakrishnan discloses the package of Claim 1, wherein the at least one mechanical support (111) comprises at least one solder ball or solder bump thermally connecting FC IPD die (100) and the circuit board (101). ([0036], Fig. 1A)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (US 20190206839 A1).
Regarding claim 3, Balakrishnan discloses the package of Claim 2. , Balakrishnan does not explicitly disclose wherein the first height is between 50 microns and 500 microns.
However, Balakrishnan does disclose:
“A layer 131 of thermally conductive material can have any suitable thickness, such as from about 50 μm to about 130 μm in one embodiment.” Per [0041]
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Balakrishnan for the first height is between 50 microns and 500 microns with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990) so as to “provide a relatively large heat transfer area to effectively move heat from the electronic component 220 outward toward a periphery of the package 200.” (Balakrishnan, [0049])
Regarding claim 4, Balakrishnan discloses the package of Claim 1. Balakrishnan does not explicitly disclose wherein the substrate material of the FC IPD die comprises silicon carbide (SiC).
However, Balakrishnan does disclose:
“For example, a substrate can be formed primarily of any suitable semiconductor material (e.g., a silicon, gallium, indium, germanium, or variations or combinations thereof, among other substrates)” per [0033])
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Balakrishnan for the substrate material of the FC IPD die comprises silicon carbide (SiC) since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 5, Balakrishnan discloses the package of Claim 1. Balakrishnan does not explicitly disclose wherein the substrate material of the FC IPD die comprises gallium nitride (GaN).
However, Balakrishnan does disclose:
“For example, a substrate can be formed primarily of any suitable semiconductor material (e.g., a silicon, gallium, indium, germanium, or variations or combinations thereof, among other substrates)” per [0033])
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Balakrishnan for the substrate material of the FC IPD die comprises gallium nitride (GaN) since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (US 20190206839 A1) as applied to claim 1 above, and further in view of Yeh et al. (US 20220310532 A1).
Regarding claim 12, Balakrishnan discloses the package of Claim 1. Balakrishnan does not disclose wherein the at least one mechanical support is a non-electrical component, and the at least one mechanical support is bonded to an electrical node of the circuit board for heat transfer.
However, Yeh discloses:
wherein the at least one mechanical support (520) is a non-electrical component (can be thermally conductive instead of electrically conductive per [0131]), and the at least one mechanical support (520) is bonded (by 510) to an electrical node (324c in Fig. 12A, [0106]) of the circuit board (300A) for heat transfer (per [0134]). (Fig. 17)
It would have been obvious to one skilled in the art to combine the teachings of Balakrishnan and Yeh for the at least one mechanical support is a non-electrical component, and the at least one mechanical support is bonded to an electrical node of the circuit board for heat transfer so that “the heat dissipation of the semiconductor device P1 in the package structure 1000B is improved.” (Yeh, [0134])
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (US 20190206839 A1) as applied to claim 1 above, and further in view of Sankman et al. (US 20200357721 A1).
Regarding claim 13, Balakrishnan discloses the package of Claim 1. Balakrishnan does not disclose wherein the at least one mechanical support comprises at least one copper (Cu) pillar thermally connecting the FC IPD die and the circuit board.
However, Sankman does disclose:
the at least one mechanical support (122) comprises at least one copper (Cu) pillar (per [0022]) thermally connecting the FC IPD die (102) and the circuit board (140). ([0022], Fig. 1)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Balakrishnan and Sankman for the at least one mechanical support comprises at least one copper (Cu) pillar thermally connecting the FC IPD die and the circuit board as a conventional choice in the art in order to “physically and electrically connect the dies 104 to the substrate 106.” (Sankman, [0022])
Claims 15-25 and 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan (US 20170084596 A1).
Regarding claim 15, Scanlan discloses a package comprising:
a circuit board (210); (Fig. 2A-4)
a flip chip (FC) radio-frequency (RF) power die (114a or 114b) comprising one or more transistors (per 0039]) on a first substrate material (112 per [0038]), and
at least one second mechanical support (182+184+186) thermally connecting the circuit board (210) to a second planar surface (bottom) of the FC RF power die (114a or 114b), the second planar surface (bottom) of the FC RF power die (114a or 114b) (Fig. 2A-4)
a FC IPD die (114a or 114b) comprising a second substrate material (112 per [0038]) and at least one capacitor (per [0039]) (the examiner is treating the limitation past or as optional) or inductor and the FC IPD die (114a or 114b) mounted so that the at least one capacitor (per [0039]) or inductor face the upper surface of the circuit board (210); (Fig. 2A-4)
at least one first mechanical support (182+184+186) thermally connecting the upper surface of the circuit board (210) to a second planar surface (bottom) of the FC IPD die (114a or 114b) comprising the at least one capacitor (per [0039]) or inductor; and
a top-side cooling structure (242) thermally connected to a first planar surface (top) of the FC IPD die (114a or 114b) comprising the second substrate material (212 per [0038]) and to a first planar surface (top) of the FC RF power die (114a or 114b) comprising the first substrate material.
Scanlan does not explicitly disclose:
wherein the FC RF power die includes a gate terminal, a drain terminal, and a source terminal, the FC RF power die mounted so that the gate terminal, the drain terminal, and the source terminal face an upper surface of the circuit board; and
comprising the gate terminal, the drain terminal, and the source terminal;
However, these are inherent components of a transistor which is disclosed ion [0039].
Therefore, it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Scanlan to arrive at the claimed invention because transistors “control the flow of electrical current” ([0006]) which “enable the semiconductor device to perform high-speed calculations and other useful functions.” (Scanlan, [0006])
Regarding claim 16, Scanlan discloses the package of Claim 15, wherein:
a first height (annotated below) includes a height of the FC IPD die (114a or 144b), a height of the at least one first mechanical support (182+184+186), and a height of a thermally conductive bonding material (224); ([0073], Fig. 4)
a second height (annotated below) includes a height of the FC RF power die (114a or 144b), a height of the at least one second mechanical support (182+184+186), and a height of a thermally conductive bonding material (224); ([0073], Fig. 4) and
the first height (annotated below) is about equal to the second height (annotated below). (Fig. 4a)
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Regarding claim 17, Scanlan discloses the package of Claim 16. Scanlan does not explicitly disclose wherein the first height and second height are between 50 microns and 500 microns.
However, Scanlan does disclose, “The molded core units 200 can comprise a thickness or height T2 in a range of 0.15-1.1 millimeters (mm), with the maximum thickness of about 1.1 mm and a minimum thickness of about 0.15 mm” in [0065].
Therefore, It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Scanlan for the first height and second height are between 50 microns and 500 microns with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990) so as to “produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products.” (Scanlan, [0008])
Regarding claim 18, Scanlan discloses the package of Claim 15, wherein the second substrate material (112) of the FC IPD die (114a or 144b), and the first substrate material (112) of the transistor die (114a or 144b) comprise silicon carbide (SiC). ([0038], Fig. 2A)
Regarding claim 19, Scanlan discloses the package of Claim 15. Scanlan does not explicitly disclose wherein the second substrate material of the FC IPD die and the first substrate material of the transistor die comprise gallium nitride (GaN).
Scanlan does disclose:
“a base substrate material 112, such as, without limitation, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support.” In [0038]
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Scanlan for the second substrate material of the FC IPD die and the first substrate material of the transistor die comprise gallium nitride (GaN) since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 20, Scanlan discloses the package of Claim 15, wherein the second substrate material (112) of the FC IPD die (114a or 114b) and the first substrate material (112) of the transistor die (114a or 114b) comprise at least one silicon substrate. ([0038])
Regarding claim 21, Scanlan discloses the package of Claim 15, wherein the second substrate material (112) of the FC IPD die (114a or 114b) at least partially fills a space between the at least one mechanical support (182+184+186) of the FC IPD die (114a or 114b) and the top-side cooling structure (242). (Fig. 2A-4)
Regarding claim 22, Scanlan discloses the package of Claim 21, wherein the second substrate material (112) of the FC IPD die (114) extends across at least a major first surface of the FC IPD die (114). (Fig. 2A)
Regarding claim 23, Scanlan discloses the package of Claim 15, wherein the top-side cooling structure (242) is thermally connected to the first planar surface (top) of the FC IPD die (114a or 114b) either directly or through a thermally conductive bonding material (224). ([0074], Fig. 4)
Regarding claim 24, Scanlan discloses the package of Claim 15, wherein the top-side cooling structure (242) is thermally connected to the first planar surface (top) of the FC RF power die (114a or 114b) either directly or through a thermally conductive bonding material (224). ([0074], Fig. 4)
Regarding claim 25, Scanlan discloses the package of Claim 15, wherein the top-side cooling structure (242) includes a planar portion (bottom) that extends in parallel to the circuit board (210) along a length of the first planar surface (top) of the FC IPD die (114a or 114b) and a length of the first planar surface (top) of the FC RF power die (114a or 114b). (Fig. 4)
Regarding claim 29, Scanlan discloses the package of Claim 15, wherein the at least one mechanical support (182+184+186) of the FC IPD die (114a or 114b) comprises at least one copper (Cu) pillar (per [0062]) thermally connecting the FC IPD die (114a or 114b) and the circuit board (210). (Fig. 4)
Regarding claim 30, Scanlan discloses the package of Claim 15, wherein the at least one mechanical support (182+184+186) of the FC IPD die (114a or 114b) comprises at least one solder ball (per [0062]) or solder bump (per [0062]) thermally connecting the first planar surface of the FC IPD die (114a or 114b) and the upper surface of the circuit board (210). (Fig. 4)
Regarding claim 31, Scanlan discloses the package of Claim 15, further comprising an overmold material (220) extending from the circuit board (210) to the top-side cooling structure (242) and laterally across a region between the FC RF power die (114a or 114b) and FC IPD die (114a or 114b). (Fig. 4)
Claims 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan (US 20170084596 A1) as applied to claim 15 above, and further in view of Balakrishnan et al. (US 20190206839 A1).
Regarding claim 26, Scanlan discloses the package of Claim 15. Scanlan does not disclose further comprising a gold (Au) backside layer that at least partially fills a space between the first planar surface of the FC IPD die and the top-side cooling structure.
However, Balakrishnan discloses:
further comprising a gold (Au) backside layer (160) that at least partially fills a space between the first planar surface of the FC IPD die (100) and the top-side cooling structure (102). ([0044], Fig. 1A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Scanlan and Balakrishnan to have a gold (Au) backside layer that at least partially fills a space between the first planar surface of the FC IPD die and the top-side cooling structure in order to “provide a thermal path away from the substrate 110 (e.g., about a periphery of the package 100 to the top of the electronic device 121) where heat can be dissipated more effectively (e.g., by the thermal solution 102). As a result, thermal headroom for the electronic component 120 can be increased, which can allow the electronic component 120 to operate at higher performance for longer duration using passive heat dissipation techniques. (Balakrishnan, [0040])
Regarding claim 27, Scanlan discloses the package of Claim 15. Scanlan does not disclose further comprising a gold (Au) backside layer that at least partially fills a space between the first planar surface of the FC RF power die and a thermally conductive bonding material connecting the Au backside layer to the top-side cooling structure.
However, Balakrishnan discloses:
further comprising a gold (Au) backside layer (160) that at least partially fills a space between the first planar surface of the FC RF power die (100) and a thermally conductive bonding material (103) connecting the Au backside layer (160) to the top-side cooling structure (102). ([0044], Fig. 1A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Scanlan and Balakrishnan to have a gold (Au) backside layer that at least partially fills a space between the first planar surface of the FC RF power die and a thermally conductive bonding material connecting the Au backside layer to the top-side cooling structure in order to “provide a thermal path away from the substrate 110 (e.g., about a periphery of the package 100 to the top of the electronic device 121) where heat can be dissipated more effectively (e.g., by the thermal solution 102). As a result, thermal headroom for the electronic component 120 can be increased, which can allow the electronic component 120 to operate at higher performance for longer duration using passive heat dissipation techniques. (Balakrishnan, [0040])
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Scanlan (US 20170084596 A1) as applied to claim 15 above, and further in view of Yeh et al. (US 20220310532 A1).
Regarding claim 28, Scanlan discloses the package of Claim 15. Scanlan does not disclose wherein the at least one mechanical support of the FC IPD die is a non-electrical component, and the at least one mechanical support of the FC IPD die is bonded to an electrical node of the circuit board for heat transfer.
However, Yeh discloses:
wherein the at least one mechanical support (520) of the FC IPD die (230 or 240) is a non-electrical component (can be thermally conductive instead of electrically conductive per [0131]), and the at least one mechanical support (520) of the FC IPD die (230 or 240) is bonded (by 510) to an electrical node (324c in Fig. 12A, [0106]) of the circuit board (300A) for heat transfer (per [0134]). (Fig. 17)
It would have been obvious to one skilled in the art to combine the teachings of Scanlan and Yeh for the at least one mechanical support of the FC IPD die is a non-electrical component, and the at least one mechanical support of the FC IPD die is bonded to an electrical node of the circuit board for heat transfer so that “the heat dissipation of the semiconductor device P1 in the package structure 1000B is improved.” (Yeh, [0134])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/
Examiner
Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights