DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of species E/fig. 14, reflected in claims 1-6, 8-12, 14, 20, 23-28 and 40 in the reply filed on 04/09/2026 is acknowledged. Claims 13, 15-19 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
A. Elements, ‘active region’, ‘inactive region’, ‘a first shunt contact structure’, ‘a second shunt contact structure’ must be shown or the feature(s) canceled from the claim 1. Applicant’s drawings fail to mark an inactive region and do not show a clear boundary between the active region and the inactive region. Applicant’s drawings also fail to show the shunt contact structures located in an inactive region.
B. Elements, ‘first shunt contact structure’, ‘second shunt contact structure’, ‘source terminal’ must be shown or the feature(s) canceled from the claim 6. Applicant’s drawings do not show a connection between shunt contact structures and the source terminal.
C. Applicant’s fig. 9 is objected as it marks ‘shunt contact structures’ as 335. It should be ‘355’.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8-12, 14, 23-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miura et al. (US 20120205669 A1, hereinafter Miura‘669).
Regarding independent claim 1, Miura‘669 teaches, “A power semiconductor device (fig. 1-10, ¶ [0031] - ¶ [0095]), comprising:
a semiconductor structure (fig. 1-4) comprising an active region and an inactive region (comprising P-well regions 42, 44), the active region comprising a plurality of unit cells;
a gate structure, wherein at least a portion of the gate structure (11, 12) is on the inactive region;
a first shunt contact structure (62, 71b, fig. 3) at least partially on the inactive region;
a second shunt contact structure (62, 71b, fig. 3) at least partially on the inactive region; and
a balancing shunt structure (63, 71c) at least partially on the inactive region (44)”.
Regarding claim 2, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the first shunt contact structure provides a first shunt path for a first displacement current through the inactive region, wherein the second shunt contact structure provides a second shunt path for a second displacement current through the inactive region, wherein the balancing shunt structure reduces a difference between the first displacement current through the first shunt path and the second displacement current through the second shunt path (¶ [0068] - ¶ [0075] etc.)”.
Regarding claim 3, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the first shunt contact structure (62, fig. 1-2) is adjacent a first side of the gate structure (11) and the balancing shunt structure (63) is adjacent a second side of the gate structure, the second side being opposite the first side (referring to fig. 1-2. Elements 62 and 63 are on both of left and right sides of the gate structure/gate pad 11)”.
Regarding claim 4, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the balancing shunt structure (63) is between the gate structure (11) and an edge termination region (40)”.
Regarding claim 5, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein at least a portion of the balancing shunt structure (63, 71c) is directly on the inactive region of the semiconductor structure (fig. 3)”.
Regarding claim 6, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the first shunt contact structure and the second shunt contact structure (62, 71b, fig. 3-4) are coupled to a source terminal for the power semiconductor device, wherein the balancing shunt structure 63, 71c) is not coupled to the source terminal (80)”.
Regarding claim 8, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the gate structure comprises a gate pad (11, fig. 1) and a gate runner (12)”.
Regarding claim 9, Miura‘669 further teaches, “The power semiconductor device of claim 8, wherein the first shunt contact structure (62, fig. 1-2) is adjacent to the gate pad (11) and the second shunt contact structure (62, fig. 1-2) is adjacent to the gate runner (12)”.
Regarding claim 10, Miura‘669 further teaches, “The power semiconductor device of claim 8, wherein the gate runner (12, fig. 1, fig. 4) is a peripheral gate runner located around at least a part of a peripheral portion of the power semiconductor device”.
Regarding claim 11, Miura‘669 further teaches, “The power semiconductor device of claim 10, wherein the balancing shunt structure comprises a balancing ring structure (63, fig. 2-4) located around at least a portion of the peripheral gate runner (12)”.
Regarding claim 12, Miura‘669 further teaches, “The power semiconductor device of claim 11, wherein the balancing ring structure comprises a discontinuous ring structure (made by holes 63 which are not connected to each other) with one or more breaks”.
Regarding claim 14, Miura‘669 further teaches, “The power semiconductor device of claim 8, wherein the gate pad (11, fig. 1) is located in a peripheral portion of the power semiconductor device”.
Regarding claim 23, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the power semiconductor device does not have a source runner in a peripheral portion of the power semiconductor device (fig. 1-4)”.
Regarding claim 24, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the first shunt contact structure and the second shunt contact structure are a part of a plurality of shunt contact structures that are in at least a partial ring arrangement adjacent to the gate structure (see the ring structures 62)”.
Regarding claim 25, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the semiconductor structure comprises a wide bandgap semiconductor (silicon carbide, ¶ [0031])”.
Regarding claim 26, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the semiconductor structure comprises silicon carbide (¶ [0031])”.
Regarding claim 27, Miura‘669 further teaches, “The power semiconductor device of claim 1, wherein the plurality of unit cells comprise one or more silicon carbide-based MOSFET transistor cells (¶ [0031] - ¶ [0032])”.
Claims 28 and 40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hino; Shiro et al. (US 20130020587 A1, hereinafter Hino‘587).
Regarding independent claim 28, Hino‘587 teaches, “A power semiconductor device (fig. 1-26; ¶ [0042] - ¶ [0155]), comprising:
a semiconductor structure (fig. 1-4) comprising an active region and an inactive region (comprising P-well regions 43), the active region comprising a plurality of unit cells;
a field insulating layer (31) at least partially on the inactive region;
a gate structure (11, 12, fig. 3-4) at least partially on the field insulating layer (31);
a shunt contact structure (63, 71c) extending at least partially through the field insulating layer (31); and
a balancing shunt structure (62, 71b) at least partially on the inactive region (43)”.
Regarding independent claim 40, Hino‘587 teaches, “A power semiconductor device (fig. 1-26; ¶ [0042] - ¶ [0155]), comprising:
a semiconductor structure (fig. 1-4) comprising an active region and an inactive region (comprising P-well regions 43), the active region comprising a plurality of unit cells;
a gate structure (11, 12, fig. 3-4), wherein at least a portion of the gate structure is on the inactive region;
a plurality of shunt contact structures (62, 71b) at least partially on the inactive region; and
a balancing shunt structure (63, 71c) at least partially on the inactive region; and
wherein the balancing shunt structure is operable to balance a displacement current associated with the plurality of shunt contact structures (¶ [0068] - ¶ [0075] etc.)”.
Claim 1 is again rejected under 35 U.S.C. 102(a)(2) as being anticipated by UCHIDA; Kosuke (US 20230335632 A1, hereinafter Uchida‘632).
Regarding independent claim 1, Uchida‘632 teaches, “A power semiconductor device (fig. 1-39; ¶ [0058] – [0128]), comprising:
a semiconductor structure comprising an active region (120A, fig. 1) and an inactive region (120B), the active region comprising a plurality of unit cells;
a gate structure (84, 85), wherein at least a portion of the gate structure is on the inactive region (120B);
a first shunt contact structure (121) at least partially on the inactive region (120B);
a second shunt contact structure (121) at least partially on the inactive region (120B); and
a balancing shunt structure (111) at least partially on the inactive region (120B)”.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 20, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: wherein the first shunt contact structure, the second shunt contact structure, and the balancing shunt structure extend through the field insulating layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
Prosecution Insights