CTNF 18/466,565 CTNF 79655 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of invention II, species 3, in the reply filed on February 26, 2026 is acknowledged. Claims 1-15 have been cancelled and claims 21-25 have been added. Accordingly, claims 16-35 are pending in the application. Claim Objections 07-29-01 AIA Claim (s) 17-19 and 31-35 is/are objected to because of the following informalities: With respect to claim 17, in line 6 of the claim “to depositing a material” should read “to deposit a material”. Claims 18-19 which either directly or indirectly depend from claim 17 and which inherit issues of claim 17 are objected to for similar reason. With respect to claim 31, in line 8 of the claim “an protective layer” should read “a protective layer”. Claims 32-35 which either directly or indirectly depend from claim 31 and which inherit issues of claim 31 are objected to for similar reason . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-31-01 Claim(s) 35 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. With respect to claim 35, as currently presented the claim requires that an inner spacer (e.g. 117, Fig. 17C and 18A-18B) comprises a first portion embedded in a source/drain epitaxial structure (e.g. 140, Fig. 17C) and a second portion vertically between the inner spacer and one of the semiconductor channel layers. The specification, however, does not provide any description of this subject matter. Specifically, while the specification discusses that protective layer 120 can be include a portion (e.g. 120M, Fig. 17C) embedded in source/drain epitaxial structure (140, Fig. 17C and ¶[0057] of the specification as published) and a portion (e.g. 120E, Fig. 17C and ¶[0056] of the specification as published) vertically between the inner space and one of the semiconductor channel layers, the specification fails to disclose and inner spacer that comprises a first portion embedded in a source/drain epitaxial structure and a second portion vertically between the inner spacer and one of the semiconductor channel layers. Accordingly, the claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. 07-34-01 Claim(s) 35 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With respect to claim 35, as currently presented the claim requires that an inner spacer (e.g. 117, Fig. 17C and 18A-18B) comprises a first portion embedded in a source/drain epitaxial structure (e.g. 140, Fig. 17C) and a second portion vertically between the inner spacer and one of the semiconductor channel layers. It is unclear, however, how a second portion of the inner spacer can be vertically between itself and the semiconductor channel layers. For purpose of compact prosecution, it will be assumed that the inner spacer has a portion between semiconductor channel layers. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 16 and 20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yao et al. (US 2021/0028297, hereinafter “Yao”) . Regarding claim 16, Yao teaches in Figs. 1 through 13 (Figs. 1B, 7 and 13B shown below) and related text a method, comprising: forming semiconductor channel layers (e.g. Si, 107, Fig. 1B and ¶[0037]) over a substrate (101, Fig. 1B and ¶[0036]) ; forming inner spacers (e.g. SiO, 113’, Fig. 6 and ¶[0049]) between adjacent two of the semiconductor channel layers (107, Fig. 6) ; selectively forming protective layers (e.g. BN, 115, Fig. 7 and ¶[0051]) on outer sidewalls of the inner spacers (113’, Fig. 7) ; forming source/drain epitaxial structures (120, Fig. 9B and ¶[0053]) on opposite sides of each of the semiconductor channel layers (107, Fig. 9B) ; and forming a gate structure (130, Fig. 13B and ¶[0059]) wrapping around each of the semiconductor channel layers. PNG media_image1.png 477 421 media_image1.png Greyscale PNG media_image2.png 659 408 media_image2.png Greyscale PNG media_image3.png 661 423 media_image3.png Greyscale Regarding claim 20 (16), Yao teaches wherein the protective layers are made of boron nitride (¶[0051]) , wherein the boron nitride has a higher deposition rate on the outer sidewalls of the inner spacers than on sidewalls of the semiconductor channel layers (i.e. since Yao teaches the same materials for the inner spacer and semiconductor channel layers as those disclosed by the applicant, the disposition rate of BN on the sidewall spacer would be higher than on the semiconductor channel ¶¶[0036] and [0049]) . 07-15-aia AIA Claim(s) 31 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chen et al (US 2023/0035791, hereinafter “Chen”) . Regarding claim 31, Chen teaches in Figs. 1 through 2 (Figs. 2A, 2D and 2F shown below) and related text a method, comprising: forming semiconductor channel layers (106, Fig. 2A and ¶[0016]) over a substrate (102, Fig. 2A and ¶[0016]) ; depositing an inner spacer material (126a, Fig. 2A and ¶[0030]) filling a gap (124, Fig. 2A and ¶[0030]) between adjacent two of the semiconductor channel layers (106, Fig. 2A) ; performing an etching (Fig. 2A and ¶[0030]) process to remove a portion of the inner spacer material outside the gap (Fig. 2A) , leaving a remaining portion of the inner spacer material in the gap as an inner spacer, wherein the inner spacer comprises a first recess (Fig. 2A, i.e. recess in 126a is similar to the recess 124 in 104) ; forming a protective layer (126b, Fig. 2C and ¶[0035]) along a surface of the inner spacer and filling the first recess of the inner spacer (Fig. 2C) ; forming a source/drain epitaxial structure (130, Fig. 2F and ¶[0043]) alongside the semiconductor channel layers; and forming a gate structure (136, Fig. 2F and ¶[0052]) over the semiconductor channel layers (Fig. 2F) . PNG media_image4.png 589 631 media_image4.png Greyscale PNG media_image5.png 589 729 media_image5.png Greyscale PNG media_image6.png 580 717 media_image6.png Greyscale 07-15-aia AIA Claim(s) 31-34 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hashemi et al. (US 2023/0187532, hereinafter “Hashemi”) and Regarding claim 31, Wang teaches in Figs. 1-16 (Figs. 5-8 and 16 shown below) and related text a method, comprising: forming semiconductor channel layers (140, Fig. 1 and ¶[0030]) over a substrate (110, Fig. 1 and ¶[0030]) ; depositing an inner spacer material (190, Fig. 5 and ¶[0044]) filling a gap (Fig. 5 and ¶[0044]) between adjacent two of the semiconductor channel layers (142, Fig. 5) ; performing an etching (Fig. 6, ¶¶[0047]-[0051]) process to remove a portion of the inner spacer material outside the gap (Figs. 6-7) , leaving a remaining portion of the inner spacer material in the gap as an inner spacer, wherein the inner spacer comprises a first recess (i.e. part of the recess formed in 195 along the bottom surface of the top 142, Figs. 6-7) ; forming a protective layer (200, Fig. 8 and ¶[0052]) along a surface of the inner spacer and filling the first recess of the inner spacer (Fig. 8) ; forming a source/drain epitaxial structure (210, Fig. 9 and ¶[0056]) alongside the semiconductor channel layers (Fig. 9) ; and forming a gate structure (260, Fig. 16 and ¶[0082]) over the semiconductor channel layers (Fig. 16) . PNG media_image7.png 625 562 media_image7.png Greyscale PNG media_image8.png 615 559 media_image8.png Greyscale PNG media_image9.png 602 548 media_image9.png Greyscale PNG media_image10.png 615 565 media_image10.png Greyscale PNG media_image11.png 631 538 media_image11.png Greyscale Regarding claim 32, Wang teaches wherein the first recess exposes a bottom surface of one of the semiconductor layers (e.g. bottom surface of top layer 142, Fig. 7) . Regarding claim 33, Wang teaches wherein the first recess exposes a top surface of one of the semiconductor layers (e.g. top surface of middle layer 142, Fig. 7) . Regarding claim 34, Wang teaches wherein the inner spacer comprises a second recess (e.g. part of recess formed in 195, Fig. 6 along the top surface of the middle 142, Fig. 7) , wherein the first recess and the second recess are on a top side and a bottom side of the inner spacer, respectively (Fig. 7) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (US 2021/0028297, hereinafter “Yao”) as applied to claim 16 above, and further in view of Saly et al. (US 2020/0234950, hereinafter, “Saly”) . Regarding claim 17 (16), teaching of Yao was discussed above in the rejection of claim 16, and includes wherein protective layer is formed selectively on outer sidewalls of the inner spacers. Yao, however, does not explicitly teach that the selectively forming the protective layers on the outer sidewalls of the inner spacers comprises performing a surface passivation treatment to passivate exposed surfaces of the semiconductor channel layers, while leaving exposed surfaces of the inner spacers non-passivated, and performing a deposition process to depositing a material of the protective layers on the exposed surfaces of the inner spacers, while leaving the exposed surfaces of the semiconductor channel layers substantially free of coverage by the material of the protective layers. Saly, in a similar field of endeavor, teaches performing a surface passivation treatment (¶¶[0024]-[0030]) to passivate exposed surface of a semiconductor layer (20, Fig. 1 and ¶[0021], i.e. layer 20 is made from the same material as the semiconductor channel layer disclosed by the applicant) , while leaving exposed surface of a material of inner spacers (30, Fig. 1 and ¶[0022], i.e. layer 30 is made of the same material as the inner spacer layer disclosed by the applicant) non-passivated (Fig. 1) , and performing a deposition process to deposit a material (40, Fig. 1 and ¶[0030]) on the exposed surface of spacer material, while leaving the exposed surfaces of the semiconductor layer substantially free of coverage by the material, in order to allow for more selective deposition of the material on the substrate. Thus, since the prior art teaches all of the claim method steps, using such steps would lead to predictable results and, as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform a surface passivation treatment to passivate exposed surfaces of the semiconductor channel layer, disclosed by Yao, while leaving exposed surfaces of the inner spacer non-passivated, and performing a deposition process to deposit material of the protective layers on the exposed surfaces of the inner spacers, while leaving the exposed surfaces of the semiconductor channel layers substantially free of coverages by the material of the protective layers, as disclosed by Saly, in order to allow for selective deposition of the protective layer on the inner spacer layer. Regarding claim 18 (17), the combined teaching of Yao and Saly further discloses wherein performing the surface passivation treatment further comprises forming inhibitors (Saly, Fig. 1 and ¶¶[0023]-[0030]) on the exposed surfaces of the semiconductor channel layers, and the method further comprises: performing an etching process to remove the inhibitors after the deposition process is complete (Saly, ¶[0031]) . 07-21-aia AIA Claim (s) 21-23 and 25-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (US 2021/0028297, hereinafter “Yao”) in view of Saly et al. (US 2020/0234950, hereinafter, “Saly”) . Regarding claim 21, Yao teaches in Figs. 1 through 13 (Figs. 1B, 7 and 13B shown above) a method, comprising: forming semiconductor channel layers (e.g. Si, 107, Fig. 1B and ¶[0037]) over a substrate (101, Fig. 1B and ¶[0037]) ; forming inner spacers (e.g. SiO, 113’, Fig. 6 and ¶[0049],) between adjacent two of the semiconductor channel layers (107, Fig. 6) ; forming protective layers on surfaces of the inner spacers (115, Fig. 7 and ¶[0051]); forming a source/drain epitaxial structure (120, Fig. 9B and ¶[0053]) alongside the semiconductor channel layers; and forming a gate structure (130, Fig. 13B and ¶[0059]) over the semiconductor channel layers. Yao, however, does not explicitly teach that a surface passivation treatment is performed on surfaces of the semiconductor channel layers, and as a result, that the protective layers have higher deposition rate on the surfaces of the inner spacers than on the surfaces of the semiconductor channel layers. Saly, in a similar field of endeavor, teaches that a deposition rate of a material (40, Fig. 1 and ¶[0030]) on a surface of a first material (30, Fig. 1 and ¶[0022], which is made of the same material as the inner spacer layer disclosed by the applicant) can be higher than disposition rate on a second material (20, Fig. 1 and ¶[0021], which is made from the same material as the semiconductor channel layer disclosed by the applicant) by performing passivation treatment on the surface of the second material (20, Fig. 1 and ¶[0021]) . Thus, since the prior art teaches all of the claim method steps, using such steps would lead to predictable results and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform surface passivation treatment on the surface of the semiconductor channel layer, in the method disclosed by Yao, so that the protective layers have higher deposition rate on the surfaces of the inner spacers than on the surfaces of the semiconductor channel layers, as disclosed by Saly, in order to allow for selective deposition of the protective layer on the inner spacer layer. Regarding claim 22 (21), the combined teaching of Yao and Saly discloses wherein performing the surface passivation treatment comprises forming inhibitors on the surfaces of the semiconductor channel layers (Saly, Fig. 1 and ¶¶[0023]-[0030]) . Regarding claim 23 (22), the combined teaching of Yao and Saly further discloses: performing an etching process to remove the inhibitors after the protective layers are formed (Saly, ¶[0031]) . Regarding claim 25 (21), the combined teaching of Yao and Saly discloses wherein the protective layers comprise dielectric material (Yao, 115, Fig. 7 and ¶[0051]) . Regarding claim 26 (25), the combined teaching of Yao and Saly discloses wherein the dielectric material is different from a material of the inner spacer (Yao, ¶¶[0049] and [0051]) . Regarding claim 27 (21), the combined teaching of Yao and Saly discloses wherein the source/drain epitaxial structure (Yao, 120, Fig. 9B) interfaces with the protective layers (Yao, 115, Fig. 9B) . Regarding claim 28 (21), the combined teaching of Yao and Saly discloses wherein the source/drain epitaxial structure (Yao, 120, Fig. 9B) is spaced apart from the inner spacers (Yao, 113’, Fig. 9B) through the protective layers (Yao, 115, Fig. 9B) . Regarding claim 29 (21), the combined teaching of Yao and Saly further discloses forming a dummy gate structure (Yao, 110, Fig. 2B and ¶[0044]) over the semiconductor channel layers (Yao, 105, 107, Fig. 2B) ; forming a gate spacer (Yao, 111, Fig. 2B and ¶[0045]) alongside the dummy gate structure, wherein the protective layers (Yao, 115, Fig. 7) are also formed on the gate spacer (Yao, 111, Fig. 7 and ¶[0051]) ; and removing the dummy gate structure (Yao, 110, Fig. 10 and ¶[0056]) to form a gate trench (Yao, 125, Fig. 10 and ¶[0056]) , wherein the gate structure (Yao, 130, Fig. 13B and ¶[0059]) is formed in the gate trench (Yao, Fig. 13B) . 07-21-aia AIA Claim (s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yao and Saly as applied to claim 29 above . Regarding claim 30 (29), the combined teaching of Yao and Saly was discussed above in the rejection of claim 29. Yao and Saly, however, do not explicitly teach that a portion of the protective layers is removed from the gate spacer after forming the source/drain epitaxial structure. Nonetheless, removing the protective layers from the gate spacers after forming source/drain epitaxial structure would have been obvious to one of ordinary skill in the art in order to protect the gate spacers from damage during formation of the source/drain epitaxial structure. Accordingly, it would have been obvious to one of ordinary skill in the art to remove protective layers from the gate spacers after forming source/drain epitaxial structures in the method disclosed by Yao and Saly, in order to protect the gate spacers during formation of source/drain epitaxial structure . 07-21-aia AIA Claim (s) 19 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yao and Saly as applied to claims 18 and 22 above, respectively, and further in view of Tsubota et al. (US 2023/0097581, hereinafter “Tsubota”) or Soethoudt et al. (cited on IDS) . Regarding claim 19 (18) , the combined teaching of Yao and Saly was discussed above in the rejection of claim 18. While Yao and Saly teach performing passivation treatment comprising forming inhibitors on the surface of the semiconductor channel layer, Yao and Saly do not explicitly teach that the inhibitors comprise -Si(CH 3 ) 3 groups. Tsubota, in a similar filed of endeavor, teaches using inhibitors that comprise -Si(CH 3 ) 3 groups (¶[0079]) to enable selective formation of the subsequently grown film on the substrate. This is similar to the teaching of Soethoudt, that also discloses using inhibitors that comprise -Si(CH 3 ) 3 groups to promote selective growth of subsequently formed materials. Accordingly, since the prior art teaches all of the claimed method steps using such steps would lead to predictable results and as such it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the inhibitors that comprise -Si(CH 3 ) 3 groups as disclosed by Tsubota or Soethoudt, in the method disclosed by Yao and Saly, as doing so would amount to nothing more than using a known inhibitor to perform a selective film growth on the substrate. Regarding claim 24 (22) , the combined teaching of Yao and Saly was discussed above in the rejection of claim 22. While Yao and Saly teach performing passivation treatment comprising forming inhibitors on the surface of the semiconductor channel layer, Yao and Saly do not explicitly teach that the inhibitors comprise -Si(CH 3 ) 3 groups. Tsubota, in a similar filed of endeavor, teaches using inhibitors that comprise -Si(CH 3 ) 3 groups (¶[0079]) to enable selective formation of the subsequently grown film on the substrate. This is similar to the teaching of Soethoudt, that also discloses using inhibitors that comprise -Si(CH 3 ) 3 groups to promote selective growth of subsequently formed materials. Accordingly, since the prior art teaches all of the claimed method steps using such steps would lead to predictable results and as such it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the inhibitors that comprise -Si(CH 3 ) 3 groups as disclosed by Tsubota or Soethoudt, in the method disclosed by Yao and Saly, as doing so would amount to nothing more than using a known inhibitor to perform a selective film growth on the substrate. Relevant Prior Art The following prior art is relevant to the invention but not relied upon in any of the rejections: Wang et al (US 2021/0376119) teaches in Figs. 1-3 and 10-25 and related text a method, comprising, forming semiconductor channel layers (20, 25, Fig. 10A and ¶[0030]) over a substrate (10, Fig. 10A and ¶[0029]), depositing an inner spacer material (33, Fig. 15A and ¶[0019]) filling a gap (e.g. 22, Fig. 12A and ¶[0046]) between adjacent two of the semiconductor channel layers (Fig. 15A), performing an etching (120, Fig. 3A and Fig. 16A and ¶[0051]) process to remove a portion of the inner spacer material outside the gap (Figs. 16A and 2I), leaving a remaining portion of the inner spacer material in the gap as an inner spacer, wherein the inner spacer comprises a first recess (Fig. 2I), forming a protective layer (122, Fig. 3B, 35, Figs. 17A, 2I and ¶[0052]) along a surface of the inner spacer and filling the first recess of the inner spacer (Fig. 2I), forming a source/drain epitaxial structure (130, Fig. 3B, 50, Fig. 19A and ¶[0054]) alongside the semiconductor channel layers, and forming a gate structure (138, Fig. 3B, 84, Fig. 24A and ¶[0060]) over the semiconductor channel layers (Fig. 25). Chen et al. (US 2025/0081549) teaches in Figs. 1-17 and related text a method that includes forming semiconductor channel layers over a substrate, depositing an inner spacer material filling a gap between adjacent two of the semiconductor channel layers; performing an etching process to remove a portion of the inner spacer material outside the gap, leaving a remaining portion of the inner spacer material in the gap as an inner spacer, wherein the inner spacer comprises a first recess; forming a protective layer along a surface of the inner spacer and filling the first recess of the inner spacer; forming a source/drain epitaxial structure alongside the semiconductor channel layers; and forming a gate structure over the semiconductor channel layers. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.B.C/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893 Application/Control Number: 18/466,565 Page 2 Art Unit: 2893 Application/Control Number: 18/466,565 Page 3 Art Unit: 2893 Application/Control Number: 18/466,565 Page 4 Art Unit: 2893 Application/Control Number: 18/466,565 Page 5 Art Unit: 2893 Application/Control Number: 18/466,565 Page 6 Art Unit: 2893 Application/Control Number: 18/466,565 Page 7 Art Unit: 2893 Application/Control Number: 18/466,565 Page 8 Art Unit: 2893 Application/Control Number: 18/466,565 Page 9 Art Unit: 2893 Application/Control Number: 18/466,565 Page 10 Art Unit: 2893 Application/Control Number: 18/466,565 Page 11 Art Unit: 2893 Application/Control Number: 18/466,565 Page 12 Art Unit: 2893 Application/Control Number: 18/466,565 Page 13 Art Unit: 2893 Application/Control Number: 18/466,565 Page 15 Art Unit: 2893 Application/Control Number: 18/466,565 Page 16 Art Unit: 2893 Application/Control Number: 18/466,565 Page 17 Art Unit: 2893 Application/Control Number: 18/466,565 Page 18 Art Unit: 2893