DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed May 18, 2026 has been entered. Cancellation of claim 24 has rendered moot the objection to claim 24 set forth in the prior office action.
Claims 1-23 and 25 remain pending in the application.
Response to Arguments
Applicant’s arguments, see pages 10-11 of Remarks, filed May 18, 2026, with respect to the rejection(s) of claim(s) 1-8, 12-14, and 17-23 under 35 USC § 103 have been fully considered in view of the Amendment and are persuasive. Therefore, the rejections have been withdrawn. However, and although allowable subject matter was indicated in the prior office action, upon updated search, a new ground(s) of rejection is made in view of newly identified additional prior art. Please see the claim rejections below.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY APPARATUS HAVING FIRST AND SECOND DATA LINE PORTIONS SEPARATED FROM ONE ANOTHER AND CONNECTED BY A THIRD PORTION AND A SHIELD ELECTRODE OVERLAPPING THE THIRD PORTION
Claim Objections
Claim 17 objected to because of the following informalities: the claim recites:
“a first conductive pattern layer extend in a first direction,
a second conductive pattern layer extend in the first direction”
which should be
“a first conductive pattern layer extending in a first direction,
a second conductive pattern layer extending in the first direction”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 15-16 and 25 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15, in is unclear whether “a shield electrode” is different from the first shield electrode of claim 1, and must additionally at least partially overlap the first connection pattern layer, and be disposed on a same layer with the first shield electrode, the first conductive pattern layer, and the second conductive pattern layer. In view of the Amendment, “a shield electrode” is believed to be to be the same as “the first shield electrode”, and the claim will be interpreted as “The display apparatus of claim 1, wherein the first shield electrode transmits a voltage”.
Regarding claim 16, note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim 25 is dependent from claim 24, which has been canceled, and recites the limitation "a conductive line that transmits the voltage" in line one of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi; Jae Won et al. (US 2016/0125789; hereinafter Choi) in view of Yao; Lei et al. (US 2021/0333608; hereinafter Yao).
Regarding claim 1, Choi discloses a display apparatus comprising:
a first display element (green subpixel 22SUB-G; Figs 6-7; ¶ [0038-48]) comprising a first pixel electrode (green anode AG; Figs 6-7; ¶ [0038-48), the first display element that emits light of a first color (green; ¶ [0023]) and
a conductive pattern layer (red data line DR; Figs 6-7; ¶ [0038-48]) extending in a first direction (vertical direction, as shown in Fig 6) and overlapping the first pixel electrode of the first display element (Figs 6-7; ¶ [0046]).
Choi does not disclose the conductive pattern layer comprises:
a first conductive pattern layer and a second conductive pattern layer extending in a first direction and spaced apart from each other;
a first connection pattern layer extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, the first connection pattern layer at least partially overlapping the first pixel electrode of the first display element; and
a first shield electrode at least partially overlapping the first connection pattern layer,
wherein the first conductive pattern layer, the first shield electrode, and the second conductive pattern layer are disposed on a same layer between the first display element and the first connection pattern layer.
In the same field of endeavor, Yao discloses an array substrate and display device, comprising:
a first conductive pattern layer (first gate line sub-segment 611; Figs 2C,2A; ¶ [0051-67]) and a second conductive pattern layer (second gate line sub-segment 612; Figs 2C,2A; ¶ [0051-67]) extending in a first direction (left to right across the page; Figs 2C,2A) and spaced apart from each other;
a first connection pattern layer (2; Figs 2C,2A,2B; ¶ [0053-67]) extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, the first connection pattern layer overlapping a data line (81; Figs 2C,2A; ¶ [0050-63]); and
a first shield electrode (613; Figs 2C,2B,2A; ¶ [0056-63]) at least partially overlapping the first connection pattern layer,
wherein the first conductive pattern layer, the first shield electrode, and the second conductive pattern layer are disposed on a same layer between the data line and the first connection pattern layer.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the structure of Yao, directed towards reducing a parasitic capacitance between a gate line and a data line (Yao; ¶ [0053]), with the display apparatus of Choi, such that the first connection pattern layer of Yao overlaps the first pixel electrode of Choi, and the first conductive pattern layer, the first shield electrode, and the second conductive pattern layer are disposed on a same layer between the first pixel electrode and the first connection pattern layer.
One would have been motivated to do this in order to reduce a parasitic capacitance between the red data line and the green anode of Choi (Choi; ¶ [0046]), and improve a display quality of the display apparatus, since Yao has indicated that the structure is formed for the purpose of reducing a parasitic capacitance between two lines by increasing a distance between them (Yao; ¶ [0047,0053]), and Choi has disclosed the need to reduce coupling capacitance to minimize color inaccuracies and improve display performance (¶ [0005]), but acknowledges that the overlap between the red data line and green anode of Figs 6-7 may still give rise to a small amount of capacitive coupling (¶ [0046]). One may be motivated to further reduce and minimize this capacitance, and increase performance, and would have had a reasonable expectation of success because of the similar endeavors of Choi and Yao and because such capacitance reduction methods are well known in the art.
Regarding claim 2, Choi in view of Yao discloses the display apparatus of claim 1, further comprising:
a first data line (Choi; {D},DR; Figs {2-3}, 6-7; ¶ [0027-39]) that transmits a first data voltage (distributes data signals), the first data line comprising the first conductive pattern layer, the second conductive pattern layer, and the first connection pattern layer (as explained for claim 1); and
a first pixel circuit (Choi; 22SUB; Fig 3; ¶ [0027-39]) electrically connected to the first data line, the first pixel circuit that receives the first data voltage through the first data line and drives the first display element (Choi; ¶ [0029-30]).
Regarding claim 14, Choi in view of Yao discloses the display apparatus of claim 1, but does not specifically disclose in a plan view, the first conductive pattern layer and the second conductive pattern layer are spaced apart from the first pixel electrode of the first display element (Choi; AG; Figs 6-7). However, this would have been obvious to a person having ordinary skill in the art: As applied to claim 1, the first conductive pattern and the second conductive pattern take the place of DR in Fig 6 of Choi except for a portion including a gap between the first and second conductive patterns and overlapping AG and the first connection pattern. It would have been obvious in combining the structure of Yao with Choi in order to reduce the parasitic coupling capacitance between the red data line DR and the green anode AG for the gap to comprise being spaced apart from the first pixel electrode (for example, spaced in the first direction) in order to ensure a sufficiently increased distance and corresponding reduced capacitance in a non-orthogonal direction from the first direction; that is, the gap should be larger than a dimension of the anode to satisfy the intended purpose).
Claims 1-8, 12-13, and 17-23 are rejected under 35 U.S.C. 103 as being unpatentable over Park; Jun Hyun et al. (US 2022/0102463; hereinafter Park) in view of Yao; Lei et al. (US 2021/0333608; hereinafter Yao).
Regarding claim 1, Park discloses a display apparatus comprising:
a first display element (green pixel G; Fig 3; ¶ [0051-52]) comprising a first pixel electrode (green pixel anode AEG; Fig 3; ¶ [0058-59), the first display element that emits light of a first color (green; ¶ [0051]) and
a conductive pattern layer (data line 171R; Fig 3; ¶ [0057]) extending in a first direction (vertical direction, as shown in Fig 3) and overlapping the first pixel electrode of the first display element (as shown in Fig 3, 171R overlaps along the left side of G).
Park does not disclose the conductive pattern layer comprises:
a first conductive pattern layer and a second conductive pattern layer extending in a first direction and spaced apart from each other; and
a first connection pattern layer extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, the first connection pattern layer at least partially overlapping the first pixel electrode of the first display element; and
a first shield electrode at least partially overlapping the first connection pattern layer,
wherein the first conductive pattern layer, the first shield electrode, and the second conductive pattern layer are disposed on a same layer between the first display element and the first connection pattern layer.
In the same field of endeavor, Yao discloses an array substrate and display device, comprising:
a first conductive pattern layer (first gate line sub-segment 611; Figs 2C,2A; ¶ [0051-67]) and a second conductive pattern layer (second gate line sub-segment 612; Figs 2C,2A; ¶ [0051-67]) extending in a first direction (left to right across the page; Figs 2C,2A) and spaced apart from each other;
a first connection pattern layer (2; Figs 2C,2A,2B; ¶ [0053-67]) extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, the first connection pattern layer overlapping a data line (81; Figs 2C,2A; ¶ [0050-63]); and
a first shield electrode (613; Figs 2C,2B,2A; ¶ [0056-63]) at least partially overlapping the first connection pattern layer,
wherein the first conductive pattern layer, the first shield electrode, and the second conductive pattern layer are disposed on a same layer between the data line and the first connection pattern layer.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the structure of Yao, directed towards reducing a parasitic capacitance between a gate line and a data line (Yao; ¶ [0053]), with the display apparatus of Park such that the first connection pattern layer of Yao overlaps the first pixel electrode of Park, and the first conductive pattern layer, the first shield electrode, and the second conductive pattern layer are disposed on a same layer between the first pixel electrode and the first connection pattern layer.
One would have been motivated to do this as an alternate or additional method to a reduce parasitic capacitance between the data line and the green pixel anode of Park, since Park has identified a potential need (Park; ¶ [0027,0067-69]) in order to enable high speed driving, and Yao has indicated that his disclosed structure is formed for the similar purpose of reducing a parasitic capacitance between two lines by increasing a distance between them (Yao; ¶ [0047,0053]). Such alternate method may enable one to otherwise maintain a dimension and configuration of at least the green pixel anode, and may be a preferable method for this or other design, manufacturing, and performance considerations. One would have had a reasonable expectation of success with the combination because of the similar endeavors of Park and Yao and because such capacitance reduction methods are well known in the art.
Regarding claim 2, Park in view of Yao discloses the display apparatus of claim 1, further comprising:
a first data line (Park; data line 171R {171}; Figs 3,{6}; ¶ [0057]) that transmits a first data voltage (Park; ¶ [0053, 0098-106), the first data line comprising the first conductive pattern layer, the second conductive pattern layer, and the first connection pattern layer (as explained for claim 1); and
a first pixel circuit (Park; PXG; Figs 3 {6}; ¶ [0053-54,0095-114]) electrically connected to the first data line, the first pixel circuit that receives the first data voltage through the first data line and drives the first display element (Park; ¶ [0053-54,0095-114]).
Regarding claim 3, Park in view of Yao discloses the display apparatus of claim 2, wherein
the first display element (Park; G; Fig 3) comprises a first emission area (Park; corresponding approximately to AEG and the emission layer LEL; Figs 3,11; ¶ [0058,0195]) that emits light of the first color (green), and
in a plan view, the first pixel circuit (Park; PXG; Fig 3) and the first emission area (Park; AEG; Fig 3) of the first display element are spaced apart from each other (as shown in Fig 3; ¶ [0056,0059-60]).
Regarding claim 4, Park in view of Yao discloses the display apparatus of claim 3, further comprising:
a second display element (Park; blue pixel B; Fig 3; ¶ [0051-52]) comprising a second emission area (Park; corresponding approximately to AEB and the emission layer LEL; Figs 3,11; ¶ [0058,0195]) and a second pixel electrode (Park; blue pixel anode AEB; Fig 3; ¶ [0058-59), the second emission area that emits light of a second color (Park; blue; ¶ [0051]) different from the first color (green);
a second data line (Park; data line 171B {171}; Figs 3,{6}; ¶ [0057]) that transmits a second data voltage (Park; ¶ [0053, 0098-106); and
a second pixel circuit (Park; PXB; Figs 3 {6}; ¶ [0053-54,0095-114]) electrically connected to the second data line, the second pixel circuit that receives the second data voltage and drives the second display element (Park; ¶ [0053-54,0095-114]), wherein
in a plan view, the second pixel circuit and the second emission area of the second display element at least partially overlap each other (Park; as shown in Fig 3; ¶ [0056,0059-60]).
Park in view of Yao as applied to claim 1 does not disclose,
the second data line comprising:
a third conductive pattern layer extending in the first direction,
a fourth conductive pattern layer extending in the first direction and being spaced apart from the third conductive pattern layer, and
a second connection pattern layer extending in the first direction, the second connection pattern layer electrically connecting the third conductive pattern layer to the fourth conductive pattern layer and at least partially overlapping the second pixel electrode of the second display element, wherein,
the third conductive pattern layer and the fourth conductive pattern layer are disposed on a same layer between the second display element and the second connection pattern layer.
However, it would have been obvious to a person having ordinary skill in the art to have combined the structure of Yao with the second data line according to the additional limitations above of claim 4, in the same manner as was done for the first data line as explained under claim 1. One may have been motivated to do this, in order to reduce a capacitance between a connecting portion AEB3 of the blue pixel anode which overlaps with the second data line 171B (Park; Fig 3; ¶ [0077]) by increasing a distance therebetween, and thereby further reduce a capacitance between the whole of the blue pixel anode AEB and the second data line 171B. One would have had a reasonable expectation of success with the combination because such jumper wire configurations for routing lines between different layers are well known in the art.
Regarding claim 5, Park in view of Yao discloses the display apparatus of claim 4, wherein
the second pixel electrode (Park; AEB; Fig 3) of the second display element comprises a first electrode portion (Park; AEB1; Fig 3), a second electrode portion (Park; AEB2; Fig 3), and a third electrode portion (Park; AEB3; Fig 3),
the first electrode portion and the second electrode portion extend in the first direction and spaced apart from each other with the second data line (Park; 171B; Fig 3) between the first electrode portion and the second electrode portion (Park; as shown in Fig 3; ¶ [0077]), and
the third electrode portion electrically connects the first electrode portion to the second electrode portion and at least partially overlaps the second connection pattern layer (Park; as shown in Fig 3; ¶ [0077]).
Regarding claim 6, Park in view of Yao discloses the display apparatus of claim 5, wherein
the second emission area of the second display element comprises:
a first light-emitting portion (Park; LEL over AEB1; Figs 3,11; ¶ [0058,0915]) overlapping the first electrode portion in a plan view, and
a second light-emitting portion (Park; LEL over AEB2; Figs 3,11; ¶ [0058,0915]) overlapping the second electrode portion in a plan view,
the first light-emitting portion overlaps the first pixel circuit (Park; PXG, as shown in Fig 3) in a plan view, and
the second light-emitting portion overlaps the second pixel circuit (Park; PXB, as shown in Fig 3) in a plan view.
Regarding claim 7, Park in view of Yao discloses the display apparatus of claim 5, wherein the third electrode portion (Park; AEB3; Fig 3) electrically connects an end portion of the first electrode portion (Park; AEB1; Fig 3) to an end portion of the second electrode portion (Park; AEB2; Fig 3; upper end, as shown in Fig 3; ¶ [0078]).
Regarding claim 8, Park in view of Yao discloses the display apparatus of claim 5, but does not disclose wherein the third electrode portion (Park; AEB3; Fig 3) electrically connects a central portion of the first electrode portion to a central portion of the second electrode portion. However, this would have been obvious to a person having ordinary skill in the art. Park discloses that the anode connection AEB3 may be positioned at an upper side, a lower side, or at both an upper side and a lower side (an opening therebetween) of AEB1 and AEB2 (Park; ¶ [0078]). It is clear from the description that these are exemplary configurations and the idea is to minimize an overlap area between AEB3 and the data line 171B in order to minimize a capacitance between AEB and 171B. It would have been obvious that various positions and configurations of AEB3 may produce a same capacitance and therefore the position may be alternately chosen in accordance with other design, manufacturing or performance considerations.
Regarding claim 9, Park in view of Yao discloses the display apparatus of claim 4, but does not disclose further comprising: a second shield electrode at least partially overlapping the second connection pattern layer, wherein the second shield electrode, the third conductive pattern layer, and the fourth conductive pattern layer are disposed on a same layer; however, it would have been obvious to have included the second shield electrode configured according to claim 9, in the same manner as was done for with the first shield electrode as explained under claim 1.
Regarding claim 12, Park in view of Yao discloses the display apparatus of claim 2, wherein the first pixel circuit comprises:
a first transistor (Park; T1; Fig 6; ¶ [0104]) that controls a magnitude of a driving current flowing through the first display element;
a second transistor (Park; T2; Fig 6; ¶ [0104]) that transmits the first data voltage (VDATA; Fig 6) to the first transistor in response to a first scan signal (Park; GW(n); Figs 6-7; ¶ [0105]) and
a third transistor (Park; T7; Fig 6; ¶ [0110]) that transmits an initialization voltage to the first pixel electrode of the first display element in response to a second scan signal (Park; EB1(n); Figs 6-7; ¶ [0134]),
wherein a frequency of the first scan signal is different from a frequency of the second scan signal (Park; Fig 7 is a waveform diagram representing different scan signals that may be applied to the pixel circuit of Fig 6 over the same time period (x-axis; ¶ [0115-118,0119-135]), and one can observe that the second scan signal EB1(n) has twice as many y-deflections as does the first scan signal GW(n), indicating a frequency twice as high.
Regarding claim 13, Park in view of Yao discloses the display apparatus of claim 12, wherein the frequency of the second scan signal is higher than the frequency of the first scan signal (as explained for claim 12).
Regarding claim 17, Park discloses a display apparatus comprising:
a data line (171B {171}; Figs 3,{6}; ¶ [0057]); and,
a pixel electrode (blue pixel anode AEB; Fig 3; ¶ [0058-59) comprising:
a first electrode portion (AEB1; Fig 3) and a second electrode portion (AEB2; Fig 3) spaced apart from each other with the data line between the first electrode portion and the second electrode portion, and
a third electrode portion (AEB3; Fig 3) electrically connecting the first electrode portion to the second electrode portion (Park; as shown in Fig 3; ¶ [0077]).
Park does not disclose, the data line comprising:
a first conductive pattern layer extending in a first direction,
a second conductive pattern layer extending in the first direction and spaced apart from the first conductive pattern layer, and
a connection pattern layer extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer;
the third electrode portion at least partially overlapping the connection pattern layer; and
a shield electrode at least partially overlapping the connection pattern layer,
wherein the first conductive pattern layer, the shield electrode, and the second conductive pattern layer are disposed on a same layer between the pixel electrode and the connection pattern layer.
In the same field of endeavor, Yao discloses an array substrate and display device, comprising:
a first conductive pattern layer (first gate line sub-segment 611; Figs 2C,2A; ¶ [0051-67]) extending in a first direction (left to right across the page; Figs 2C,2A),
a second conductive pattern layer (second gate line sub-segment 612; Figs 2C,2A; ¶ [0051-67]) extending in the first direction and spaced apart from the first conductive pattern layer, and
a connection pattern layer (2; Figs 2C,2A,2B; ¶ [0053-67]) extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, a data line (81; Figs 2C,2A; ¶ [0050-63]) overlapping the connection pattern layer; and
a shield electrode (613; Figs 2C,2B,2A; ¶ [0056-63]) at least partially overlapping the first connection pattern layer,
wherein the first conductive pattern layer, the first shield electrode, and the second conductive pattern layer are disposed on a same layer between the data line and the connection pattern layer.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the structure of Yao, directed towards reducing a parasitic capacitance between a gate line and a data line (Yao; ¶ [0053]), with the display apparatus of Park such that the connection pattern layer of Yao overlaps the third electrode portion of Park, and the first conductive pattern layer, the first shield electrode, and the second conductive pattern layer are disposed on a same layer between the pixel electrode and the connection pattern layer.
One would have been motivated to do this in order to reduce a capacitance between a connecting portion AEB3 of the blue pixel anode which overlaps with the second data line 171B (Park; Fig 3; ¶ [0077]), since Park has identified the need for reduced capacitance (Park; ¶ [0027,0067-69]) in order to enable high speed driving, and Yao has indicated that his disclosed structure is formed for the similar purpose of reducing a parasitic capacitance between two lines by increasing a distance between them (Yao; ¶ [0047,0053]). Reducing the capacitance between AEB3 and 171B would further reduce a capacitance between the whole of the blue pixel anode AEB and the second data line 171B. One would have had a reasonable expectation of success with the combination because of the similar endeavors of Park and Yao and because such capacitance reduction methods are well known in the art.
Regarding claim 18, Park in view of Yao discloses the display apparatus of claim 17, further comprising:
a display element (Park; blue pixel B; Fig 3; ¶ [0051-52,0058-59]) comprising the pixel electrode (Park; AEB; Fig 3); and
a pixel circuit (Park; PXB; Figs 3 {6}; ¶ [0053-54,0095-114]) that drives the display element, wherein
the pixel circuit comprises:
a first transistor (Park; T1; Fig 6; ¶ [0104]) that controls a magnitude of a driving current flowing through the display element;
a second transistor (Park; T2; Fig 6; ¶ [0104]) that electrically connects the data line (171; Fig 6) to the first transistor in response to a first scan signal (Park; GW(n); Figs 6-7; ¶ [0105]) and
a third transistor (Park; T7; Fig 6; ¶ [0110]) that transmits an initialization voltage (VINIT; Fig 6) to the first pixel electrode of the first display element in response to a second scan signal (Park; EB1; Figs 6-7; ¶ [0134]), and
a frequency of the first scan signal is different from a frequency of the second scan signal (Park; Fig 7 is a waveform diagram representing different scan signals that may be applied to the pixel circuit of Fig 6 over the same time period (x-axis; ¶ [0115-118,0119-135]), and one can observe that the second scan signal EB1(n) has twice as many y-deflections as does the first scan signal GW(n), indicating a frequency twice as high.
Regarding claim 19, Park in view of Yao discloses the display apparatus of claim 18, wherein the frequency of the second scan signal is higher than the frequency of the first scan signal (as explained for claim 18).
Regarding claim 20, Park in view of Yao discloses the display apparatus of claim 18, wherein, in a plan view, the pixel circuit (Park; PXB; Figs 3) at least partially overlaps the first electrode portion (AEB1; Fig 3) or the second electrode portion (AEB2; as shown in Fig 3).
Regarding claim 21, Park in view of Yao discloses the display apparatus of claim 17, wherein the third electrode portion (Park; AEB3; Fig 3) electrically connects an end portion of the first electrode portion (Park; AEB1; Fig 3) to an end portion of the second electrode portion (Park; AEB2; Fig 3; upper end, as shown in Fig 3; ¶ [0078]).
Regarding claim 22, Park in view of Yao discloses the display apparatus of claim 17, but does not disclose wherein the third electrode portion (Park; AEB3; Fig 3) electrically connects a central portion of the first electrode portion to a central portion of the second electrode portion. However, this would have been obvious to a person having ordinary skill in the art. Park discloses that the anode connection AEB3 may be positioned at an upper side, a lower side, or at both an upper side and a lower side (an opening therebetween) of AEB1 and AEB2 (Park; ¶ [0078]). It is clear from the description that these are exemplary configurations and the idea is to minimize an overlap area between AEB3 and the data line 171B in order to minimize a capacitance between AEB and 171B. It would have been obvious that various positions and configurations of AEB3 may produce a same capacitance and therefore the position may be alternately chosen in accordance with other design, manufacturing or performance considerations.
Regarding claim 23, Park in view of Yao discloses the display apparatus of claim 17, but does not specifically disclose in a plan view, the first conductive pattern layer and the second conductive pattern layer are spaced apart from the pixel electrode (Park; AEB; Fig 3). However, this would have been obvious to a person having ordinary skill in the art: As applied to claim 1, the first conductive pattern and the second conductive pattern take the place of 171B in Fig 3 of Park except for a portion including a gap between the first and second conductive patterns and overlapping AEB3 and the first connection pattern. It would have been obvious in combining the structure of Yao with Park in order to reduce the parasitic coupling capacitance between the data line 171B and the pixel electrode AEB for the gap to comprise being spaced apart from the pixel electrode (for example, spaced in the first direction from AEB3) in order to ensure a sufficiently increased distance and corresponding reduced capacitance in a non-orthogonal direction from the first direction; that is, the gap should be larger than a dimension of the anode to satisfy the intended purpose).
Claims 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Park; Jun Hyun et al. (US 2022/0102463; hereinafter Park) in view of Yao; Lei et al. (US 2021/0333608; hereinafter Yao) and further in view of Shim Woo Sung et al. (KR 2018/0062897; hereinafter Shim).
Regarding claim 10, Park in view of Yao discloses the display apparatus of claim 9, but does not disclose further comprising: a first conductive line that transmits a first voltage, the first conductive line extending in the first direction; and a second conductive line that transmits a second voltage, the second conductive line extending in the first direction, wherein the first shield electrode extends from the first conductive line in a second direction intersecting the first direction, and the second shield electrode extends from the second conductive line in the second direction.
In the same field of endeavor, Shim discloses a display device comprising a first shield electrode (141B; Figs 3,4e; ¶ [0047]) that extends between a pixel electrode (anode (151R); Figs 3,4e; ¶ [0047]) and a data line (DLG), wherein the shield electrode transmits a first voltage (¶ [0047,0064-65]) in order to reduce a parasitic capacitance between the pixel electrode and the data line, the display device of Shim further comprising:
a first conductive line (VDLB; Fig 4e; ¶ [0047]) that transmits the first voltage (¶ [0047,0064-65]), the first conductive line extending in a first direction (vertically; Fig 4e), wherein the first shield electrode extends from the first conductive line in a second direction intersecting the first direction (horizontally; Fig 4e).
It would have been obvious to a person having ordinary skill in the art to have combined the structure of Shim with the display apparatus of Park in view of Yao to apply a voltage to the shield layer (Yao; 613; Fig 2C) by using the structure taught by Shim. One would have been motivated to do this in order to ensure effective shielding, because Shim teaches that for a case where a shield electrode is electrically floating, the pixel electrode may not be effectively shielded to reduce a capacitance between the pixel electrode and the data line (Shim; ¶ [0064]). One would have had a reasonable expectation of success because of the similar method of using an intervening shield electrode to reduce a capacitance disclosed by both Yao and Shim in the similar endeavors, and because routing of various gate lines, data lines, shield lines and other wiring lines and connections is well-known and routine in the art to accommodate a variety of required performance and manufacturing requirements (that is, it is within the capability of a person of ordinary skill in the art to combine the structure of Shim with the display apparatus of Park in view of Yao, to connect the shield layer to a voltage source).
Further, the same reasoning applies to the configuration of a second conductive line and second shield layer, which may be configured in the same manner, satisfying the further limitation of claim 10.
Regarding claim 15, Park in view of Yao discloses the display apparatus of claim 1, but does not disclose “wherein the first shield electrode transmits a voltage”.
In the same field of endeavor, Shim discloses a display device comprising a shield electrode (141B; Figs 3,4e; ¶ [0047]) that extends between a pixel electrode (anode (151R); Figs 3,4e; ¶ [0047]) and a data line (DLG), which transmits a voltage (¶ [0047,0064-65]) in order to reduce a parasitic capacitance between the pixel electrode and the data line.
It would have been obvious to a person having ordinary skill in the art to have combined the teaching of Shim with the display apparatus of Park in view of Yao, as applied to claim 1, to apply a voltage to the shield layer (Yao; 613; Fig 2C). One would have been motivated to do this in order to ensure effective shielding, because Shim teaches that for a case where a shield electrode is electrically floating, the pixel electrode may not be effectively shielded to reduce a capacitance between the pixel electrode and the data line (Shim; ¶ [0064]). One would have had a reasonable expectation of success because of the similar method of using an intervening shield electrode to reduce a capacitance by both Park and Shim in the similar endeavors, and because routing of various gate lines, data lines, shield lines and other wiring lines and connections is well-known and routine in the art to accommodate a variety of required performance and manufacturing requirements.
Allowable Subject Matter
Claims 11 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, in addition to overcoming any 112(b) rejections applied to the claim(s).
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 11, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the first voltage and the second voltage are different from each other”, in combination with all of the limitations of the base claim and any intervening claims.
Regarding claim 16, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the conductive line extending in the first direction, wherein the shield electrode extends from the conductive line in a second direction intersecting the first direction, and the shield electrode and the conductive line are integral with each other”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim; Kyung-Wook et al. (US 2013/0235020; the prior art discloses a configuration wherein a common voltage line is inserted between a pixel electrode and a data line to shield a capacitance therebetween);
Hwang; JaeSik (US 2017/0345877; the prior art discloses a configuration wherein a common voltage line is inserted between an anode and a data line to reduce a capacitance therebetween);
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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