DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 24 objected to because of the following informalities:
Claim 24 recites “wherein the shield electrode, the the first conductive pattern layer”, where the word “the” is duplicated. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi; Jae Won et al. (US 2016/0125789; hereinafter Choi) in view of Gan; Qiming et al. (US 2018/0341159; hereinafter Gan).
Regarding claim 1, Choi discloses a display apparatus comprising:
a first display element (green subpixel 22SUB-G; Figs 6-7; ¶ [0038-48]) comprising a first pixel electrode (green anode AG; Figs 6-7; ¶ [0038-48), the first display element that emits light of a first color (green; ¶ [0023]) and
a conductive pattern layer (red data line DR; Figs 6-7; ¶ [0038-48]) extending in a first direction (vertical direction, as shown in Fig 6) and overlapping the first pixel electrode of the first display element (Figs 6-7; ¶ [0046]).
Choi does not disclose the conductive pattern layer comprises:
a first conductive pattern layer and a second conductive pattern layer extending in a first direction and spaced apart from each other; and
a first connection pattern layer extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, the first connection pattern layer at least partially overlapping the first pixel electrode of the first display element,
wherein the first conductive pattern layer and the second conductive pattern layer are disposed on a same layer between the first display element and the first connection pattern layer.
In the same field of endeavor, Gan discloses a jumper wire (108; Fig 1; ¶ [0057-58]) extending in a first direction (vertical, Fig 1) and electrically connecting first and second portions of a data line (102; Fig 1; ¶ [0057-58]), the first and second portions being separated by a gap and extending in the first direction, the first and second portions being disposed on a same layer and overlapping a scan line (103; Fig 1; ¶ [0057-58]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the capacitance reduction method of Gan with the display apparatus of Choi by substituting the data line and jumper wire of Gan for the red data line of Choi, such that the jumper wire overlaps a portion (Choi; 102; Fig 7; ¶ [0046]) of the green anode AG. One would have been motivated to do this in order to reduce parasitic coupling capacitance between the red data line and the green anode of Choi (Choi; ¶ [0046]), since Gan has indicated the that the jumper wire structure formed on a different layer to increase a distance (thickness) between two lines having capacitance between them as a method for reducing the capacitance. Choi has disclosed the need to reduce coupling capacitance to minimize color inaccuracies and improve display performance (¶ [0005]), but acknowledges that the overlap between the red data line and green anode of Figs 6-7 may still give rise to a small amount of capacitive coupling (¶ [0046]). One may be motivated to further reduce and minimize this capacitance, and increase performance, and would have had a reasonable expectation of success with the combination because such jumper wire configurations are well known in the art.
Regarding the limitation wherein the first conductive pattern layer and the second conductive pattern layer (first and second portions of the data line) are disposed on a same layer (Gan; ¶ [0057-58], as mentioned above) between the first display element (green subpixel) and the first connection pattern layer (jumper wire), this would have been obvious to a person having ordinary skill in the art in order to increase a distance between the green subpixel and the data line and thereby reduce a capacitance therebetween. (In the case of Gan, the capacitance to be reduced is between the data line 102 and a scan line 103 below (Gan; Fig 1), so the jumper is above the data line to increase capacitance; for the case of Choi, the capacitance is between the red data line DR and the green anode AG above, so the jumper should be below the red data line to increase a distance and correspondingly a capacitance therebetween).
Regarding claim 2, Choi in view of Gan discloses the display apparatus of claim 1, further comprising:
a first data line (Choi; {D},DR; Figs {2-3}, 6-7; ¶ [0027-39]) that transmits a first data voltage (distributes data signals), the first data line comprising the first conductive pattern layer, the second conductive pattern layer, and the first connection pattern layer (as explained for claim 1); and
a first pixel circuit (Choi; 22SUB; Fig 3; ¶ [0027-39]) electrically connected to the first data line, the first pixel circuit that receives the first data voltage through the first data line and drives the first display element (Choi; ¶ [0029-30]).
Regarding claim 14, Choi in view of Gan discloses the display apparatus of claim 1, but does not specifically disclose in a plan view, the first conductive pattern layer and the second conductive pattern layer are spaced apart from the first pixel electrode of the first display element (Choi; AG; Figs 6-7). However, this would have been obvious to a person having ordinary skill in the art: As applied to claim 1, the first conductive pattern and the second conductive pattern take the place of DR in Fig 6 of Choi except for a portion including a gap between the first and second conductive patterns and overlapping AG and the first connection pattern. It would have been obvious in combining the structure of Gan with Choi in order to reduce the parasitic coupling capacitance between the red data line DR and the green anode AG for the gap to comprise being spaced apart from the first pixel electrode (for example, spaced in the first direction) in order to ensure a sufficiently increased distance and corresponding reduced capacitance in a non-orthogonal direction from the first direction; that is, the gap should be larger than a dimension of the anode to satisfy the intended purpose).
Claims 1-8, 12-13, and 17-23 are rejected under 35 U.S.C. 103 as being unpatentable over Park; Jun Hyun et al. (US 2022/0102463; hereinafter Park) in view of Gan; Qiming et al. (US 2018/0341159; hereinafter Gan).
Regarding claim 1, Park discloses a display apparatus comprising:
a first display element (green pixel G; Fig 3; ¶ [0051-52]) comprising a first pixel electrode (green pixel anode AEG; Fig 3; ¶ [0058-59), the first display element that emits light of a first color (green; ¶ [0051]) and
a conductive pattern layer (data line 171R; Fig 3; ¶ [0057]) extending in a first direction (vertical direction, as shown in Fig 3) and overlapping the first pixel electrode of the first display element (as shown in Fig 3, 171R overlaps along the left side of G).
Park does not disclose the conductive pattern layer comprises:
a first conductive pattern layer and a second conductive pattern layer extending in a first direction and spaced apart from each other; and
a first connection pattern layer extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer, the first connection pattern layer at least partially overlapping the first pixel electrode of the first display element,
wherein the first conductive pattern layer and the second conductive pattern layer are disposed on a same layer between the first display element and the first connection pattern layer.
In the same field of endeavor, Gan discloses a jumper wire (108; Fig 1; ¶ [0057-58]) extending in a first direction (vertical, Fig 1) and electrically connecting first and second portions of a data line (102; Fig 1; ¶ [0057-58]), the first and second portions being separated by a gap and extending in the first direction, the first and second portions being disposed on a same layer and overlapping a scan line (103; Fig 1; ¶ [0057-58]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the capacitance reduction method of Gan with the display apparatus of Park by substituting the data line and jumper wire of Gan for the data line of Park, such that the jumper wire overlaps a portion of the green pixel anode AEG (at the left side of AEG in Fig 3). One would have been motivated to do this as an alternate method to a reduce parasitic capacitance between the data line and the green pixel anode of Park, since Park has identified a potential need (Park; ¶ [0027,0067-69]) in order to enable high speed driving, and Gan has disclosed the jumper wire structure formed on a different layer in order to increase a distance (thickness) between two lines having capacitance between them as a method for reducing the capacitance. Such alternate method may enable one to otherwise maintain a dimension and configuration of at least the green pixel anode, and may be a preferable method for this or other design, manufacturing, and performance considerations. One would have had a reasonable expectation of success with the combination because such jumper wire configurations for routing lines between different layers are well known in the art.
Regarding the limitation wherein the first conductive pattern layer and the second conductive pattern layer (first and second portions of the data line) are disposed on a same layer (Gan; ¶ [0057-58], as mentioned above) between the first display element (green subpixel) and the first connection pattern layer (jumper wire), this would have been obvious to a person having ordinary skill in the art in order to increase a distance between the green subpixel and the data line and thereby reduce a capacitance therebetween. (In the case of Gan, the capacitance to be reduced is between the data line 102 and a scan line 103 below (Gan; Fig 1), so the jumper is above the data line to increase capacitance; for the case of Park, the capacitance is between the data line 171R and the green pixel anode G above, so the jumper should be below the data line to increase a distance and correspondingly a capacitance therebetween).
Regarding claim 2, Park in view of Gan discloses the display apparatus of claim 1, further comprising:
a first data line (Park; data line 171R {171}; Figs 3,{6}; ¶ [0057]) that transmits a first data voltage (Park; ¶ [0053, 0098-106), the first data line comprising the first conductive pattern layer, the second conductive pattern layer, and the first connection pattern layer (as explained for claim 1); and
a first pixel circuit (Park; PXG; Figs 3 {6}; ¶ [0053-54,0095-114]) electrically connected to the first data line, the first pixel circuit that receives the first data voltage through the first data line and drives the first display element (Park; ¶ [0053-54,0095-114]).
Regarding claim 3, Park in view of Gan discloses the display apparatus of claim 2, wherein
the first display element (Park; G; Fig 3) comprises a first emission area (Park; corresponding approximately to AEG and the emission layer LEL; Figs 3,11; ¶ [0058,0195]) that emits light of the first color (green), and
in a plan view, the first pixel circuit (Park; PXG; Fig 3) and the first emission area (Park; AEG; Fig 3) of the first display element are spaced apart from each other (as shown in Fig 3; ¶ [0056,0059-60]).
Regarding claim 4, Park in view of Gan discloses the display apparatus of claim 3, further comprising:
a second display element (Park; blue pixel B; Fig 3; ¶ [0051-52]) comprising a second emission area (Park; corresponding approximately to AEB and the emission layer LEL; Figs 3,11; ¶ [0058,0195]) and a second pixel electrode (Park; blue pixel anode AEB; Fig 3; ¶ [0058-59), the second emission area that emits light of a second color (Park; blue; ¶ [0051]) different from the first color (green);
a second data line (Park; data line 171B {171}; Figs 3,{6}; ¶ [0057]) that transmits a second data voltage (Park; ¶ [0053, 0098-106); and
a second pixel circuit (Park; PXB; Figs 3 {6}; ¶ [0053-54,0095-114]) electrically connected to the second data line, the second pixel circuit that receives the second data voltage and drives the second display element (Park; ¶ [0053-54,0095-114]), wherein
in a plan view, the second pixel circuit and the second emission area of the second display element at least partially overlap each other (Park; as shown in Fig 3; ¶ [0056,0059-60]).
Park in view of Gan as applied to claim 1 does not disclose,
the second data line comprising:
a third conductive pattern layer extending in the first direction,
a fourth conductive pattern layer extending in the first direction and being spaced apart from the third conductive pattern layer, and
a second connection pattern layer extending in the first direction, the second connection pattern layer electrically connecting the third conductive pattern layer to the fourth conductive pattern layer and at least partially overlapping the second pixel electrode of the second display element, wherein,
the third conductive pattern layer and the fourth conductive pattern layer are disposed on a same layer between the second display element and the second connection pattern layer.
However, it would have been obvious to a person having ordinary skill in the art to have combined the jumper wire structure of Gan with the second data line according to the additional limitations above of claim 4, in the same manner as was done for the first data line as explained under claim 1. One may have been motivated to do this, in order to reduce a capacitance between a connecting portion AEB3 of the blue pixel anode which overlaps with the second data line 171B (Park; Fig 3; ¶ [0077]) by increasing a distance therebetween, and thereby further reduce a capacitance between the whole of the blue pixel anode AEB and the second data line 171B. One would have had a reasonable expectation of success with the combination because such jumper wire configurations for routing lines between different layers are well known in the art.
Regarding claim 5, Park in view of Gan discloses the display apparatus of claim 4, wherein
the second pixel electrode (Park; AEB; Fig 3) of the second display element comprises a first electrode portion (Park; AEB1; Fig 3), a second electrode portion (Park; AEB2; Fig 3), and a third electrode portion (Park; AEB3; Fig 3),
the first electrode portion and the second electrode portion extend in the first direction and spaced apart from each other with the second data line (Park; 171B; Fig 3) between the first electrode portion and the second electrode portion (Park; as shown in Fig 3; ¶ [0077]), and
the third electrode portion electrically connects the first electrode portion to the second electrode portion and at least partially overlaps the second connection pattern layer (Park; as shown in Fig 3; ¶ [0077]).
Regarding claim 6, Park in view of Gan discloses the display apparatus of claim 5, wherein
the second emission area of the second display element comprises:
a first light-emitting portion (Park; LEL over AEB1; Figs 3,11; ¶ [0058,0915]) overlapping the first electrode portion in a plan view, and
a second light-emitting portion (Park; LEL over AEB2; Figs 3,11; ¶ [0058,0915]) overlapping the second electrode portion in a plan view,
the first light-emitting portion overlaps the first pixel circuit (Park; PXG, as shown in Fig 3) in a plan view, and
the second light-emitting portion overlaps the second pixel circuit (Park; PXB, as shown in Fig 3) in a plan view.
Regarding claim 7, Park in view of Gan discloses the display apparatus of claim 5, wherein the third electrode portion (Park; AEB3; Fig 3) electrically connects an end portion of the first electrode portion (Park; AEB1; Fig 3) to an end portion of the second electrode portion (Park; AEB2; Fig 3; upper end, as shown in Fig 3; ¶ [0078]).
Regarding claim 8, Park in view of Gan discloses the display apparatus of claim 5, but does not disclose wherein the third electrode portion (Park; AEB3; Fig 3) electrically connects a central portion of the first electrode portion to a central portion of the second electrode portion. However, this would have been obvious to a person having ordinary skill in the art. Park discloses that the anode connection AEB3 may be positioned at an upper side, a lower side, or at both an upper side and a lower side (an opening therebetween) of AEB1 and AEB2 (Park; ¶ [0078]). It is clear from the description that these are exemplary configurations and the idea is to minimize an overlap area between AEB3 and the data line 171B in order to minimize a capacitance between AEB and 171B. It would have been obvious that various positions and configurations of AEB3 may produce a same capacitance and therefore the position may be alternately chosen in accordance with other design, manufacturing or performance considerations.
Regarding claim 12, Park in view of Gan discloses the display apparatus of claim 2, wherein the first pixel circuit comprises:
a first transistor (Park; T1; Fig 6; ¶ [0104]) that controls a magnitude of a driving current flowing through the first display element;
a second transistor (Park; T2; Fig 6; ¶ [0104]) that transmits the first data voltage (VDATA; Fig 6) to the first transistor in response to a first scan signal (Park; GW(n); Figs 6-7; ¶ [0105]) and
a third transistor (Park; T7; Fig 6; ¶ [0110]) that transmits an initialization voltage to the first pixel electrode of the first display element in response to a second scan signal (Park; EB1(n); Figs 6-7; ¶ [0134]),
wherein a frequency of the first scan signal is different from a frequency of the second scan signal (Park; Fig 7 is a waveform diagram representing different scan signals that may be applied to the pixel circuit of Fig 6 over the same time period (x-axis; ¶ [0115-118,0119-135]), and one can observe that the second scan signal EB1(n) has twice as many y-deflections as does the first scan signal GW(n), indicating a frequency twice as high.
Regarding claim 13, Park in view of Gan discloses the display apparatus of claim 12, wherein the frequency of the second scan signal is higher than the frequency of the first scan signal (as explained for claim 12).
Regarding claim 17, Park discloses a display apparatus comprising:
a data line (171B {171}; Figs 3,{6}; ¶ [0057]); and,
a pixel electrode (blue pixel anode AEB; Fig 3; ¶ [0058-59) comprising:
a first electrode portion (AEB1; Fig 3) and a second electrode portion (AEB2; Fig 3) spaced apart from each other with the data line between the first electrode portion and the second electrode portion, and
a third electrode portion (AEB3; Fig 3) electrically connecting the first electrode portion to the second electrode portion (Park; as shown in Fig 3; ¶ [0077]).
Park does not disclose, the data line comprising:
a first conductive pattern layer extend in a first direction,
a second conductive pattern layer extend in the first direction and spaced apart from the first conductive pattern layer, and
a connection pattern layer extending in the first direction and electrically connecting the first conductive pattern layer to the second conductive pattern layer; and
the third electrode portion at least partially overlapping the connection pattern layer,
wherein the first conductive pattern layer and the second conductive pattern layer are disposed on a same layer between the pixel electrode and the connection pattern layer.
In the same field of endeavor, Gan discloses a jumper wire (108; Fig 1; ¶ [0057-58]) extending in a first direction (vertical, Fig 1) and electrically connecting first and second portions of a data line (102; Fig 1; ¶ [0057-58]), the first and second portions being separated by a gap and extending in the first direction, the first and second portions being disposed on a same layer and overlapping a scan line (103; Fig 1; ¶ [0057-58]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the capacitance reduction method of Gan with the display apparatus of Park by substituting the data line and jumper wire of Gan for the data line of Park, such that the jumper wire overlaps a portion of the third electrode portion AEB3. One would have been motivated to do this in order to reduce a capacitance between a connecting portion AEB3 of the blue pixel anode which overlaps with the second data line 171B (Park; Fig 3; ¶ [0077]), since Park has identified the need for reduced capacitance (Park; ¶ [0027,0067-69]) in order to enable high speed driving, and Gan has disclosed the jumper wire structure formed on a different layer in order to increase a distance (thickness) between two lines having capacitance between them as a method for reducing the capacitance. Reducing the capacitance between AEB3 and 171B would further reduce a capacitance between the whole of the blue pixel anode AEB and the second data line 171B. One would have had a reasonable expectation of success with the combination because such jumper wire configurations for routing lines between different layers are well known in the art.
Regarding the limitation wherein the first conductive pattern layer and the second conductive pattern layer (first and second portions of the data line) are disposed on a same layer (Gan; ¶ [0057-58], as mentioned above) between the pixel electrode and the first connection pattern layer (jumper wire), this would have been obvious to a person having ordinary skill in the art in order to increase a distance between the pixel electrode and the data line and thereby reduce a capacitance therebetween. (In the case of Gan, the capacitance to be reduced is between the data line 102 and a scan line 103 below (Gan; Fig 1), so the jumper is above the data line to increase capacitance; for the case of Park, the capacitance is between the data line 171B and the pixel electrode AEB, so the jumper should be below the data line to increase a distance and correspondingly a capacitance therebetween).
Regarding claim 18, Park in view of Gan discloses the display apparatus of claim 17, further comprising:
a display element (Park; blue pixel B; Fig 3; ¶ [0051-52,0058-59]) comprising the pixel electrode (Park; AEB; Fig 3); and
a pixel circuit (Park; PXB; Figs 3 {6}; ¶ [0053-54,0095-114]) that drives the display element, wherein
the pixel circuit comprises:
a first transistor (Park; T1; Fig 6; ¶ [0104]) that controls a magnitude of a driving current flowing through the display element;
a second transistor (Park; T2; Fig 6; ¶ [0104]) that electrically connects the data line (171; Fig 6) to the first transistor in response to a first scan signal (Park; GW(n); Figs 6-7; ¶ [0105]) and
a third transistor (Park; T7; Fig 6; ¶ [0110]) that transmits an initialization voltage (VINIT; Fig 6) to the first pixel electrode of the first display element in response to a second scan signal (Park; EB1; Figs 6-7; ¶ [0134]), and
a frequency of the first scan signal is different from a frequency of the second scan signal (Park; Fig 7 is a waveform diagram representing different scan signals that may be applied to the pixel circuit of Fig 6 over the same time period (x-axis; ¶ [0115-118,0119-135]), and one can observe that the second scan signal EB1(n) has twice as many y-deflections as does the first scan signal GW(n), indicating a frequency twice as high.
Regarding claim 19, Park in view of Gan discloses the display apparatus of claim 18, wherein the frequency of the second scan signal is higher than the frequency of the first scan signal (as explained for claim 18).
Regarding claim 20, Park in view of Gan discloses the display apparatus of claim 18, wherein, in a plan view, the pixel circuit (Park; PXB; Figs 3) at least partially overlaps the first electrode portion (AEB1; Fig 3) or the second electrode portion (AEB2; as shown in Fig 3).
Regarding claim 21, Park in view of Gan discloses the display apparatus of claim 17, wherein the third electrode portion (Park; AEB3; Fig 3) electrically connects an end portion of the first electrode portion (Park; AEB1; Fig 3) to an end portion of the second electrode portion (Park; AEB2; Fig 3; upper end, as shown in Fig 3; ¶ [0078]).
Regarding claim 22, Park in view of Gan discloses the display apparatus of claim 17, but does not disclose wherein the third electrode portion (Park; AEB3; Fig 3) electrically connects a central portion of the first electrode portion to a central portion of the second electrode portion. However, this would have been obvious to a person having ordinary skill in the art. Park discloses that the anode connection AEB3 may be positioned at an upper side, a lower side, or at both an upper side and a lower side (an opening therebetween) of AEB1 and AEB2 (Park; ¶ [0078]). It is clear from the description that these are exemplary configurations and the idea is to minimize an overlap area between AEB3 and the data line 171B in order to minimize a capacitance between AEB and 171B. It would have been obvious that various positions and configurations of AEB3 may produce a same capacitance and therefore the position may be alternately chosen in accordance with other design, manufacturing or performance considerations.
Regarding claim 23, Park in view of Gan discloses the display apparatus of claim 17, but does not specifically disclose in a plan view, the first conductive pattern layer and the second conductive pattern layer are spaced apart from the pixel electrode (Park; AEB; Fig 3). However, this would have been obvious to a person having ordinary skill in the art: As applied to claim 1, the first conductive pattern and the second conductive pattern take the place of 171B in Fig 3 of Park except for a portion including a gap between the first and second conductive patterns and overlapping AEB3 and the first connection pattern. It would have been obvious in combining the structure of Gan with Park in order to reduce the parasitic coupling capacitance between the data line 171B and the pixel electrode AEB for the gap to comprise being spaced apart from the pixel electrode (for example, spaced in the first direction from AEB3) in order to ensure a sufficiently increased distance and corresponding reduced capacitance in a non-orthogonal direction from the first direction; that is, the gap should be larger than a dimension of the anode to satisfy the intended purpose).
Allowable Subject Matter
Claims 9-11, 15-16, and 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 9-11, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the first shield electrode, the first conductive pattern layer, and the second conductive pattern layer are disposed on a same layer, and the second shield electrode, the third conductive pattern layer, and the fourth conductive pattern layer are disposed on a same layer.”
Regarding claim 15-16, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the shield electrode, the first conductive pattern layer, and the second conductive pattern layer are disposed on a same layer.”
Regarding claim 24-25, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the shield electrode, the first conductive pattern layer, and the second conductive pattern layer are disposed on a same layer.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim; Kyung-Wook et al. (US 2013/0235020; the prior art discloses a configuration wherein a common voltage line is inserted between a pixel electrode and a data line to shield a capacitance therebetween);
Hwang; JaeSik (US 2017/0345877; the prior art discloses a configuration wherein a common voltage line is inserted between an anode and a data line to reduce a capacitance therebetween);
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817