Prosecution Insights
Last updated: May 29, 2026
Application No. 18/467,412

METALLIC LID STRUCTURE FOR DISSIPATING HEAT GENERATED BY A THERMAL HOT SPOT REGION OF AN IC STRUCTURE

Non-Final OA §102§103§112
Filed
Sep 14, 2023
Priority
May 25, 2023 — provisional 63/504,247 +1 more
Examiner
RODRIGUEZ VILLANU, SANDRA MILENA
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
99 granted / 111 resolved
+21.2% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
27 currently pending
Career history
153
Total Applications
across all art units

Statute-Specific Performance

§103
68.9%
+28.9% vs TC avg
§102
4.5%
-35.5% vs TC avg
§112
24.7%
-15.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 111 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election without traverse of Invention I, (claims 1-12 and 21-28), in the reply filed on 01/23/2026 is acknowledged. Claims 13-20 were canceled by Applicant. Claims 21-28 are new. Claims 1-12 and 21-28 are pending. Claim Objections Claim 27 is objected to because of the following informalities: “…the structure of claim 23, further comprising. …”. It should be read “…the structure of claim 23, further comprising: …” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 25-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Re: claim 25, it recites the limitation “…a region of the first IC die or a region of the second IC die … the TSVs are vertically aligned with the first region or the second region” is not explained. The limitation has an antecedent issue of “the first region or the second region”. Therefore, it is indefinite. For the examination purpose, the limitation “…a region of the first IC die or a region of the second IC die … the TSVs are vertically aligned with the first region or the second region” is interpreted as “…a region of the first IC die or a region of the second IC die … the TSVs are vertically aligned with the region of the first IC die or the region of the second IC die Regarding claim 26, this is rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 25. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claim 10 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Crippen (US 20060246621 A1, hereinafter Crippen). Re: Independent Claim 10, Crippen teaches a structure (Fig. 6), comprising: one or more integrated circuit (IC) dies (116, microelectronic devices in [0023], Figs. 4b,6-Annotated), wherein a first region (below-124, contact zones 124 of thermal vias 110 are vertically aligned to hot spots of 116, “a configuration of thermal vias provided in the die substrate, may preferably be dictated by hot spots” in [0024], Figs. 4b,6-Annotated) of the one or more IC dies (116) has a greater temperature (hot spots in [0024]) than a second region (out-below-124 a region outside of below-124, Figs. 4b,6-Annotated) of the one or more IC dies (116) that neighbors the first region (below-124); PNG media_image1.png 396 674 media_image1.png Greyscale Crippen’s Figure 6-Annotated. a substrate (100 a die substrate made of silicon in [0016,0023], Figs. 4b,6-Annotated) disposed over the one or more IC dies (116), wherein the substrate (100) includes a plurality of through substrate vias (TSVs) (110, thermal vias 110 are through vias in [0023], Figs. 4b,6-Annotated), and wherein a location of the TSVs (110) is vertically aligned ([0024]) with a location of the first region (below-124) of the one or more IC dies (116); and a thermally conductive lid structure (140, a thermal interface material, such as solder in [0026], Figs. 4b,6-Annotated) disposed over the substrate (100), wherein the thermally conductive lid structure (140) is thermally coupled to the first region (below-124) of the one or more IC dies (116) at least in part through the TSVs (110). Claim Rejections - 35 USC § 103 The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Crippen in view of Refai-Ahmed et al. (US 11373929 B1, hereinafter Refai-Ahmed). Re: Claim 11, Crippen discloses the structure of claim 10, Crippen does not expressly disclose further comprising: a metallization structure disposed between the substrate and the thermally conductive lid structure, wherein the metallization structure is in direct contact with the TSVs; and a thermal interface material (TIM) disposed between the metallization structure and the thermally conductive lid structure. PNG media_image2.png 476 714 media_image2.png Greyscale Refai-Ahmed’s Figure 1-Annotated. However, in the same semiconductor device field of endeavor, Refai-Ahmed discloses a metallization structure (102 a heat spreader made of metal in Col. 5, lines 16-20, Fig.1-Annotated) and a thermal interface material (TIM) (114 a TIM in Col. 5, lines 23-25, Fig.1-Annotated) disposed between the metallization structure (102) and the thermally conductive lid structure (184 a cooling device made of metal in Col. 7,44-45, Fig.1-Annotated). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Refai-Ahmed’s feature of a metallization structure and a thermal interface material (TIM) disposed between the metallization structure and the thermally conductive lid structure to the Crippen’s device to have a metallization structure disposed between the substrate and the thermally conductive lid structure, wherein the metallization structure is in direct contact with the TSVs; and a thermal interface material (TIM) disposed between the metallization structure and the thermally conductive lid structure to enhances local-level heat transfer to the cooling plate assembly (Col. 5, lines 21-22, Refai-Ahmed). Claim(s) 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Crippen. Re: Claim 12, Crippen discloses the structure of claim 10, Crippen does not expressly disclose wherein the thermally conductive lid structure includes a single block of copper. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as copper (140 thermal interface material disclosed by Crippen made of a known material as copper) based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP § 2144.07. Claim(s) 21-22 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Crippen in view of Elsherbini et al. (US 20220199546 A1, hereinafter Elsherbini). Re: Claim 21, Crippen discloses the structure of claim 10, Crippen does not expressly disclose wherein at least one of the one or more IC dies includes a System on a Chip (SoC) die. However, in the same semiconductor device field of endeavor, Elsherbini discloses wherein at least one of the one or more IC dies (102-3, 102 a stack of IC dies in [0032], Fig. 1) includes a System on a Chip (SoC) die ([0080]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Elsherbini’s feature of wherein at least one of the one or more IC dies includes a System on a Chip (SoC) die to the Crippen’s device to add more electronic components to the device ([0080], Elsherbini). Re: Claim 22, Crippen discloses the structure of claim 10, Crippen does not expressly disclose wherein the one or more IC dies includes a first subset of IC dies and a second subset of IC dies, and wherein the second subset of IC dies are located above, and bonded to, the first subset of IC dies. However, in the same semiconductor device field of endeavor, Elsherbini discloses wherein the one or more IC dies (102 a stack of IC dies in [0032], Fig. 1) includes a first subset of IC dies (102-1, 102 a stack of IC dies in [0032], Fig. 1) and a second subset of IC dies (102-3, 102 a stack of IC dies in [0032], Fig. 1), and wherein the second subset of IC dies (102-3) are located above (Fig.1), and bonded to, the first subset of IC dies (102-1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Elsherbini’s feature of wherein the one or more IC dies includes a first subset of IC dies and a second subset of IC dies, and wherein the second subset of IC dies are located above, and bonded to, the first subset of IC dies to the Crippen’s device to add more electronic components to the device ([0080], Elsherbini). Claim(s) 1-4 and 8-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Elsherbini et al. (US 20220199546 A1, hereinafter Elsherbini) in view of Crippen (US 20060246621 A1, hereinafter Crippen). Re: Independent Claim 1, Elsherbini discloses a structure (Fig. 1), comprising: PNG media_image3.png 440 652 media_image3.png Greyscale Elsherbini’s Figure 1-Annotated. a bottom level integrated circuit (IC) die (102-1, 102 a stack of IC dies in [0032], Fig. 1); one or more top level IC dies (102-3, 102 a stack of IC dies in [0032], Fig. 1), wherein a first side (Fig. 1-Annotated) of the one or more top level IC dies (102-3) is bonded to the bottom IC die (102-1); a metallic lid structure (152, heat transfer structure made of metal in [0038], Fig. 1) Elsherbini does not expressly disclose a supporting substrate coupled to a second side of the one or more top level IC dies; a plurality of conductive through-substrate vias (TSVs) that each extend vertically through the supporting substrate and a metallic lid structure disposed over the supporting substrate, wherein the metallic lid structure is thermally coupled to the conductive TSVs. However, in the same semiconductor device field of endeavor, Crippen discloses a supporting substrate (100 a die substrate made of silicon in [0016,0023], Figs. 4b,6-Annotated) coupled to a second side of the one or more dies (116, microelectronic devices in [0023], Figs. 4b,6-Annotated); a plurality of conductive through-substrate vias (TSVs) (110, thermal vias 110 are through vias in [0023], Figs. 4b,6-Annotated) that each extend vertically through the supporting substrate (100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Crippen’s feature of a supporting substrate coupled to a second side of the one or more dies; a plurality of conductive through-substrate vias (TSVs) that each extend vertically through the supporting substrate to Elsherbini’s device to have a supporting substrate coupled to a second side of the one or more top level IC dies; a plurality of conductive through-substrate vias (TSVs) that each extend vertically through the supporting substrate and a metallic lid structure disposed over the supporting substrate, wherein the metallic lid structure is thermally coupled to the conductive TSVs to enhance a conduction of heat from active devices on the die toward a heat spreader ([0019], Crippen). Re: Claim 2, Elsherbini modified by Crippen discloses the structure of claim 1, wherein the supporting substrate (100’s Crippen applied to Elsherbini) includes a silicon substrate (100’s Crippen in [0016] applied to Elsherbini). Re: Claim 3, Elsherbini modified by Crippen discloses the structure of claim 1, Elsherbini modified by Crippen does not expressly disclose wherein: the bottom level IC die or the one or more top level IC dies include a thermal hot spot region that has an elevated temperature compared to a rest of the bottom level IC die or a rest of the one or more top level IC dies; and the conductive TSVs are vertically aligned with the thermal hot spot region. However, in the same semiconductor device field of endeavor, Crippen discloses the bottom level IC die or the one or more top level IC dies (116, microelectronic devices in [0023], Figs. 4b,6-Annotated) include a thermal hot spot region (below-124, contact zones 124 of thermal vias 110 are vertically aligned to hot spots of 116, “a configuration of thermal vias provided in the die substrate, may preferably be dictated by hot spots” in [0024], Figs. 4b,6-Annotated) that has an elevated temperature compared to a rest of (out-below-124 a region outside of below-124, Figs. 4b,6-Annotated) the bottom level IC die or a rest of the one or more top level IC dies (116); and the conductive TSVs (110, thermal vias 110 are through vias in [0023], Figs. 4b,6-Annotated) are vertically aligned ([0024]) with the thermal hot spot region (below-124). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Crippen’s feature of wherein: the bottom level IC die or the one or more top level IC dies include a thermal hot spot region that has an elevated temperature compared to a rest of the bottom level IC die or a rest of the one or more top level IC dies; and the conductive TSVs are vertically aligned with the thermal hot spot region to Elsherbini’s device to enhance a conduction of heat from active devices on the die toward a heat spreader ([0019], Crippen). Re: Claim 4, Elsherbini modified by Crippen discloses the structure of claim 3, wherein: the bottom level IC die or the one or more top level IC dies (102-1,3’s Crippen) include a plurality of thermal hot spot regions (below-124’s Crippen applied to Elsherbini); the plurality of conductive TSVs (below-124’s Crippen applied to Elsherbini) include a plurality of different subsets of conductive TSVs ([0024] Crippen); and each of the subsets of conductive TSVs is vertically aligned ([0024] Crippen) with a respective one of the thermal hot spot regions (below-124’s Crippen applied to Elsherbini). Re: Claim 8, Elsherbini modified by Crippen discloses the structure of claim 1, wherein the one or more top level IC dies (102-3 Elsherbini) include at least a first System on a Chip (SoC) die and a second SoC die ([0080], Elsherbini). Re: Claim 9, Elsherbini modified by Crippen discloses the structure of claim 1, Elsherbini modified by Crippen does not expressly disclose wherein the metallic lid structure includes a copper lid structure. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as copper (the metal lid structure disclosed by Elsherbini made of a known material as copper) based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP § 2144.07. Claim(s) 5-7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Elsherbini et al. (US 20220199546 A1, hereinafter Elsherbini) in view of Crippen (US 20060246621 A1, hereinafter Crippen) and further in view of Refai-Ahmed et al. (US 11373929 B1, hereinafter Refai-Ahmed). Re: Claim 5, Elsherbini modified by Crippen discloses the structure of claim 1, Elsherbini modified by Crippen does not expressly disclose further comprising a first metallization structure disposed between the supporting substrate and the metallic lid structure, wherein the first metallization structure is thermally coupled to the conductive TSVs. However, in the same semiconductor device field of endeavor, Refai-Ahmed discloses a first metallization structure (102 a heat spreader made of metal in Col. 5, lines 16-20, Figs.1-Annotated). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Refai-Ahmed’s feature of a first metallization structure to the combination of Elsherbini and Crippen to have a first metallization structure disposed between the supporting substrate and the metallic lid structure, wherein the first metallization structure is thermally coupled to the conductive TSVs to enhances local-level heat transfer to the cooling plate assembly (Col. 5, lines 21-22, Refai-Ahmed). Re: Claim 6, Elsherbini modified by Crippen and Refai-Ahmed discloses the structure of claim 5, Elsherbini modified by Crippen and Refai-Ahmed does not expressly disclose further comprising: a thermal interface material (TIM) disposed between the first metallization structure and the metallic lid structure; and a second metallization structure disposed between the metallic lid structure and the TIM. However, in the same semiconductor device field of endeavor, Refai-Ahmed discloses a thermal interface material (TIM) (114 a TIM in Col. 5, lines 23-25, Fig.1-Annotated) disposed between the first metallization structure (102 a heat spreader made of metal in Col. 5, lines 16-20, Figs.1-Annotated) and the metallic lid structure (184 a cooling device made of metal in Col. 7,44-45, Fig.1-Annotated); and a second metallization structure (182 a cooling plate made of metal in Col. 6, lines 45-50, Fig.1-Annotated) disposed between the metallic lid structure (184) and the TIM (114). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Refai-Ahmed’s feature of a thermal interface material (TIM) disposed between the first metallization structure and the metallic lid structure; and a second metallization structure disposed between the metallic lid structure and the TIM to the combination of Elsherbini and Crippen to enhances local-level heat transfer to the cooling plate assembly (Col. 5, lines 21-22, Refai-Ahmed). Re: Claim 7, Elsherbini modified by Crippen and Refai-Ahmed discloses the structure of claim 6, Elsherbini modified by Crippen and Refai-Ahmed does not expressly disclose wherein the TIM comprises a solder material. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as a TIM made of a solder material (a 154-TIM made of a solder material in [0037] disclosed by Elsherbini) based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP § 2144.07. Claim(s) 23-28 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Elsherbini et al. (US 20220199546 A1, hereinafter Elsherbini) in view of Crippen (US 20060246621 A1, hereinafter Crippen) and further in view of Refai-Ahmed et al. (US 11373929 B1, hereinafter Refai-Ahmed). Re: Independent Claim 23, Elsherbini discloses a structure (Fig. 1), comprising: a first integrated circuit (IC) die (102-1, 102 a stack of IC dies in [0032], Fig. 1); a second IC die (102-3, 102 a stack of IC dies in [0032], Fig. 1) located above the first IC die (102-1), wherein the second IC die (102-3) comprises a System on a Chip (SoC) ([0080]), and wherein a first side (Fig. 1-Annotated) of the second IC die (102-3) is bonded to the first IC die (102-1); a bulk structure (152, heat transfer structure made of metal in [0038], Fig. 1), wherein the bulk structure (152) provides thermal dissipation for the first IC die (102-1) or the second IC die through the TSVs. Elsherbini does not expressly disclose a substrate coupled to a second side of the second IC die, wherein the second side is opposite the first side; a plurality of through-substrate vias (TSVs) that each extend vertically through the substrate; a bulk copper structure over the substrate and a first metallization structure disposed between the substrate and the bulk copper structure, wherein the first metallization structure is thermally coupled to the TSVs. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as copper (the metal lid structure disclosed by Elsherbini made of copper) based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP § 2144.07. Still, Elsherbini does not expressly disclose a substrate coupled to a second side of the second IC die, wherein the second side is opposite the first side; a plurality of through-substrate vias (TSVs) that each extend vertically through the substrate; a bulk copper structure over the substrate and a first metallization structure disposed between the substrate and the bulk copper structure, wherein the first metallization structure is thermally coupled to the TSVs. However, in the same semiconductor device field of endeavor, Crippen discloses a substrate (100 a die substrate made of silicon in [0016,0023], Figs. 4b,6-Annotated) coupled to a second side of the second IC die (116, microelectronic devices in [0023], Figs. 4b,6-Annotated), wherein the second side is opposite the first side (Fig. 6-Annotated); a plurality of through-substrate vias (TSVs) (110, thermal vias 110 are through vias in [0023], Figs. 4b,6-Annotated) that each extend vertically through the substrate (100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Crippen’s feature of a substrate coupled to a second side of the second IC die, wherein the second side is opposite the first side; a plurality of through-substrate vias (TSVs) that each extend vertically through the substrate to Elsherbini’s device to have a bulk structure over the substrate to enhance a conduction of heat from active devices on the die toward a heat spreader ([0019], Crippen). Still, Elsherbini and Crippen does not expressly disclose a first metallization structure disposed between the substrate and the bulk copper structure, wherein the first metallization structure is thermally coupled to the TSVs. However, in the same semiconductor device field of endeavor, Refai-Ahmed discloses a first metallization structure (102 a heat spreader made of metal in Col. 5, lines 16-20, Figs.1-Annotated). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Refai-Ahmed’s feature of a first metallization structure to the combination of Elsherbini and Crippen to have a first metallization structure disposed between the substrate and the bulk copper structure, wherein the first metallization structure is thermally coupled to the TSVs to enhances local-level heat transfer to the cooling plate assembly (Col. 5, lines 21-22 , Refai-Ahmed). Re: Claim 24, Elsherbini modified by Crippen and Refai-Ahmed discloses the structure of claim 23, wherein the substrate (100’s Crippen applied to Elsherbini) is a silicon substrate (100’s Crippen in [0016] applied to Elsherbini). Re: Claim 25, Elsherbini modified by Crippen and Refai-Ahmed discloses the structure of claim 23, Elsherbini modified by Crippen and Refai-Ahmed does not expressly disclose wherein: a region of the first IC die or a region of the second IC die generates more heat than a rest of the first IC die or a rest of the second IC die; and the TSVs are vertically aligned with the region of the first IC die or the region of the second IC die. However, in the same semiconductor device field of endeavor, Crippen discloses a region (below-124, contact zones 124 of thermal vias 110 are vertically aligned to hot spots of 116, “a configuration of thermal vias provided in the die substrate, may preferably be dictated by hot spots” in [0024], Figs. 4b,6-Annotated) of the first IC die or a region of the second IC die (116, microelectronic devices in [0023], Figs. 4b,6-Annotated) generates more heat (hot spots in [0024]) than a rest of the first IC die or a rest of the second IC die (116); and the TSVs (110, thermal vias 110 are through vias in [0023], Figs. 4b,6-Annotated) are vertically aligned ([0024]) with the region of the first IC die or the region of the second IC die. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Crippen’s feature of wherein: a region of the first IC die or a region of the second IC die generates more heat than a rest of the first IC die or a rest of the second IC die; and the TSVs are vertically aligned with the region of the first IC die or the region of the second IC die to the combination of Elsherbini, Crippen and Refai-Ahmed to enhance a conduction of heat from active devices on the die toward a heat spreader ([0019], Crippen). Re: Claim 26, Elsherbini modified by Crippen and Refai-Ahmed discloses the structure of claim 25, wherein: the plurality of TSVs (110’s Crippen applied to Elsherbini) includes a plurality of subsets of TSVs ([0024] Crippen); one subset of the TSVs is vertically aligned (below-124, contact zones 124 of thermal vias 110 are vertically aligned to hot spots of 116, “a configuration of thermal vias provided in the die substrate, may preferably be dictated by hot spots” in [0024], Figs. 4b,6-Annotated) with the region of the first IC die (116’s Crippen); and another subset of the TSVs is vertically aligned ([0024] Crippen) with the region of the second IC die (116’s Crippen). Re: Claim 27, Elsherbini modified by Crippen and Refai-Ahmed discloses the structure of claim 23, further comprising: a thermal interface material (TIM) (154 TIM in [0020] Elsherbini) disposed between the first metallization structure (102’s Refai-Ahmed applied to Elsherbini, Fig.1-Annotated) and the bulk copper structure (152’s Elsherbini); Elsherbini modified by Crippen and Refai-Ahmed does not expressly disclose a second metallization structure disposed between the bulk copper structure and the TIM. However, in the same semiconductor device field of endeavor, Refai-Ahmed discloses a second metallization structure (182 a cooling plate made of metal in Col. 6, lines 45-50, Fig.1-Annotated) disposed between the thermal structure (184 a cooling device made of metal in Col. 7,44-45, Fig.1-Annotated) and the TIM (114 a TIM in Col. 5, lines 23-25, Fig.1-Annotated). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Refai-Ahmed’s feature of a second metallization structure disposed between the thermal structure and the TIM to the combination of Elsherbini, Crippen and Refai-Ahmed to have a second metallization structure disposed between the bulk copper structure and the TIM to enhances local-level heat transfer to the cooling plate assembly (Col. 5, lines 21-22, Refai-Ahmed). Re: Claim 28, Elsherbini modified by Crippen and Refai-Ahmed discloses the structure of claim 27, Elsherbini modified by Crippen and Refai-Ahmed does not expressly disclose wherein the TIM comprises a solder material. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as a TIM made of a solder material (a 154-TIM made of a solder material in [0037] disclosed by Elsherbini) based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP § 2144.07. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lan et al. (US 20230197554 A1) teaches “THERMAL BRIDGE INTERPOSER STRUCTURE”. This document is related to an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure. Chen et al. (US 20180190638 A1) teaches “COWOS STRUCTURES AND METHOD OF FORMING THE SAME”. This document is related to a semiconductor device including a substrate between a heat dissipation lid and dies for providing structural support to the device and evenly distribute heat from package. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
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Prosecution Timeline

Sep 14, 2023
Application Filed
Mar 30, 2026
Non-Final Rejection mailed — §102, §103, §112
May 21, 2026
Examiner Interview Summary
May 21, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12635174
Semiconductor Device and Fabricating Method Thereof
3y 3m to grant Granted May 19, 2026
Patent 12635254
DEVICE INTEGRATING TRENCH TYPE POWER DEVICE AND SOURCE CAPACITOR AND MANUFACTURING METHOD THEREOF
3y 0m to grant Granted May 19, 2026
Patent 12635173
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
2y 11m to grant Granted May 19, 2026
Patent 12621993
THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
3y 5m to grant Granted May 05, 2026
Patent 12615782
SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE
3y 2m to grant Granted Apr 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+10.1%)
2y 10m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 111 resolved cases by this examiner. Grant probability derived from career allowance rate.

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