DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 08/12/2026 has been entered. Applicant's amendment have overcome
the objections to the Claims and 112 (b) rejections previously set forth in the Non-Final Office Action dated on 03/30/2026. Claims 13-20 are canceled. Claims 1-12 and 21-28 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 08/12/2026, have been fully considered, the arguments/amendments regarding claim 1 of “a plurality of bonding pads and a dielectric structure that laterally surrounds the bonding pads, wherein the bonding pads are coupled to the TSVs, respectively, and wherein the supporting substrate and the one or more top level IC dies are bonded together by the bonding pads and the dielectric structure” and claims 10 and 23 “wherein the first metallization structure is a part of a multi-layer interconnect (MLI) structure that includes a dielectric material and a plurality of horizontal interconnect features and vertical interconnect features” are moot because do not apply to new ground of rejections with a new references, US 20090273068 A1, to Kaskoun and US 20140252645 A1 to Kim, being used in the current rejection, see detail below.
Specification
The disclosure is objected to because of the following informalities: in Paragraph [0050] of the
Specification describes that Figure 8 shows a thermal hotspot regions 600A, but element 600A is not shown in Figure 8.
Appropriate correction is required.
Drawings
The drawings are objected to because in Figure 8 is showed thermal hot spots 600, however,
these are referred as element 600A in paragraph [0050] of the Specifications. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations “…wherein the metallization structure is a part of a multi-layer interconnect (MLI) structure that includes a dielectric material and a plurality of interconnect features surrounded by the dielectric material” in claim 5, “a metallization structure disposed between the substrate and the thermally conductive lid structure, wherein the metallization structure is a part of a multi-layer interconnect (MLI) structure that includes a combination of dielectric layers and electrically conductive layers” in claim 10 and “wherein the first metallization structure is a part of a multi-layer interconnect (MLI) structure that includes a dielectric material and a plurality of horizontal interconnect features and vertical interconnect features” in claim 23 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 10 is objected to because the limitation “wherein a first region of the one or more IC dies
has a greater temperature than a second region of the one or more IC dies that neighbors the first region” is unclear of what would happen if the device of the instant application is off and all the regions have the same temp.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Elsherbini et al. (US 20220199546 A1, hereinafter Elsherbini, of the record).
Re: Independent Claim 1, Elsherbini discloses a structure (Fig. 1), comprising:
a bottom level integrated circuit (IC) die (102-1, 102 a stack of IC dies in [0032], Fig. 1);
one or more top level IC dies (102-3, 102 a stack of IC dies in [0032], Fig. 1), wherein a first side (Fig. 1-Annotated) of the one or more top level IC dies (102-3) is bonded to the bottom IC die (102-1);
a metallic lid structure (152, heat transfer structure made of metal in [0038], Fig. 1)
a supporting substrate (150, interposer in [0020], Fig. 1) with a plurality of conductive through-substrate vias (TSVs) (116, conductive vias in [0027], Fig. 1) therein;
a plurality of bonding pads (110, contacts in [0021], Fig. 1) and a dielectric structure (108, dielectric in [0021], Fig. 1) that laterally surrounds the bonding pads (Fig. 1), wherein the bonding pads are coupled (all elements are electrically coupled, Fig. 1) to the TSVs (116) , respectively, and wherein the supporting substrate (150) and the one or more top level IC dies (102-3) are bonded together by the bonding pads (110) and the dielectric structure (108); and a metallic lid structure (152, heat transfer structure in [0020], Fig. 1) disposed over the supporting substrate (150), wherein the metallic lid structure (152) is thermally coupled to the conductive TSVs (116).
Second ground of rejection of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 8-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Elsherbini et al. (US 20220199546 A1, hereinafter Elsherbini, of the record) in view of Kaskoun et al. (US 20090273068 A1, hereinafter Kaskoun).
Re: Independent Claim 1, Elsherbini discloses a structure (Fig. 1), comprising:
PNG
media_image1.png
440
652
media_image1.png
Greyscale
Elsherbini’s Figure 1-Annotated.
a bottom level integrated circuit (IC) die (102-1, 102 a stack of IC dies in [0032], Fig. 1);
one or more top level IC dies (102-3, 102 a stack of IC dies in [0032], Fig. 1), wherein a first side (Fig. 1-Annotated) of the one or more top level IC dies (102-3) is bonded to the bottom IC die (102-1);
a metallic lid structure (152, heat transfer structure made of metal in [0038], Fig. 1)
Elsherbini does not expressly disclose a supporting substrate with a plurality of conductive through-substrate vias (TSVs) therein a plurality of bonding pads and a dielectric structure that laterally surrounds the bonding pads, wherein the bonding pads are coupled to the TSVs, respectively, and wherein the supporting substrate and the one or more top level IC dies are bonded together by the bonding pads and the dielectric structure; and a metallic lid structure disposed over the supporting substrate, wherein the metallic lid structure is thermally coupled to the conductive TSVs.
However, in the same semiconductor device field of endeavor, Kaskoun discloses a supporting substrate (11 a die substrate comprising silicon in [0007,0019,0023], Fig. 2) with a plurality of conductive through-substrate vias (TSVs) (201, 203, a TSV array 200 having individual TSVs 201, 202, and 203 in [0023 Fig. 2) therein a plurality of bonding pads (204,205 as electrical paths such bond pads described in [0020], Fig. 2) and a dielectric structure (a dielectric material include in layer 102 and between 204 and 205 as required for electrical isolations, Fig. 2-Annotated) that laterally surrounds the bonding pads (204,205), wherein the bonding pads (204,205) are coupled to the TSVs (201, 203), respectively.
PNG
media_image2.png
250
793
media_image2.png
Greyscale
Kaskoun’s Figure 2-Annotated.
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Kaskoun’s supporting substrate 11 between the Elsherbini’s thermal interface material 154 and the Elsherbini’s one or more top level IC dies 102-3, wherein the Kaskoun’s supporting substrate 11 includes a plurality of conductive through-substrate vias (TSVs), therein a plurality of bonding pads and a dielectric structure that laterally surrounds the bonding pads, wherein the bonding pads are coupled to the TSVs, in order to have the predictable result of improving thermal conductivity for heat from the hot spot ([0023], Kaskoun).
Therefore, Elsherbini in view of Kaskoun teaches wherein the supporting substrate (11, Kaskoun) and the one or more top level IC dies (102-3, Fig. 1, Elsherbini) are bonded together by the bonding pads (204,205, Kaskoun) and the dielectric structure (dielectric between 204,205, Kaskoun) and a metallic lid structure (152, Fig. 1, Elsherbini) disposed over the supporting substrate (11, Kaskoun), wherein the metallic lid structure (152, Fig. 1, Elsherbini) is thermally coupled to the conductive TSVs (201,203, Kaskoun).
Re: Claim 2, Elsherbini modified by Kaskoun discloses the structure of claim 1, wherein the supporting substrate (11, in [0007], having through-silicon-vias (TSVs), Kaskoun) includes a silicon substrate.
Re: Claim 3, Elsherbini modified by Kaskoun discloses the structure of claim 1,
Elsherbini modified by Kaskoun does not expressly disclose wherein: the bottom level IC die or the one or more top level IC dies include a thermal hot spot region that has an elevated temperature compared to a rest of the bottom level IC die or a rest of the one or more top level IC dies; and the conductive TSVs are vertically aligned with the thermal hot spot region.
However, in the same semiconductor device field of endeavor, Kaskoun discloses the bottom level IC die or the one or more top level IC dies (12, die in [0022], Figs. 2) include a thermal hot spot region (110 hot spot in [0022], Figs. 2) that has an elevated temperature compared to a rest of ([0022]) the bottom level IC die or a rest of the one or more top level IC dies (12); and the conductive TSVs (201,203, Fig. 2, Kaskoun) are vertically aligned ([0023], Fig. 2) with the thermal hot spot region (110).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Kaskoun’s feature of wherein: the bottom level IC die or the one or more top level IC dies include a thermal hot spot region that has an elevated temperature compared to a rest of the bottom level IC die or a rest of the one or more top level IC dies; and the conductive TSVs are vertically aligned with the thermal hot spot region to Elsherbini’s device in order to have the predictable result of providing thermal conductivity for heat from the hot spot ([0023], Kaskoun).
Re: Claim 4, Elsherbini modified by Kaskoun discloses the structure of claim 3,
wherein: the bottom level IC die or the one or more top level IC dies include a plurality of thermal hot spot regions; the plurality of conductive TSVs include a plurality of different subsets of conductive TSVs; and each of the subsets of conductive TSVs is vertically aligned with a respective one of the thermal hot spot regions.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the bottom level IC die or the one or more top level IC dies include a plurality of thermal hot spot regions; the plurality of conductive TSVs include a plurality of different subsets of conductive TSVs; and each of the subsets of conductive TSVs is vertically aligned with a respective one of the thermal hot spot regions, since Kaskoun discloses a hot spot and a TSV vertically aligned with the hot spot to dissipate the heat from the die. The mere duplication of parts has no patentable significance unless a new and unexpected result is produced (2144.04.VI.B).
Re: Claim 8, Elsherbini modified by Kaskoun discloses the structure of claim 1, wherein the one or more top level IC dies (102-3 Elsherbini) include at least a first System on a Chip (SoC) die and a second SoC die ([0080], Elsherbini).
Re: Claim 9, Elsherbini modified by Kaskoun discloses the structure of claim 1,
Elsherbini modified by Kaskoun does not expressly disclose wherein the metallic lid structure includes a copper lid structure.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as copper (the metal lid structure disclosed by Elsherbini made of a known material as copper) based on its suitability for its intended use supported a prima facie obviousness determination (MPEP § 2144.07).
Third ground of rejection of claim 1.
Claim(s) 1, 5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20140252645 A1, hereinafter Kim) in view of Kaskoun et al. (US 20090273068 A1, hereinafter Kaskoun).
Re: Independent Claim 1, Kim discloses a structure (Fig. 2), comprising:
PNG
media_image3.png
398
520
media_image3.png
Greyscale
Kim’s Figure 2-Annotated.
a bottom level integrated circuit (IC) die (222-1 a die from one or more dies in 222, as second package 206 in [0038, 0085], Fig. 2-Annotated);
one or more top level IC dies (222-2 a die from one or more dies in 222, Fig. 2-Annotated), wherein a first side of the one or more top level IC dies (222-2) is bonded to the bottom IC die (222-1);
a supporting substrate (220 in [0038], Fig. 2);
a metallic lid structure (218, a heat spreader, as common in the art as a block of metal material such as copper, in [0040], Fig. 2); and a metallic lid structure (218) disposed over the supporting substrate (220).
Kim does not expressly disclose a supporting substrate with a plurality of conductive through-substrate vias (TSVs) therein; a plurality of bonding pads and a dielectric structure that laterally surrounds the bonding pads, wherein the bonding pads are coupled to the TSVs, respectively, and wherein the supporting substrate and the one or more top level IC dies are bonded together by the bonding pads and the dielectric structure; wherein the metallic lid structure is thermally coupled to the conductive TSVs.
However, in the same semiconductor device field of endeavor, Kaskoun discloses a supporting substrate (11 a die substrate comprising silicon in [0007,0019,0023], Fig. 2) with a plurality of conductive through-substrate vias (TSVs) (201, 203, a TSV array 200 having individual TSVs 201, 202, and 203 in [0023 Fig. 2) therein; a plurality of bonding pads (204,205 as electrical paths such bond pads described in [0020], Fig. 2) and a dielectric structure (a dielectric material include in layer 102 and between 204 and 205 as required for electrical isolations, Fig. 2-Annotated) that laterally surrounds the bonding pads (204,205), wherein the bonding pads (204,205) are coupled to the TSVs (201, 203), respectively.
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to make the Kim’s supporting substrate have the features of the Kaskoun’s substrate 11, wherein the supporting substrate includes a plurality of conductive through-substrate vias (TSVs) therein; a plurality of bonding pads and a dielectric structure that laterally surrounds the bonding pads, wherein the bonding pads are coupled to the TSVs, respectively in order to have the predictable result of providing thermal conductivity for heat from the hot spot ([0023], Kaskoun).
Therefore, Kim in view of Kaskoun teaches wherein the supporting substrate (11, Kaskoun) and the one or more top level IC dies (222-2, Kim) are bonded together by the bonding pads (204,205, Kaskoun) and the dielectric structure (a dielectric material include in layer 102, Kaskoun).
Re: Claim 5, Kim modified by Kaskoun discloses the structure of claim 1,
further comprising a first metallization structure (212 interposer in [0040], Fig. 2, Kim) disposed between the supporting substrate (11, Kaskoun) and the metallic lid structure (218, Kim) wherein the metallization structure (212, Kim) is a part of a multi-layer interconnect (MLI) structure that includes a dielectric material and a plurality of interconnect features surrounded by the dielectric material (212 including vias, traces, and/or interconnects and one or more dielectric layers in [0040], Kim), and wherein the first metallization structure (212, Kim) is thermally coupled to the conductive TSVs (201, 203, Kaskoun).
Claim(s) 6-7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Kaskoun, and further in view of Refai-Ahmed et al. (US 11373929 B1, hereinafter Refai-Ahmed, of the record).
Re: Claim 6, Kim modified by Kaskoun discloses the structure of claim 5,
Kim modified by Kaskoun does not expressly disclose further comprising: a thermal interface material (TIM) disposed between the first metallization structure and the metallic lid structure; and a second metallization structure disposed between the metallic lid structure and the TIM.
However, in the same semiconductor device field of endeavor, Refai-Ahmed discloses a thermal interface material (TIM) (114 a TIM in Col. 5, lines 23-25, Fig.1-Annotated) disposed between the first metallization structure (102 a heat spreader made of metal in Col. 5, lines 16-20, Figs.1-Annotated) and the metallic lid structure (184 a cooling device made of metal in Col. 7,44-45, Fig.1-Annotated); and a second metallization structure (182 a cooling plate made of metal in Col. 6, lines 45-50, Fig.1-Annotated) disposed between the metallic lid structure (184) and the TIM (114).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Refai-Ahmed’s thermal interface material (TIM) 114 between the Kim’s first metallization structure 212 and the Kim’s metallic lid structure 218 in order to have the predictable result of providing enhances of local-level heat transfer to the cooling plate assembly (Col. 5, lines 21-22, Refai-Ahmed).
Therefore, Kim in view of Kaskoun and Refai-Ahmed teaches a second metallization structure (Refai-Ahmed’s second 182) disposed between the Kim’s metallic lid structure 218 and the TIM (Refai-Ahmed’s 114 applied to Kim).
Re: Claim 7, Kim modified by Kaskoun and Refai-Ahmed discloses the structure of claim 6,
Kim modified by Kaskoun and Refai-Ahmed does not expressly disclose wherein the TIM comprises a solder material, and wherein the metallic lid structure includes a copper lid.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as a TIM made of a solder material and wherein the metallic lid structure includes a copper lid (a 154-TIM made of a solder material in [0037] and 152 metallic lid in [0038] evidenced by Elsherbini) based on its suitability for its intended use supported a prima facie obviousness determination (MPEP § 2144.07).
Claim(s) 10,12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20140252645 A1, hereinafter Kim) in view of Kaskoun et al. (US 20090273068 A1, hereinafter Kaskoun).
Re: Independent Claim 10, Kim teaches a structure (Fig. 6), comprising:
one or more integrated circuit (IC) dies (222, die in [0038], Fig. 2), wherein a first region (a region above one electronic element such as CPU during operation as common in the art) of the one or more IC dies (222) has a greater temperature (expected hot spots during the device operation) than a second region (a region outside of the electronic element such as CPU during operation as common in the art) of the one or more IC dies (222) that neighbors the first region;
a substrate (220, a substrate die in [0038], Fig. 2) disposed over the one or more IC dies (222);
a thermally conductive lid structure (218, a heat spreader, as common in the art as a block of metal material such as copper, in [0040], Fig. 2) disposed over the substrate (220), wherein the thermally conductive lid structure (218) is thermally coupled to the first region of the one or more IC dies (222); and
a metallization structure (212 interposer in [0040], Fig. 2), wherein the metallization structure is a part of a multi-layer interconnect (MLI) structure that includes a combination of dielectric layers and electrically conductive layers (212 including vias, traces, and/or interconnects and one or more dielectric layers in [0040]).
Kim does not expressly disclose wherein the substrate includes a plurality of through substrate vias (TSVs), and wherein a location of the TSVs is vertically aligned with a location of the first region of the one or more IC dies, wherein the thermally conductive lid structure is thermally coupled to the first region of the one or more IC dies at least in part through the TSVs, a metallization structure disposed between the substrate and the thermally conductive lid structure.
However, in the same semiconductor device field of endeavor, Kaskoun discloses wherein the substrate (11 a die substrate in [0023], Fig. 2) includes a plurality of through substrate vias (TSVs) (201, 203, a TSV array 200 having individual TSVs 201, 202, and 203 in [0023], Fig. 2), and wherein a location of the TSVs (201, 203) is vertically aligned (Fig. 2) with a location of the first region (110 hot spot in [0023], Fig. 2) of the one or more IC dies (12);
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to make the Kim’s substrate have the features of the Kaskoun’s substrate 11 wherein the substrate includes a plurality of through substrate vias (TSVs), and wherein a location of the TSVs is vertically aligned with a location of the first region of the one or more IC dies in order to have the predictable result of providing thermal conductivity for heat from the hot spot ([0023], Kaskoun).
Therefore, Kim in view of Kaskoun teaches a thermally conductive lid structure (218, Kim) disposed over the substrate (11, Kaskoun), wherein the thermally conductive lid structure (218, Kim) is thermally coupled to the first region (hot spot regions, Kim) of the one or more IC dies (222, Kim) at least in part through the TSVs (201, 203, Kaskoun), a metallization structure (212, Kim) disposed between the substrate (11, Kaskoun) and the thermally conductive lid structure (218, Kim).
Re: Claim 12, Kim modified by Kaskoun discloses the structure of claim 10,
Kim modified by Kaskoun does not expressly disclose wherein the thermally conductive lid structure (218, Kim) includes a single block of copper.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as copper (a heat spreader disclosed by Kim, as common in the art as a block of metal material such as copper) based on its suitability for its intended use supported a prima facie obviousness determination (MPEP § 2144.07).
Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Kaskoun and further in view of Refai-Ahmed et al. (US 11373929 B1, hereinafter Refai-Ahmed, of the record).
Re: Claim 11, Kim modified by Kaskoun discloses the structure of claim 10, wherein the metallization structure (212, Fig. 2, Kim) extends to the TSVs (201, 203, Kaskoun);
Kim modified by Kaskoun does not expressly disclose wherein the structure further comprises a thermal interface material (TIM) disposed between the metallization structure and the thermally conductive lid structure.
However, in the same semiconductor device field of endeavor, Refai-Ahmed discloses wherein the structure further comprises a thermal interface material (TIM) (114 a TIM in Col. 5, lines 23-25, Fig.1-Annotated) disposed between the metallization structure (102 a heat spreader made of metal in Col. 5, lines 16-20, Fig.1-Annotated) and the thermally conductive lid structure (184 a cooling device made of metal in Col. 7,44-45, Fig.1-Annotated).
PNG
media_image4.png
476
714
media_image4.png
Greyscale
Refai-Ahmed’s Figure 1-Annotated.
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Refai-Ahmed’s TIM 114 between the Kim’s metallization structure 212 and the Kim’s thermally conductive lid structure 218 in order to have the predictable result of providing enhances of local-level heat transfer to the cooling plate assembly (Col. 5, lines 21-22, Refai-Ahmed).
Claim(s) 21-22 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Kaskoun and further in view of Elsherbini et al. (US 20220199546 A1, hereinafter Elsherbini, of the record).
Re: Claim 21, Kim modified by Kaskoun discloses the structure of claim 10,
Kim modified by Kaskoun does not expressly disclose wherein at least one of the one or more IC dies includes a System on a Chip (SoC) die.
However, in the same semiconductor device field of endeavor, Elsherbini discloses a die (1800, [0080]) comprising a System on a Chip (SoC) (some or all these components are fabricated onto a single system-on-a-chip (SoC) die in [0080]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to make the Kim’s second IC die 222-2 have the features of the Elsherbini’s die 1800 wherein the die comprises a System on a Chip (SoC) in order to have the predictable result of improving the integration of the device and reducing its size ([0080], Elsherbini).
Re: Claim 22, Kim modified by Kaskoun discloses the structure of claim 10,
Kim modified by Kaskoun does not expressly disclose wherein the one or more IC dies includes a first subset of IC dies and a second subset of IC dies, and wherein the second subset of IC dies are located above, and bonded to, the first subset of IC dies.
However, in the same semiconductor device field of endeavor, Elsherbini discloses wherein the one or more IC dies (102 a stack of IC dies in [0032], Fig. 1) includes a first subset of IC dies (102-1, 102 a stack of IC dies in [0032], Fig. 1) and a second subset of IC dies (102-3, 102 a stack of IC dies in [0032], Fig. 1), and wherein the second subset of IC dies (102-3) are located above (Fig.1), and bonded to, the first subset of IC dies (102-1).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Elsherbini’s feature of wherein the one or more IC dies includes a first subset of IC dies and a second subset of IC dies, and wherein the second subset of IC dies are located above, and bonded to, the first subset of IC dies to the Kim’s device in order to have the predictable result of adding more electronic components to the device ([0080], Elsherbini).
Claim(s) 23-26 and 28 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Elsherbini et al. and further in view of Kaskoun.
Re: Independent Claim 23, Kim discloses a structure (Fig. 1), comprising:
a first integrated circuit (IC) die (222-1 one or more die 222 in [0038, 0085], Fig. 2);
a second IC die (222-2 one or more die 222 in [0038, 0085], Fig. 2) located above the first IC die (222-1), and wherein a first side of the second IC die (222-2) is bonded to the first IC die (222-1);
a substrate (220 die in [0038], Fig. 2) coupled to a second side of the second IC die (222-2), wherein the second side is opposite the first side (Fig. 2);
a bulk structure (218, a heat spreader, as common in the art as a block of metal material such as copper in [0040], Fig. 2), wherein the bulk structure (218) provides thermal dissipation for the first IC die (222-1) or the second IC die (222-2); and
a first metallization structure (212 interposer in [0040], Fig. 2) disposed between the substrate (220) and the bulk structure (218), wherein the first metallization structure (212) is a part of a multi-layer interconnect (MLI) structure that includes a dielectric material and a plurality of horizontal interconnect features and vertical interconnect features (212 including vias, traces, and/or interconnects and one or more dielectric layers in [0040]).
Kim does not expressly disclose wherein the second IC die comprises a System on a Chip (SoC); a plurality of through-substrate vias (TSVs) that each extend vertically through the substrate; a bulk copper structure over the substrate and wherein the first metallization structure is thermally coupled to the TSVs.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as copper (the bulk structure disclosed by Kim made of copper) based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP § 2144.07.
Therefore, Kim discloses a bulk copper structure (218) over the substrate (220).
Still, Kim does not expressly disclose wherein the second IC die comprises a System on a Chip (SoC); a plurality of through-substrate vias (TSVs) that each extend vertically through the substrate; and wherein the first metallization structure is thermally coupled to the TSVs.
However, in the same semiconductor device field of endeavor, Elsherbini discloses a die (1800, [0080]) comprising a System on a Chip (SoC) (some or all these components are fabricated onto a single system-on-a-chip (SoC) die in [0080]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to make the Kim’s second IC die 222-2 have the features of the Elsherbini’s die 1800 wherein the die comprises a System on a Chip (SoC) in order to have the predictable result of improving the integration of the device and reducing its size ([0080], Elsherbini).
Still, Kim and Elsherbini does not expressly disclose a plurality of through-substrate vias (TSVs) that each extend vertically through the substrate; and wherein the first metallization structure is thermally coupled to the TSVs.
However, in the same semiconductor device field of endeavor, Kaskoun discloses a plurality of through-substrate vias (TSVs) (201, 203, a TSV array 200 having individual TSVs 201, 202, and 203 in [0023], Fig. 2) that each extend vertically (Fig. 2) through the substrate (11 a die substrate in [0023], Fig. 2);
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to make the Kim’s substrate 220 have the features of the Kaskoun’s substrate 11 wherein the substrate includes a plurality of through substrate vias (TSVs), that each extend vertically through the substrate in order to have the predictable result of providing thermal conductivity for heat from the hot spot ([0023], Kaskoun).
Therefore, Kim in view of Elsherbini and Kaskoun teaches wherein the first metallization structure (212, Kim) is thermally coupled to the TSVs (201, 203, Kaskoun).
Re: Claim 24, Kim modified by Elsherbini and Kaskoun discloses the structure of claim 23,
Kim modified by Elsherbini and Kaskoun does expressly discloses wherein the substrate is a silicon substrate.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made the selection of a known material as silicon (the substrate disclosed by Kim made of silicon) based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP § 2144.07.
Re: Claim 25, Kim modified by Elsherbini and Kaskoun discloses the structure of claim 23,
Kim modified by Elsherbini and Kaskoun does expressly discloses wherein: a region of the first IC die or a region of the second IC die generates more heat than a rest of the first IC die or a rest of the second IC die; and the TSVs are vertically aligned with the region of the first IC die or the region of the second IC die.
However, in the same semiconductor device field of endeavor, Kaskoun discloses a region (110 hot spot in [0022], Figs. 2) of the first IC die or a region of the second IC die (12, die in [0022], Figs. 2) generates more heat than a rest of the first IC die or a rest of the second IC die (12); and the TSVs (201,203, Fig. 2, Kaskoun) are vertically aligned ([0023], Fig. 2) with the region of the first IC die or the region of the second IC die (12).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Kaskoun’s feature of wherein: a region of the first IC die or a region of the second IC die generates more heat than a rest of the first IC die or a rest of the second IC die; and the TSVs are vertically aligned with the region of the first IC die or the region of the second IC die to the combination of Kim, Elsherbini and Kaskoun in order to have the predictable result of providing thermal conductivity for heat from the hot spot ([0023], Kaskoun).
Re: Claim 26, Kim modified by Elsherbini and Kaskoun discloses the structure of claim 25,
Kim modified by Elsherbini and Kaskoun does expressly disclose wherein: the plurality of TSVs includes a plurality of subsets of TSVs; one subset of the TSVs is vertically aligned with the region of the first IC die; and another subset of the TSVs is vertically aligned with the region of the second IC die.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the plurality of TSVs includes a plurality of subsets of TSVs; one subset of the TSVs is vertically aligned with the region of the first IC die; and another subset of the TSVs is vertically aligned with the region of the second IC die, since Kaskoun discloses a hot spot and a TSV vertically aligned with the hot spot to dissipate the heat from the die. The mere duplication of parts has no patentable significance unless a new and unexpected result is produced (2144.04.VI.B).
Re: Claim 28, Kim modified by Elsherbini and Kaskoun discloses the structure of claim 23,
the bulk copper structure (218, Kim) is at least as wide as the first metallization structure (212, Kim) in a horizontal direction (x-direction).
Claim(s) 27 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable Kim et al. in view of Elsherbini et al. in view of Kaskoun and further in view of Refai-Ahmed et al. (US 11373929 B1, hereinafter Refai-Ahmed, of the record).
Re: Claim 27, Kim modified by Elsherbini and Kaskoun discloses the structure of claim 23,
Kim modified by Elsherbini and Kaskoun does not expressly disclose further comprising: a thermal interface material disposed between the first metallization structure and the bulk copper structure; a second metallization structure disposed between the bulk copper structure and the TIM.
However, in the same semiconductor device field of endeavor, Elsherbini discloses a thermal interface material (TIM) (154 TIM in [0020]) disposed above the bulk structure (152, [0020]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Elsherbini’s TIM 154 between the Kim’s first metallization structure 212 and the Kim’s bulk structure 218 in order to have the predictable result of improving the heat transfer of the device ([0020], Elsherbini).
Still, Kim modified by Elsherbini and Kaskoun does not expressly disclose a second metallization structure disposed between the bulk copper structure and the TIM.
However, in the same semiconductor device field of endeavor, Refai-Ahmed discloses a second metallization structure (182 a cooling plate made of metal in Col. 6, lines 45-50, Fig.1-Annotated) disposed between the bulk structure (184 a cooling device made of metal in Col. 7,44-45, Fig.1-Annotated) and the TIM (114 a TIM in Col. 5, lines 23-25, Fig.1-Annotated).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Refai-Ahmed’s second metallization structure 182 between the Kim’s bulk structure 218 and Elsherbini’s TIM 154 (applied to Kim) in order to have the predictable result of providing enhances of local-level heat transfer to the cooling plate assembly (Col. 5, lines 21-22, Refai-Ahmed).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/
Examiner, Art Unit 2898
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
Prosecution Insights