Prosecution Insights
Last updated: April 19, 2026
Application No. 18/467,481

MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER

Non-Final OA §102§103§DP
Filed
Sep 14, 2023
Examiner
GHEYAS, SYED I
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Adeia Semiconductor Technologies LLC
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
87%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
549 granted / 666 resolved
+14.4% vs TC avg
Minimal +5% lift
Without
With
+4.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
22 currently pending
Career history
688
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
52.2%
+12.2% vs TC avg
§102
29.9%
-10.1% vs TC avg
§112
12.0%
-28.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 666 resolved cases

Office Action

§102 §103 §DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on September 14, 2023, August 27, 2024, May 13, 2025 and February 12, 2026 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Objections Claims 9 and 10 are objected to under 37 CFR 1.75(c) as being in improper dependent form for failing to further limit the subject matter of a claim previously set forth. For the purposes of examination, the Examiner interprets both claims 9 and 10 to depend on claim 1, instead of on claim 12 as recited. However, appropriate correction and/or clarification is requested. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based e-Terminal Disclaimer may be filled out completely online using web-screens. An e-Terminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about e-Terminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1-6 & 9-11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11,387,214 B2. Although U.S. Patent No. US 11,387,214 B2 is directed toward a method, the method forms an apparatus that is recited by the instant application. Regarding Claim 1, Patent No.: US 11,387,214 B2 discloses an apparatus, comprising: a first die at least partially surrounded by a first insulating material, a pad layer disposed over the first die and including at least one contact (claim 1); a second die with a second insulating material along at least one side surface of the second die, the second die directly bonded to the first die by way of a direct bonded interconnect, the second die including at least one contact directly bonded and in contact with the at least one contact of the pad layer without an intervening solder ball (claim 1); and at least one conductor through the first insulating material, the at least one conductor being in contact with the second die (claim 1). Regarding Claim 2, Patent No.: US 11,387,214 B2, as applied to claim 1, discloses the apparatus, wherein the first die is a bridging die between the second die and a third die in a reconstituted form (claim 2). Regarding Claim 3, Patent No.: US 11,387,214 B2, as applied to claim 1, discloses the apparatus, wherein the second die and a third die partially overlap a facing surface of the first die (claim 3). Regarding Claim 4, Patent No.: US 11,387,214 B2, as applied to claim 1, discloses the apparatus, wherein the at least one conductor is a through- insulator via (claim 4). Regarding Claim 5, Patent No.: US 11,387,214 B2, as applied to claim 1, discloses the apparatus, wherein a redistribution layer couples the at least one conductor for electrical conductivity with the second die (claim 6). Regarding Claim 6, Patent No.: US 11,387,214 B2, as applied to claim 1, discloses the apparatus, wherein the second die comprises fine-pitch contacts (claim 7). Regarding Claim 9, Patent No.: US 11,387,214 B2, as applied to claim 12, discloses the apparatus, wherein the first insulating material comprises a molding material (claim 1). Regarding Claim 10, Patent No.: US 11,387,214 B2, as applied to claim 12, discloses the apparatus, wherein the at least one conductor comprises a via through the first insulating material (claim 4). Regarding Claim 11, Patent No.: US 11,387,214 B2, as applied to claim 10, discloses the apparatus, wherein the first insulating material comprises an encapsulating material and the via extends through the encapsulating material (claim 4). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6, and 9-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 20160071818 A). Regarding Claim 1, Wang et al. discloses an apparatus, comprising: a first die at least partially surrounded by a first insulating material, a pad layer disposed over the first die and including at least one contact (Par. 0251-0265; Figs. 12C-12D – first die 110N; lower portion of 1210 that is below a second die 110F.1 and a third die 110F.2 could be considered as the first insulating material; pad layer comprising contacts 210A); PNG media_image1.png 298 1136 media_image1.png Greyscale a second die with a second insulating material along at least one side surface of the second die, the second die directly bonded to the first die by way of a direct bonded interconnect, the second die including at least one contact directly bonded and in contact with the at least one contact of the pad layer without an intervening solder ball (Par. 0060, 0073, 0251-0265; Figs. 12C-12D – second die 110F.1; portion of 1210 that is above the previously defined first insulating material could be considered as the second insulating material; this prior art teaches that the attachment of second die to the first die could be through diffusion bonding); and at least one conductor through the first insulating material, the at least one conductor being in contact with the second die (Par. 0251-0265; Figs. 12C-12D – these Figs. show conductors through the first insulating material being in contact with the second die 110F.1). Regarding Claim 2, Wang et al., as applied to claim 1, discloses the apparatus, wherein the first die is a bridging die between the second die and a third die in a reconstituted form (Par. 0251-0265; Figs. 12C-12D – third die 110F.2). Regarding Claim 3, Wang et al., as applied to claim 1, discloses the apparatus, wherein the second die and a third die partially overlap a facing surface of the first die (Figs. 12C-12D). Regarding Claim 4, Wang et al., as applied to claim 1, discloses the apparatus, wherein the at least one conductor is a through- insulator via (Figs. 12C-12D – if BRI of the claim is made, this prior art teaches the conductor is a conductor through at least part of the first insulating material; i.e. the conductor is a through insulator via). Regarding Claim 5, Wang et al., as applied to claim 1, discloses the apparatus, wherein a redistribution layer couples the at least one conductor for electrical conductivity with the second die (Figs. 12C-12D – a portion of RDL 890 excluding the at least one conductor could be considered as the redistribution layer). Regarding Claim 6, Wang et al., as applied to claim 1, discloses the apparatus, wherein the second die comprises fine-pitch contacts (Par. 0059). Regarding Claim 9, Wang et al., as applied to claim 1, discloses the apparatus, wherein the first insulating material comprises a molding material (Par. 0132). Regarding Claim 10, Wang et al., as applied to claim 1, discloses the apparatus, wherein the at least one conductor comprises a via through the first insulating material (Figs. 12C-12D – if BRI of the claim is made, this prior art teaches the conductor is a conductor through at least part of the first insulating material; i.e. the conductor is a via through the first insulating material). Regarding Claim 11, Wang et al., as applied to claim 10, discloses the apparatus, wherein the first insulating material comprises an encapsulating material and the via extends through the encapsulating material (Par. 0132). Regarding Claim 12, Wang et al. discloses an apparatus, comprising: a first die at least partially surrounded by an insulating layer (Par. 0060, 0073, 0251-0265; Figs. 12C-12D – first die 110F.1; portion of 1210 that is surrounding the sidewall of the first die could be considered as the insulating layer); a second die adjacent to the first die (Par. 0251-0265; Figs. 12C-12D – second die 110F.2); and PNG media_image2.png 308 1122 media_image2.png Greyscale an active bridge die coupling the second die with the first die, and the active bridge die comprising active circuitry (Par. 0041; 0251-0265; Figs. 12C-12D – first die 110N). . Regarding Claim 13, Wang et al., as applied to claim 12, discloses the apparatus, wherein the active bridge die is coupled to the first die via direct bond interconnect (DBI) and the active bridge die is coupled to the second die via DBI (Par. 0060, 0073, 0251-0265; Figs. 12A-12D –this prior art teaches that the attachment of active bridge die to the first die and the second die could be through diffusion bonding). Regarding Claim 14, Wang et al., as applied to claim 12, discloses the apparatus, wherein the second die is at least partially surrounded by the insulating layer (Par. 0060, 0073, 0251-0265; Figs. 12A-12D). Regarding Claim 15, Wang et al., as applied to claim 12, discloses the apparatus, wherein the active bridge die is at least partially surrounded by an additional insulating layer (Par. 0251-0265; Figs. 12C-12D – lower portion of 1210 that is below the first die 110F.1 and the second die 110F.2 could be considered as the additional insulating layer). Regarding Claim 16, Wang et al., as applied to claim 15, discloses the apparatus, further comprising at least one conductor through the additional insulating layer, the at least one conductor being in contact with the first die or the second die (Par. 0251-0265; Figs. 12C-12D – these Figs. show conductors through the additional insulating layer being in contact with the first die 110F.1 and second die 110F.2). Regarding Claim 17, Wang et al., as applied to claim 16, discloses the apparatus, wherein a redistribution layer couples the at least one conductor for electrical conductivity with the first die or the second die (Figs. 12C-12D – a portion of RDL 890 excluding the at least one conductor could be considered as the redistribution layer). Regarding Claim 18, Wang et al., as applied to claim 16, discloses the apparatus, wherein the at least one conductor is a through-insulator via (Figs. 12C-12D – teaches under BRI of the claim – the conductor is a through insulator via through at least part of the first insulating material). Regarding Claim 19, Wang et al., as applied to claim 12, discloses the apparatus, wherein the first die and the second die partially overlap a facing surface of the active bridge die (Figs. 12C-12D). Regarding Claim 20, Wang et al., as applied to claim 12, discloses the apparatus, wherein the first die or the second die comprises fine-pitch contacts (Par. 0059). Regarding Claim 21, Wang et al., as applied to claim 12, discloses the apparatus, wherein the insulating layer comprises a molding material (Par. 0132). Regarding Claim 22, Wang et al. discloses an apparatus, comprising: a first die (Par. 0132-0138; Figs. 12A-12D – first die 110F.1); PNG media_image2.png 308 1122 media_image2.png Greyscale a second die adjacent to the first die (Par. 0132-0138; Figs. 12A-12D – second die 110F.2); and an active bridge die coupling the second die with the first die, and the active bridge die comprising active circuitry configured to actively perform at least one function (Par. 0041; 0132-0138; Figs. 12C-12D – active bridge 110N), wherein the active bridge die is coupled to the first die via direct bond interconnect (DBI) and the active bridge die is coupled to the second die via DBI (Par. 0060, 0073, 0132-0138; Figs. 12A-12D –this prior art teaches that the attachment of active bridge die to the first die and second die could be through diffusion bonding). Regarding Claim 23, Wang et al., as applied to claim 22, discloses the apparatus, wherein the first die is at least partially surrounded by a molding layer (Par. 0132; Fig. 12D – molding layer 1210). Regarding Claim 24, Wang et al., as applied to claim 22, discloses the apparatus, wherein the second die is at least partially surrounded by an insulating layer (Par. 0132; Fig. 12D – insulating layer 1210). Regarding Claim 25, Wang et al., as applied to claim 22, discloses the apparatus, wherein the active bridge die is at least partially surrounded by an additional insulating layer (Par. 0132; Fig. 12D – additional insulating layer 1210). Regarding Claim 26, Wang et al., as applied to claim 25, discloses the apparatus, further comprising at least one conductor through the additional insulating layer, the at least one conductor being in contact with the first die or the second die (Par. 0132-0138; Figs. 12C-12D – these Figs. show conductors through the additional insulating layer being in contact with the first die 110F.1 and second die 110F.2). Regarding Claim 27, Wang et al., as applied to claim 26, discloses the apparatus, wherein a redistribution layer couples the at least one conductor for electrical conductivity with the first die or the second die (Figs. 12C-12D – a portion of RDL 890 excluding the at least one conductor could be considered as comprising the redistribution layer). Regarding Claim 28, Wang et al., as applied to claim 26, discloses the apparatus, wherein the at least one conductor is a through-mold via (Figs. 12C-12D – teaches under BRI of the claim – the conductor is a through mold via through at least part of the molding layer 1210). Regarding Claim 29, Wang et al., as applied to claim 22, discloses the apparatus, wherein the first die and the second die partially overlap a facing surface of the active bridge die (Figs. 12C-12D). Regarding Claim 30, Wang et al., as applied to claim 22, discloses the apparatus, wherein the first die or the second die comprises fine-pitch contacts (Par. 0059). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 7 is rejected under 35 U.S.C. 103 as obvious over Wang et al. (US 20160071818 A), as applied to claim 6, further in view of Yu et al. (“Study of 15µm Pitch Solder Microbumps for 3D IC Integration” – 2009). Regarding Claim 7, Wang et al., as applied to claim 6, does not explicitly disclose the apparatus, wherein the fine-pitch contacts have a pitch of less than 20 microns However Yu et al., at least implicitly teaches the apparatus, wherein the fine-pitch contacts have a pitch of less than 20 microns (Pages 6-7). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Yu et al. to adapt the apparatus, wherein the fine-pitch contacts of Wang et al. have a pitch of less than 20 microns thereby enabling the die to be packed with a high level of functionalities Claim 8 is rejected under 35 U.S.C. 103 as obvious over Wang et al. (US 20160071818 A), as applied to claim 6, further in view of Enquist (“Direct Bond Interconnect for Advanced Packaging Applications” – 2007). Regarding Claim 8, Wang et al., as applied to claim 6, does not explicitly disclose the apparatus, wherein the fine-pitch contacts have a pitch of less than 10 microns. However Enquist, at least implicitly teaches the apparatus, wherein the fine-pitch contacts have a pitch of less than 10 microns (Page 11). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Enquist to adapt the apparatus, wherein the fine-pitch contacts of Wang et al. have a pitch of less than 10 microns thereby enabling the die to be packed with a high level of functionalities Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lin et al. (Pub. No.: US 2016/0343685 A1) – This prior art is particularly relevant as its teaches two upper level dies bonded to a lower level bridge die; it further teaches a plurality of conductors through an insulator later, wherein the conductors are electrically coupled to the upper level dies; the insulator layer surrounding the bridge die (see Figs. 4-5). Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 03/03/2026 /SYED I GHEYAS/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Sep 14, 2023
Application Filed
Mar 05, 2026
Non-Final Rejection — §102, §103, §DP
Mar 23, 2026
Applicant Interview (Telephonic)
Mar 29, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
87%
With Interview (+4.8%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 666 resolved cases by this examiner. Grant probability derived from career allow rate.

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