DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant' s Amendment filed on 03/13/2026. Claims 1, 4, 6, and 13 have been amended. No new claims have been added. Claims 2 and 3 have been canceled. Currently, claims 1, 4-20 are pending.
Response to Arguments
Applicant's arguments with respect to claims 1 and 13 filed on 03/13/2026 have been fully considered but they are not persuasive. The reason is set forth below.
Regarding amended claim 1, Remarks document page 7, applicant stated “Park does not appear to disclose the features now recited in claims 1 and 13. Applicant respectfully submits that the remaining cited references do not appear to cure the deficiencies of Park to teach or suggest the abovementioned features of claims 1 and 13. Accordingly, it appears that the references, whether taken alone or in combination, fail to disclose the features now recited in amended claims 1 and 13.”
However, CHO et al. ¶ [0056] discloses, “The first power voltage line 10 may be connected to a pad 56 of the pad portion 50”. Furthermore, Park et al. ¶ [0127] discloses, “third conductive line 50a and the fourth conductive line 50b may extend in the first direction D1”. Furthermore, Park et al. Fig. 7 shows conductive line 50 is extended in directions D1 and D2 and spaced apart. Therefore, the current prior arts of record CHO, Seunghwan (US 20210305351 A1) “CHO et al.” in view of Park, Hyungjun (US 20200176540 A1) “Park et al.”. still read on the amended claim 1 and 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 1, 4-5, 8-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over CHO, Seunghwan (US 20210305351 A1) “CHO et al.” in view of Park, Hyungjun (US 20200176540 A1) “Park et al.”.
Regarding Independent Claim 1, CHO et al. Figs. 1-11 discloses a display apparatus (“a display device” ¶ [0049]) comprising:
a substrate (“a substrate 110” ¶ [0053]) comprising a display area (“a display area DA” ¶ [0053]) configured to display an image using a pixel (“A plurality of pixels PX are included at (e.g., in or on) the display area DA to display an image.” ¶ [0053]), and a peripheral area (“a peripheral area PA” ¶ [0053]) at least partially surrounding the display area (“a peripheral area PA surrounding (e.g., around a periphery of) the display area DA” ¶ [0053]);
a pad portion (“a pad portion 50” ¶ [0055]) in the peripheral area (“a pad portion 50 may be arranged at (e.g., in or on) the peripheral area PA” ¶ [0055]), and comprising pads (“pad portion 50 is arranged at (e.g., in or on) the peripheral area PA, and includes a plurality of pads 51, 52, 53, 54, 55, and 56.” ¶ [0061]);
a first power voltage line (“A first power voltage line 10” ¶ [0055]) between the display area and the pad portion in plan view (Fig. 1 shows 10 is between the DA and 50), and
a fan-out wire portion (“a fan-out wire portion 60” ¶ [0061]) connected between the pad portion and the display area (“The pad portion 50 may be connected to a fan-out wire portion 60 including a plurality of fan-out wires 61, 62, 63 (e.g., see FIGS. 3), 64, 65, and 66 to transmit the voltages and the various signals to the display area DA.” ¶ [0061]), and overlapping at least a portion of the first power patterns (“A conductive layer may be between an upper portion of the fan-out wire portion and a lower portion of the pad portion, and may at least partially correspond to an overlapping area of the fan-out wire portion and the pad portion” ¶ [0049]),
wherein the fan-out wire portion comprises a first fan-out wire, a second fan-out wire, and a third fan-out wire (“a fan-out wire portion 60 including a plurality of fan-out wires 61, 62, 63” ¶ [0061]), the second fan-out wire being at a different layer from the first fan-out wire, and the third fan-out wire being at a different layer from the first fan-out wire and from the second fan-out wire (“the fan-out wires 61, 62, and 63 of the fan-out wire portion 60 may be arranged at (e.g., in or on) different layers from each other. ” ¶ [0090]), wherein the first power patterns comprise a first connection line connected to the pad portion (“The first power voltage line 10 may be connected to a pad 56 of the pad portion 50.” ¶ [0056]).
However, CHO et al. does not disclose, a first power voltage line comprising first power patterns spaced apart from each other; and a fan-out wire portion overlapping at least a portion of the first power patterns and wherein the first power patterns are arranged in a first direction.
In the similar field of endeavor of display devices, Park et al. Figs. 5-18 discloses a first power voltage line (“power supply portion 50 having a multi-line structure” ¶ [0125]) comprising first power patterns spaced apart from each other (“power supply portion 50 may include a third conductive line 50a, a fourth conductive line 50b” ¶ [0129]); and a fan-out wire portion overlapping at least a portion of the first power patterns (“power supply portion 50 may overlap the fan-out portion 20.” ¶ [0149]) and wherein the first power patterns are arranged in a first direction (“third conductive line 50a and the fourth conductive line 50b may extend in the first direction D1” ¶ [0127]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of Park et al. so that heat of wires may be effectively distributed and dissipated. Advantageously, luminous uniformity of the display unit may be optimized. The multi-line structure of the first power supply portion and the oblique sections of the fan-out portion may advantageously enable minimization of a width of the non-display area NDA (Park et al. [0123]).
Regarding Claim 4, CHO et al. as modified by Park et al. discloses the limitations of claim 1. However, CHO et al. does not disclose, further comprising: a third power voltage line extending in the first direction between the display area and the first power voltage line; and a third connection line connected to the third power voltage line, and extending in a second direction between the first power patterns.
In the similar field of endeavor of display devices, Park et al. Figs. 5-18 discloses further comprising: a third power voltage line (“power supply portion 40 having a multi-line structure” ¶ [0113]) extending in the first direction (“ first conductive line 40a and the second conductive line 40b may extend in a first direction D1” ¶ [0115]) between the display area DA and the first power voltage line 50 (Fig. 7 shows 40 is between DA and 50); and a third connection line connected (“first connection line 40c1 and the second connection line 40c2 may extend in the second direction D2 different from the first direction D1” ¶ [0116]) to the third power voltage line 40, and extending in a second direction between the first power patterns (“first connection line 40c1 and the second connection line 40c2 may extend in the second direction D2 different from the first direction D1” ¶ [0116]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of Park et al. so that heat of wires may be effectively distributed and dissipated. Advantageously, luminous uniformity of the display unit may be optimized. The multi-line structure of the first power supply portion and the oblique sections of the fan-out portion may advantageously enable minimization of a width of the non-display area NDA (Park et al. [0158]).
Regarding Claim 5, CHO et al. as modified by Park et al. discloses the limitations of claim 4. However, CHO et al. does not disclose, further comprising: wherein the third connection line and the first power patterns are at a same layer.
In the similar field of endeavor of display devices, Park et al. Figs. 5-18 discloses wherein the third connection line and the first power patterns are at a same layer (“connection line 40c1 may be positioned in the bending area BA and may extend into the first non-display area NDA1 and the second non-display area NDA2” ¶ [0128]; “The third conductive line 50a may be positioned in the first non-display area NDA1, and the fourth conductive line 50b may be positioned in the second non-display area NDA2.” ¶ [0130]; therefore, 40c1 and 50a and 50b are in same layer NDA2).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of Park et al. so that heat of wires may be effectively distributed and dissipated. Advantageously, luminous uniformity of the display unit may be optimized. The multi-line structure of the first power supply portion and the oblique sections of the fan-out portion may advantageously enable minimization of a width of the non-display area NDA (Park et al. [0158]).
Regarding Claim 8, CHO et al. as modified by Park et al. discloses the limitations of claim 1. CHO et al. Figs. 1-12 further discloses, further comprising: a transistor (“A first thin film transistor T1” ¶ [0106]) and a storage capacitor (“storage capacitor Cst” ¶ [0111]) in the display area, the transistor comprising a semiconductor layer (“a semiconductor layer A1” ¶ [0106]), a gate electrode (“a gate electrode G1” ¶ [0106]), a source electrode (“a source electrode S1” ¶ [0106]), and a drain electrode (“a drain electrode D1” ¶ [0106]), and the storage capacitor Cst comprising a first electrode (“A first electrode CE1” ¶ [0111]) and a second electrode (“A second electrode CE2” ¶ [0112]); and
a driving voltage line (“A plurality of driving voltage lines PL configured to transmit driving voltages to the plurality of pixels PX arranged at (e.g., in or on) the display area DA” ¶ [0056]) above the transistor in the display area, and connected to the first power voltage line (“A plurality of driving voltage lines PL configured to transmit driving voltages to the plurality of pixels PX arranged at (e.g., in or on) the display area DA may be connected to the first power voltage line 10.” ¶ [0056]).
Regarding Claim 9, CHO et al. as modified by Park et al. discloses the limitations of claim 8. CHO et al. Figs. 5-12 further discloses, wherein the first power patterns and the driving voltage line are at a same layer (Fig. 2A shows ELVDD and PL are in the same layer).
However, CHO et al. does not disclose, wherein the first fan-out wire and the source electrode are at a same layer.
In the similar field of endeavor of display devices, Park et al. Figs. 5-18 discloses wherein the first fan-out wire (“first fan-out portion 21 may include a plurality of first conductive lines CL1. The plurality of first conductive lines CL1 may include n first conductive lines including a conductive line CL1-1 through a conductive line CL1-n” ¶ [0111]) and the source electrode are at a same layer (Fig. 13 shows CL2c is in the same layer as source 215a).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of Park et al. so that heat of wires may be effectively distributed and dissipated. Advantageously, luminous uniformity of the display unit may be optimized. The multi-line structure of the first power supply portion and the oblique sections of the fan-out portion may advantageously enable minimization of a width of the non-display area NDA (Park et al. [0158]).
Regarding Claim 10, CHO et al. as modified by Park et al. discloses the limitations of claim 9. CHO et al. Figs. 5-12 further discloses, wherein the second fan-out wire 61 and the first electrode CE1are at a same layer (Fig. 10 shows fan-out wire 61 is in the same layer as CE1), and wherein the third fan-out wire 62 and the second electrode CE2 are at a same layer (Fig. 10 shows fan-out wire 62 is in the same layer as CE2).
Regarding Claim 11, CHO et al. as modified by Park et al. discloses the limitations of claim 1. CHO et al. Figs. 1-12 further discloses, further comprising a second power voltage line (“a second power voltage line 20” ¶ [0055]) partially overlapping the fan-out wire portion (Fig. 1 shows fan-out portions partially overlaps second power voltage line 20), the second power voltage line and the first power patterns being at a same layer (“ A first power voltage line 10 and a second power voltage line 20 configured to apply different power voltages from each other may be arranged at (e.g., in or on) the peripheral area PA.” ¶ [0055]).
Regarding Claim 12, CHO et al. as modified by Park et al. discloses the limitations of claim 1. CHO et al. Figs. 1-12 further discloses, further comprising an organic light-emitting element (“At (e.g., in or on) the display area DA of the substrate 110, the organic light-emitting diode 300” ¶ [0116]) in the display area, and comprising a pixel electrode (“pixel electrode 310” ¶ [0116]), an intermediate layer comprising an organic emission layer (“an intermediate layer 320 including an organic emission layer” ¶ [0116]), and an opposite electrode (“an opposite electrode 330” ¶ [0116]).
Regarding Claim 13, CHO et al. Figs. 1-11 discloses a display apparatus comprising:
a substrate (“a substrate 110” ¶ [0053]) comprising a display area (“a display area DA” ¶ [0053]) configured to display an image using a pixel (“A plurality of pixels PX are included at (e.g., in or on) the display area DA to display an image.” ¶ [0053]), and a peripheral area (“a peripheral area PA” ¶ [0053]) at least partially surrounding the display area (“a peripheral area PA surrounding (e.g., around a periphery of) the display area DA” ¶ [0053]);
a pad portion (“a pad portion 50” ¶ [0055]) in the peripheral area (“a pad portion 50 may be arranged at (e.g., in or on) the peripheral area PA” ¶ [0055]), and comprising pads (“pad portion 50 is arranged at (e.g., in or on) the peripheral area PA, and includes a plurality of pads 51, 52, 53, 54, 55, and 56.” ¶ [0061]);
a first power voltage line (“A first power voltage line 10” ¶ [0055]) in the peripheral area (“The first power voltage line 10 may be arranged at (e.g., in or on) the peripheral area PA” ¶ [0056]), and respectively connected to the pad portion through first connection lines (“The first power voltage line 10 may be connected to a pad 56 of the pad portion 50” ¶ [0056]);
a driving voltage line (“A plurality of driving voltage lines PL” ¶ [0056]) electrically connected to the first power voltage line (“A plurality of driving voltage lines PL configured to transmit driving voltages to the plurality of pixels PX arranged at (e.g., in or on) the display area DA may be connected to the first power voltage line 10.” ¶ [0056]), and extending to the display area (“A plurality of driving voltage lines PL configured to transmit driving voltages to the plurality of pixels PX arranged at (e.g., in or on) the display area DA” ¶ [0056]);
However, CHO et al. does not disclose, a first power voltage line comprising first power patterns arranged in a first direction, a third power voltage line extending in the first direction in the peripheral area; and a third connection line connecting the third power voltage line to the pad portion, crossing between the first power patterns, and at a same layer as the first power patterns.
In the similar field of endeavor of display devices, Park et al. Figs. 5-18 discloses a first power voltage line (“power supply portion 50 having a multi-line structure” ¶ [0125]) comprising first power patterns (“power supply portion 50 may include a third conductive line 50a, a fourth conductive line 50b” ¶ [0129]); a third power voltage line (“power supply portion 40 having a multi-line structure” ¶ [0113]) extending in a first direction (“ first conductive line 40a and the second conductive line 40b may extend in a first direction D1” ¶ [0115]) between the display area DA and the first power voltage line 50 (Fig. 7 shows 40 is between DA and 50); and a third connection line connected (“first connection line 40c1 and the second connection line 40c2 may extend in the second direction D2 different from the first direction D1” ¶ [0116]) to the third power voltage line 40, and extending in a second direction between the first power patterns (“first connection line 40c1 and the second connection line 40c2 may extend in the second direction D2 different from the first direction D1” ¶ [0116]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of Park et al. so that heat of wires may be effectively distributed and dissipated. Advantageously, luminous uniformity of the display unit may be optimized. The multi-line structure of the first power supply portion and the oblique sections of the fan-out portion may advantageously enable minimization of a width of the non-display area NDA (Park et al. [0158]).
Regarding Claim 14, CHO et al. as modified by Park et al. discloses the limitations of claim 13. CHO et al. further discloses, a first fan-out wire extending from the pad portion to the display area (“a fan-out wire portion 60 including a plurality of fan-out wires 61, 62, 63” ¶ [0061]), and overlapping at least a portion of the first power patterns (“A conductive layer may be between an upper portion of the fan-out wire portion and a lower portion of the pad portion, and may at least partially correspond to an overlapping area of the fan-out wire portion and the pad portion” ¶ [0049]).
Regarding Claim 15, CHO et al. as modified by Park et al. discloses the limitations of claim 14. CHO et al. further discloses, further comprising a transistor (“A first thin film transistor T1” ¶ [0106]) in the display area, and comprising a semiconductor layer (“a semiconductor layer A1” ¶ [0106]), a gate electrode (“a gate electrode G1” ¶ [0106]), a source electrode (“a source electrode S1” ¶ [0106]), and a drain electrode (“a drain electrode D1” ¶ [0106]).
However, CHO et al. does not disclose, wherein the first fan-out wire and the source electrode are at a same layer.
In the similar field of endeavor of display devices, Park et al. Figs. 5-18 discloses wherein the first fan-out wire (“first fan-out portion 21 may include a plurality of first conductive lines CL1. The plurality of first conductive lines CL1 may include n first conductive lines including a conductive line CL1-1 through a conductive line CL1-n” ¶ [0111]) and the source electrode are at a same layer (Fig. 13 shows CL2c is in the same layer as source 215a).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of Park et al. so that heat of wires may be effectively distributed and dissipated. Advantageously, luminous uniformity of the display unit may be optimized. The multi-line structure of the first power supply portion and the oblique sections of the fan-out portion may advantageously enable minimization of a width of the non-display area NDA (Park et al. [0158]).
Regarding Claim 16, CHO et al. as modified by Park et al. discloses the limitations of claim 15. CHO et al. further discloses, further comprising a second power voltage line (“a second power voltage line 20” ¶ [0055]) partially overlapping the first fan-out wire (Fig. 1 shows fan-out portions partially overlaps second power voltage line 20), and at a same layer as the first power patterns (“ A first power voltage line 10 and a second power voltage line 20 configured to apply different power voltages from each other may be arranged at (e.g., in or on) the peripheral area PA.” ¶ [0055]).
Regarding Claim 20, CHO et al. as modified by Park et al. discloses the limitations of claim 13. CHO et al. Figs. 1-12 further discloses, further comprising an organic light-emitting element (“At (e.g., in or on) the display area DA of the substrate 110, the organic light-emitting diode 300” ¶ [0116]) in the display area, and comprising a pixel electrode (“pixel electrode 310” ¶ [0116]), an intermediate layer comprising an organic emission layer (“an intermediate layer 320 including an organic emission layer” ¶ [0116]), and an opposite electrode (“an opposite electrode 330” ¶ [0116]).
Claims 6-7 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over CHO, Seunghwan (US 20210305351 A1) “CHO et al.” in view of Park, Hyungjun (US 20200176540 A1) “Park et al.” further in view of KIM, Dong-Gyu (US 20110085100 A1) “KIM et al.”.
Regarding Claim 6, CHO et al. as modified by Park et al. discloses the limitations of claim 1. However, CHO et al. does not disclose, further comprising a first power sub-line extending in the first direction between the first power voltage line and the display area, wherein the first power sub-line is electrically connected to at least one of the first power patterns.
In the similar field of endeavor of display devices, KIM et al. Figs. 1-2 discloses further comprising a first power sub-line (“power line 1051a” ¶ [0104]) extending in the first direction between the first power voltage line (“power line 1052b” ¶ [0105]) and the display area, wherein the first power sub-line is electrically connected to at least one of the first power patterns (“The first power line 1051a is electrically connected to a fourth power line 1052b” ¶ [0105]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of KIM et al. so that a first voltage and a second voltage are uniformly applied to a display area without a delay. Thus, a reduction of a charge rate generated at one side of the display area may be prevented (KIM et al. ¶ [0060]).
Regarding Claim 7, CHO et al. as modified by Park et al. and KIM et al. discloses the limitations of claim 6. However, CHO et al. does not disclose, wherein the first power sub-line is at a different layer from the first power patterns.
In the similar field of endeavor of display devices, KIM et al. Figs. 1-2 discloses wherein the first power sub-line is at a different layer from the first power patterns (Fig. 2 shows the first power sub-line 1051a is at a different layer from the first power patterns 1052b).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of KIM et al. so that a first voltage and a second voltage are uniformly applied to a display area without a delay. Thus, a reduction of a charge rate generated at one side of the display area may be prevented (KIM et al. ¶ [0060]).
Regarding Claim 17, CHO et al. as modified by Park et al. discloses the limitations of claim 13. However, CHO et al. does not disclose, further comprising a first power sub-line extending in a first direction between the first power voltage line and the display area, wherein the first power sub-line is electrically connected to at least one of the first power patterns.
In the similar field of endeavor of display devices, KIM et al. Figs. 1-2 discloses further comprising a first power sub-line (“power line 1051a” ¶ [0104]) extending in a first direction between the first power voltage line (“power line 1052b” ¶ [0105]) and the display area, wherein the first power sub-line is electrically connected to at least one of the first power patterns (“The first power line 1051a is electrically connected to a fourth power line 1052b” ¶ [0105]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of KIM et al. so that a first voltage and a second voltage are uniformly applied to a display area without a delay. Thus, a reduction of a charge rate generated at one side of the display area may be prevented (KIM et al. ¶ [0060]).
Regarding Claim 18, CHO et al. as modified by Park et al. and KIM et al. discloses the limitations of claim 17. However, CHO et al. does not disclose, wherein the first power sub-line is connected to the driving voltage line.
In the similar field of endeavor of display devices, KIM et al. Figs. 1-2 discloses wherein the first power sub-line is connected to the driving voltage line (“the power wire 1050 extending from the data driving chips 1031 may be disposed to be electrically connected to the gate driving chip 1011.” ¶ [0102]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of KIM et al. so that a first voltage and a second voltage are uniformly applied to a display area without a delay. Thus, a reduction of a charge rate generated at one side of the display area may be prevented (KIM et al. ¶ [0060]).
Regarding Claim 19, CHO et al. as modified by Park et al. and KIM et al. discloses the limitations of claim 17. However, CHO et al. does not disclose, wherein the first power sub-line is at a different layer from the first power patterns.
In the similar field of endeavor of display devices, KIM et al. Figs. 1-2 discloses wherein the first power sub-line is at a different layer from the first power patterns (Fig. 2 shows the first power sub-line 1051a is at a different layer from the first power patterns 1052b).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify first power voltage line of CHO et al. using the first power voltage line of KIM et al. so that a first voltage and a second voltage are uniformly applied to a display area without a delay. Thus, a reduction of a charge rate generated at one side of the display area may be prevented (KIM et al. ¶ [0060]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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