Prosecution Insights
Last updated: April 19, 2026
Application No. 18/467,650

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Sep 14, 2023
Examiner
PARK, SAMUEL
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
388 granted / 461 resolved
+16.2% vs TC avg
Strong +26% interview lift
Without
With
+25.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
24 currently pending
Career history
485
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
53.2%
+13.2% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
21.3%
-18.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 461 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Note by the Examiner 2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis. Election/Restrictions 3. Applicant’s election without traverse of Invention II, identified as encompassing claims 16-35 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 4. Claims 21-22 and 26-32 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Chen et al. (US 2021/0343600 A1), hereinafter as C1 PNG media_image1.png 762 774 media_image1.png Greyscale 5. Regarding Claim 21, C1 discloses a method for manufacturing a semiconductor device (see in particular Figs. 1-29D, “Labeled Fig. 29D” above, and [0015] “fragmentary perspective views of a multigate device 200, in portion or entirety, at various fabrication stages (such as those associated with method 100 in FIG. 1)”), comprising: forming a gate structure (element 384, see [0050] “gate electrode 384”) across a first channel region (element 220’ of 202A, see [0051] “channel layers 220’” and [0058] “n-type transistor region 202A”) and a second channel region (element 220’ of 202B, see [0058] “p-type transistor region 202B”); forming a first source/drain epitaxial structure (element 320A of 202A, see [0058] “epitaxial source/drain features 320A”) on a side of the first channel region (see Figs. 29A-D); forming a second source/drain epitaxial structure (element 320B of 202B, see [0058] “epitaxial source/drain features 320B”) on a side of the second channel region (see Figs. 29A-D); forming contact etch stop layer (element 332, 272, see in particular Fig. 20, see [0042] “contact etch stop layer (CESL) 332” and [0045] “dielectric liner 272”) surrounding the first source/drain epitaxial structure and the second source/drain epitaxial structure (see in particular Fig. 20, 29D), wherein a first portion of the contact etch stop layer over the first source/drain epitaxial structure is thicker than a second portion of the contact etch stop layer over the second source/drain epitaxial structure (see “Labeled Fig. 29D” above); and forming an interlayer dielectric layer (element 330, see [0045] “ILD layer 330”) over the contact etch stop layer. 6. Regarding Claim 22, C1 discloses the method of claim 21, wherein the first source/drain epitaxial structure and the second source/drain epitaxial structure are of opposite conductive types (see [0058] n-type versus p-type). 7. Regarding Claim 26, C1 discloses the method of claim 21, wherein the contact etch stop layer comprises a plurality of dielectric layers (elements 332 and 272), and a number of the dielectric layers in the first portion of the contact etch stop layer (both elements 332 and 272 are in the labeled element “First Portion”) is greater than a number of the dielectric layers in the second portion of the contact etch stop layer (only the element 332 is in the labeled element “Second Portion”). 8. Regarding Claim 27, C1 discloses the method of claim 21, wherein at least two of the dielectric layers comprises different dielectric materials (see [0042] “CESL 332 can include silicon and nitride, such as silicon nitride or silicon oxynitride” and [0031] “dielectric liner 272 includes … silicon oxycarbonitride”). PNG media_image2.png 762 774 media_image2.png Greyscale 9. Regarding Claim 28, C1 discloses the method of claim 21, wherein a third portion (see labeled element “Third Portion” above) of the contact etch stop layer at a sidewall (right sidewall) of the first source/drain epitaxial structure is thinner than the first portion of the contact etch stop layer over the first source/drain epitaxial structure (see “Labeled Fig. 29D” above). 10. Regarding Claim 29, C1 discloses a method for manufacturing a semiconductor device (see in particular Figs. 1-29D, “Labeled Fig. 29D” above, and [0015] “fragmentary perspective views of a multigate device 200, in portion or entirety, at various fabrication stages (such as those associated with method 100 in FIG. 1)”), comprising: forming a gate structure (element 384, see [0050] “gate electrode 384”) across a channel region (element 220’ of 202A, see [0051] “channel layers 220’” and [0058] “n-type transistor region 202A”); forming a source/drain epitaxial structure (element 320A of 202A, see [0058] “epitaxial source/drain features 320A”) on a side of the channel region (see Figs. 29A-D); forming a contact etch stop layer (element 332, 272, see in particular Fig. 20, see [0042] “contact etch stop layer (CESL) 332” and [0045] “dielectric liner 272”) surrounding the source/drain epitaxial structure (see in particular Figs. 20, 29D), comprising: forming a first dielectric layer (element 332 portion) at a top of the source/drain epitaxial structure, wherein at least a lower portion of a sidewall of the source/drain epitaxial structure is free of the first dielectric layer (see in particular Figs. 20, 29D); and forming a second dielectric layer (element 277 portion) at the top (note, the manner in which the claim is currently recited does not require the second dielectric layer to be above the top, and broadly requires “at” which is interpreted to mean “proximate” and is disclosed by the element 277 portion) and the sidewall of the source/drain epitaxial structure and over the first dielectric layer (see in particular Figs. 20, 29D); and forming an interlayer dielectric layer (element 330, see [0045] “ILD layer 330”) over the contact etch stop layer (see in particular Figs. 20, 29D). 11. Regarding Claim 30, C1 discloses the method of claim 29, wherein an oxygen concentration of the second dielectric layer is greater than that of the first dielectric layer (see [0042] “CESL 332 can include silicon and nitride, such as silicon nitride or silicon oxynitride” First dielectric selected as silicon nitride and [0031] “dielectric liner 272 includes … silicon oxycarbonitride” second dielectric selected as silicon oxynitride). 12. Regarding Claim 31, C1 discloses the method of claim 29, wherein the first dielectric layer is further at an upper portion of the sidewall of the source/drain epitaxial structure (see in particular Figs. 20, 29D). 13. Regarding Claim 32, C1 discloses the method of claim 29, wherein an upper portion of the sidewall of the source/drain epitaxial structure is free of the first dielectric layer (see in particular Figs. 20, 29D). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 14. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0343600 A1), hereinafter as C1, in view of Basker et al. (US 2016/0099342 A1), hereinafter as B1 15. Regarding Claim 23, C1 discloses the method of claim 21, further comprising: forming a first source/drain contact (first element 400 over the first source/drain epitaxial structure, see [0057] “source/drain contacts 400”) over the first source/drain epitaxial structure (see Fig. 29D); and forming a second source/drain contact over the second source/drain epitaxial structure (second element 400 over the second source/drain, see [0057] and Fig. 29D). C1 discloses wherein a height of the second source/drain contact is greater than a height of the first source/drain contact. B1 discloses wherein a height of the second source/drain contact is greater than a height of the first source/drain contact (see Fig. 10 height of element 54a is greater than a height of element 54b). The height difference between the two source/drain contacts as taught by B1 is incorporated with C1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of B1 with C1 because the combination allows for accommodation of different source/drain contacts for the n-type device region versus the p-type device region adjusting contact area and stresses (see B1 [0070-0071]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known source/drain contacts for another in a similar device to obtain predictable results (see B1 Fig. 10). 16. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0343600 A1), hereinafter as C1, in view of Basker et al. (US 2016/0099342 A1), hereinafter as B1, in view of Cheng et al. (US 2020/0052091 A1), hereinafter as C2 17. Regarding Claim 24, C1, B1 disclose the method of claim 23. C1, B1 do not disclose further comprising: forming a first dielectric liner between the first source/drain contact and the interlayer dielectric layer; and forming a second dielectric liner between the second source/drain contact and the interlayer dielectric layer, wherein a bottom end of the first dielectric liner is higher than a bottom end of the second dielectric liner. C2 discloses (see Fig. 1A-D) further comprising: forming a first dielectric liner (element 70 of a first element 50, see [0090] “interlayer dielectric (ILD) layer 70”) between the first source/drain contact (first element 75 over a first element 50, see [0091] “source/drain epitaxial layers 50 and 55” and [0100] “conductive contact plug 75”) and the interlayer dielectric layer (element 40, see [0040] “spacers 40”); and forming a second dielectric liner (element 70 of a second element 75 over a second element 50) between the second source/drain contact and the interlayer dielectric layer (see Fig. 1A-D). The first and second dielectric liners as taught by C2 are incorporated as first and second dielectric liners of C1, the combination further discloses wherein a bottom end of the first dielectric liner is higher than a bottom end of the second dielectric liner (see B1 Fig. 10, the combination has a taller height and lower extending bottom end of the second source/drain contact such that the second dielectric liner has a bottom end lower than the first dielectric liner). The dielectric liners as taught by C2 is incorporated as dielectric liners of C1,B1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C2 with C1,B1 because the combination allows for controlled thicknesses and protection during formation and for the resulting source/drain contact elements (see [0083-0084]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known source/drain contacts sidewall for another in a similar device to obtain predictable results (see C2 Fig. 1). 18. Claims 33 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0343600 A1), hereinafter as C1, in view of Cheng et al. (US 2020/0052091 A1), hereinafter as C2 19. Regarding Claim 33, C1 discloses the method of claim 29, further comprising: forming a source/drain contact (first element 400 over the first source/drain epitaxial structure, see [0057] “source/drain contacts 400”) over the source/drain epitaxial structure (see Fig. 29D). C1 does not disclose forming a dielectric liner between the source/drain contact and the interlayer dielectric layer, wherein a bottom end of the dielectric liner is in contact with the first dielectric layer. C2 discloses (see Fig. 1A-D) forming a dielectric liner (element 70 of a first element 50, see [0090] “interlayer dielectric (ILD) layer 70”) between the source/drain contact (first element 75 over a first element 50, see [0091] “source/drain epitaxial layers 50 and 55” and [0100] “conductive contact plug 75”) and the interlayer dielectric layer (element 40, see [0040] “spacers 40”). The dielectric liner as taught by C2 is incorporated as a dielectric liner of C1, the combination further discloses wherein a bottom end of the dielectric liner is in contact with the first dielectric layer (see C1 Fig. 20, 29D the bottom end as currently recited is broadly recited such that an outer surface portion of the bottom end is in contact with the first dielectric layer element 332 – the claim does not require the bottom surface to be in contact). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C2 with C1,B1 because the combination allows for controlled thicknesses and protection during formation and for the resulting source/drain contact elements (see [0083-0084]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known source/drain contacts sidewall for another in a similar device to obtain predictable results (see C2 Fig. 1). 20. Regarding Claim 35, C1 discloses the method of claim 29, wherein the source/drain epitaxial structure is an p-type feature (see [0041] “Epitaxial source/drain features 320A, 320B are doped with n-type dopants and/or p-type dopants” Selected as the p-type doped feature). Allowable Subject Matter 21. Claims 16-20 are allowed. Claims 25 and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reason for indicating allowable subject matter: The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of: 22. Claim 16, “epitaxially growing a first source/drain epitaxial structure on a side of the first channel region; depositing a dielectric film; patterning the dielectric film into at least a first contact etch stop layer over the first source/drain epitaxial structure; after patterning the dielectric film into the first contact etch stop layer, epitaxially growing a second source/drain epitaxial structure on a side of the second channel region; depositing a second contact etch stop layer over the first contact etch stop layer and the second source/drain epitaxial structure; depositing an interlayer dielectric layer over the second contact etch stop layer; and forming a first source/drain contact and a second source/drain contact in the interlayer dielectric layer and respectively over the first source/drain epitaxial structure and the second source/drain epitaxial structure” – as instantly claimed and in combination with the additionally claimed limitations. All claims depending on the current claim incorporate the same allowable subject matter. 23. Claim 25, “wherein the isolation layer is below the second source/drain epitaxial structure, and the isolation layer comprises a dielectric material the same as a layer of the contact etch stop layer” – as instantly claimed and in combination with the additionally claimed limitations. 24. Claim 34, “forming a third dielectric layer at the top and the sidewall of the source/drain epitaxial structure and below the first dielectric layer, wherein the third dielectric layer comprises a dielectric material different from that of the first dielectric layer” – as instantly claimed and in combination with the additionally claimed limitations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL PARK/Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Sep 14, 2023
Application Filed
Feb 28, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+25.7%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 461 resolved cases by this examiner. Grant probability derived from career allow rate.

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