DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Amendment and Response to Office Action , received 02/23/2026, has been entered
Claims 1-20 are presented for examination
Priority
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 5, 7-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ting-You Lin et al. (US 10692969 B1) herein after referred to as “Lin” in view of Patrick M Shea (US 20090283826 A1) herein after referred to as “Shea”
Regarding claim 1, Lin teaches:
A transistor structure, comprising:
a substrate; (Fig. 9 element 800)
a first well region element (705 with 802) and a second well region (702), located in the substrate (800) and adjacent to each other; (Fig. 9 elements 705, 802, 702, 800)
a gate structure (G2), located on the substrate; (Fig. 9 element G2)
a drift region (703), located in the second well region on one side of the gate structure ; (Fig. 9 element 703)
a first doped region (706) and a second doped region (704), located in the substrate on two sides of the gate structure, wherein the first doped region is located in the first well region, and the second doped region is located in the drift region; and (Fig. 9 element 706 and 704) Column 11 lines 34-47
a first isolation structure (804), located in the substrate between the gate structure (G2) and the second doped region (704), wherein (Fig. 9 element 804 Column 15 lines 33-55 )
the first well region has a first portion lower than a bottom surface of the drift region, (Fig. 9 element 802 is lower than 703)
the second well region has a second portion lower than the bottom surface of the drift region, and (Fig. 9 portions of element 702 are lower than 703)
Lin discusses the dopant concentration in the well regions, but not that a doping concentration of the first portion of the first well region is greater than a doping concentration of the second portion of the second well region.
Shea teaches:
a doping concentration of the first portion of the first well region is greater than a doping concentration of the second portion of the second well region. (Para. [0080][0052] Fig 9. Element 49 [since placing a highly doped area in to that portion of the well region thusly makes it of higher concentration compared to the second well.])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lin as taught by Shea such that the a doping concentration of the first portion of the first well region is greater than a doping concentration of the second portion of the second well region, because Shea teaches that it is known that electrical conductivity can be manipulated through the process of doping and thus a high doping concentration displaced far enough away from the gate region such that the threshold voltage of the device is not significantly affected, and since the region is also connected to the source, it lowers the base resistance of the semiconductor. (Para.[0005],[0006],[0080],[0052] Fig 9. Element 49).
Regarding claim 2, Lin in view of Shea teach:
The transistor structure according to claim 1,
Lin further teaches:
wherein the first well region has a third portion lower than a bottom surface of the first isolation structure, (Fig. 9 element 802 is lower than 804 [where 802 may contain the first and third portions of the first well (705 and 802)])
the second well region has a fourth portion lower than the bottom surface of the first isolation structure, (Fig. 9 element 702 is lower than 804 [where 702 may contain the second and fourth portions of the second well])
Lin as modified by Shea above teaches that a doping concentration of the third portion of the first well region is greater than a doping concentration of the fourth portion of the second well region.
Shea teaches:
and a doping concentration of the third portion of the first well region is greater than a doping concentration of the fourth portion of the second well region. (Para. [0080][0052] Fig 9. Element 49)
Regarding Claim 5, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin further teaches:
wherein the bottom surface of the drift region is lower than a bottom surface of the first isolation structure, and the drift region surrounds the first isolation structure. (Fig 9 element 703 lower than and surrounds 804)
Regarding Claim 7, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin further teaches:
wherein a part of the first well region is located directly below the gate structure. (Fig. 9 element 705 below G2)
Regarding Claim 8, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin further teaches:
wherein a part of the second well region is located directly below the gate structure. (Fig. 9 element 702 below G2)
Regarding Claim 9, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin further teaches:
wherein a part of the drift region is located directly below the gate structure. (Fig. 9 element 703 below G2)
Regarding Claim 10, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin further teaches:
wherein a part of the first isolation structure is located directly below the gate structure. (Fig.9 element 804 below G2)
Regarding Claim 11, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin further teaches:
wherein the gate structure comprises: a gate, located on the substrate; and (Fig. 9 element 806 Column 15-16 lines 56-18)
a gate dielectric layer, located between the gate and the substrate. (Fig. 9 element 805
Column 15-16 lines 56-18)
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Shea as applied to claim 1 above, and further in view of James B, Burr et al. (EP 0697740 A2) herein after referred to as “Burr”.
Regarding Claim 3, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin further teaches:
wherein the first well region (705 and 802) has a top surface and a bottom surface opposite to each other, the top surface is adjacent to the gate structure, (Fig. element 705 is adjacent to G2)
Lin does not teach:
and the first well region has a doping concentration increasing from the top surface to the bottom surface.
Shea teaches dopant concentration variation but not doping concentration increasing from the top surface to the bottom surface specifically (Para.[0005],[0006],[0080],[0052] Fig 9. Element 49).
Burr teaches:
and the first well region has a doping concentration increasing from the top surface to the bottom surface. (Fig. 1 element 34, Page 5 column 1 lines 44 -51, Page 5 column 2 lines 5-6)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lin in view of Shea such that the first well region has a doping concentration increasing from the top surface to the bottom surface, as described in the analogous prior art of Burr because to modify the other analogous device described in Lin in view of Shea allows for the reduction of cost. (Fig. 1 element 34, Page 5 column 1 lines 44 -51, Page 5 column 2 lines 5-6)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Shea as applied to claim 1 above, and further in view of Akio Kitamura et al. (EP 0588067 A2) herein after referred to as “Kitamura”.
Regarding Claim 4, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin further teaches:
wherein the second well region has a top surface and a bottom surface opposite to each other, (Fig 9. element 702)
the top surface is adjacent to the gate structure, and (Fig. 9 element 702 is adjacent to G2)
Lin in view of Shea does not teach:
the second well region has a doping concentration decreasing from the top surface to the bottom surface.
Kitamura teaches:
the second well region has a doping concentration decreasing from the top surface to the bottom surface. (Fig. 1b element 2, Page 10 column 1 lines 27-35)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lin in view of Shea such that the second well region has a doping concentration decreasing from the top surface to the bottom surface, as described in the analogous prior art of Kitamura because to modify the other analogous device described in Lin in view of Shea allows for the decrease of the resistance value for the well. (Fig. 1b element 2, Page 10 column 1 lines 27-35).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Shea as applied to claim 1 above, and further in view of Akihiro Imada et al. (US 20150194424 A1) herein after referred to as “Imada”.
Regarding claim 6, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin in view of Shea does not teach:
wherein the drift region is further located in the first well region.
Imada teaches:
wherein the drift region (6) is further located in the first well region(3). (Fig. 1 element 6 and 3)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lin in the view of Shea such that the drift region is further located in the first well region, as described in the analogous prior art of Imada because to modify the other analogous device described in Lin in view of Shea allows for the drift region that is in extended contact with the well region, that is in contact with the source, to form a high resistance region containing an impurity at a lower concentration as compared to the drain region resistance region; this high resistance lessens the source-to-drain electric field, thus providing a high-voltage transistor structure. (Para [0015], Fig. 1 element 6 and 3)
Claim(s) 12-15, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Shea as applied to claim 1 above, and further in view of Jens Schneider et al. (US 20090140335 A1) herein after referred to as “Schneider”.
Regarding claim 12, Lin in view of Shea teaches:
The transistor structure according to claim 1,
Lin in view of Shea does not teach:
wherein the first well region and the second well region have a first conductivity type, and the drift region, the first doped region, and the second doped region have a second conductivity type.
Schneider teaches:
wherein the first well region (410) and the second well region (404) have a first conductivity type, (fig 4a elements 410 and 404 may both be p-type, Para [0058][0039]) and the drift region (412), the first doped region (402), and the second doped region (403) have a second conductivity type.(Fig 4A element 412, 402, and 403 may all be n-type)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lin in view of Shea such that the first well region and the second well region have a first conductivity type, and the drift region, the first doped region, and the second doped region have a second conductivity type, as described in the analogous prior art of Schneider because to modify the other analogous device described in Lin in view of Shea allows for a deep n-band under thus the drain may be electrically isolated against the substrate. (Para. [0094])
Regarding claim 13, Lin in view of Shea and Schneider teaches:
The transistor structure according to claim 12,
Lin further teaches
wherein the substrate has the first conductivity type. (Column 1 lines 34-39 Column 5 lines 15-18)
Regarding claim 14, Lin in view of Shea and Schneider teaches:
The transistor structure according to claim 12,
Schneider further teaches:
further comprising: a third well region (413), located in the substrate below the first well region and the second well region, (Fig. 5 element 413) wherein the third well region has the second conductivity type. (Fig. 5 element 413)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device such that a third well region, located in the substrate below the first well region and the second well region wherein the third well region has the second conductivity type, as described in the analogous prior art of Schneider because to modify the device described in Lin in view of Shea and Schneider allows for the third well region (element 413) to be electrically connected to the second well region (element 404) thusly creating an electrostatic discharge protection region . (Para. [0108])
Regarding claim 15, Lin in view of Shea and Schneider teaches:
The transistor structure according to claim 14,
Schneider further teaches:
wherein the first well region and the second well region are connected to the third well region. (Fig. 5 element 413 connected to 410 and 404)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have the first and second well region connected to the third well region, because the device described in Lin in view of Shea and Schneider allows for the third well region to be under the first well region to configure the device as a drain-extended field effect transistor and allows for the third well region to be electrically connected to the second well region thusly creating an electrostatic discharge protection region (Para. [0103][0108])
Regarding claim 18, Lin in view of Shea and Schneider teaches:
The transistor structure according to claim 12,
Schneider further teaches:
further comprising: a bulk region (406), located in the first well region, (Fig. 4a element 406) wherein the first doped region (402) is between the gate structure and the bulk region, (Fig. 4a element 402) and the bulk region has the first conductivity type. (Fig. 4a element 406)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lin in view of Shea to include a bulk region, located in the first well region, wherein the first doped region is between the gate structure and the bulk region, and the bulk region has the first conductivity type, as described in the analogous prior art of Schneider because including the bulk region in Lin in view of Shea and Schneider allows for the bulk region to serve as an electrical bulk or as a substrate contact. (Para. [0060])
Regarding claim 19, Lin in view of Shea and Schneider teaches:
The transistor structure according to claim 18,
Schneider further teaches:
further comprising: a second isolation structure (407), located in the substrate between the first doped region and the bulk region. (Fig. 4a element 407)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device such that a second isolation structure, located in the substrate between the first doped region and the bulk region, as described in the analogous prior art of Schneider because to modify the other analogous device described in Lin in view of Shea and Schneider allows for the lateral electric isolation of the bulk region and the first doped region. (Para. [0063])
Regarding claim 20, Lin in view of Shea and Schneider teaches:
The transistor structure according to claim 19,
Schneider further teaches:
wherein a bottom surface of the first well region (410) is lower than a bottom surface of the second isolation structure (407) and the first well region surrounds the second isolation structure. (Fig. 4a element 410 and 407),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have the a bottom surface of the first well region is lower than a bottom surface of the second isolation structure and the first well region surrounds the second isolation structure, as described in Schneider because to adjust Lin in view of Shea and Schneider allows for the current to flow under the isolation structure, also allowing the bulk region to serve as an electrical bulk or as a substrate contact. (Para. [0060], [0136])
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Shea and Schneider as applied to claim 12 above, and further in view of Constantin Bulucea et al. (US 20100244128 A1) herein after referred to as “Bulucea”
Regarding claim 16, Lin in view of Shea and Schneider teach:
The transistor structure according to claim 12,
Lin in view of Shea and Schneider did not teach:
further comprising: a lightly doped drain region, located in the first well region between the first doped region and the gate structure, wherein the lightly doped drain region has the second conductivity type.
Bulucea teaches:
further comprising: a lightly doped drain region, located in the first well region between the first doped region and the gate structure, wherein the lightly doped drain region has the second conductivity type. (Fig 1 element 26E and Fig. 22a element 320E Para. [0007], [0011], [0567]. Elements 26E and 320E are analogous elements)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to place a lightly doped drain region, located in the first well region between the first doped region and the gate structure, wherein the lightly doped drain region has the second conductivity type, as described Bulucea because to add the region into Lin in view of Shea and Schneider allows for the surface punch through to be avoided (Para. [0011])
Regarding claim 17, Lin in view of Shea, Schneider, and Bulucea teach:
The transistor structure according to claim 16,
Bulucea further teaches:
wherein the lightly doped drain region is located directly below the gate structure. (Fig. 19a element 240E is below gate 262 Para. [0389]. Element 240e is an analogous element to 26E and 320E)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device such that the lightly doped drain region is located directly below the gate structure, as described in the analogous prior art of Bulucea because to modify the other analogous device described in Lin in view of Shea, Schneider, and Bulucea allows for the lightly doped region to serve as a buffer that prevents damage to the gate dielectric layer during fabrication. (Para. [0389])
Response to Arguments
Applicant's arguments filed 02/23/2026 have been fully considered but they are not persuasive.
Applicant argued on page 7 of the response: “The independent claim 1 recites the limitation (I) "a first isolation structure, located in the substrate between the gate structure and the second doped region" and the limitation (II)" a doping concentration of the first portion of the first well region is greater than a doping concentration of the second portion of the second well region".
The third heavily doped region 804 of Lin is interpreted as the first isolation structure of the present application by the Examiner. Furthermore, one of ordinary skill in the art will understand that the isolation structure is a component used for electrical isolation between components, However, column 15, lines 52-55 of Lin recited "In other embodiments, the first heavily doped region 704 and pair of third heavily doped regions 804 may electrically connect electrodes (not shown) through an interconnection structure (not shown)", SO the third heavily doped regions 804 is used for electrical connection and is not an isolation structure. Therefore, Applicant respectfully submits that the third heavily doped regions 804 cannot be interpreted as the first isolation structure of the present application, and Lin fails to disclose the foregoing limitation (I) of the claim 1 of the present application…”
Examiner disagrees because the claim limitation does not explicitly mention an electrical isolation structure and could be read as a physical isolation structure. Moreover, examiner disagrees because Lin teaches 804 may have second conductivity (Col. 15 lines 39-41) while 704 may have first conductivity type (Col 12 lines 52-55) therefore Lin also teaches an electrical isolation.
Applicant argued on pages 7 and 8 of the response: “…Moreover, the Examiner indicated "Shea teaches: a doping concentration of the first portion of the first well region is greater than a doping concentration of the second portion of the second well region. (Para. [0080][0052] Fig 9. Element 49 [since placing a highly doped area in to that portion of the well region thusly makes it of higher concentration compared to the second well.])". In the claim 1 of the present application, the first portion of the limitation (II) is lower than the bottom surface of the drift region, and the second portion of the limitation (II) is lower than the bottom surface of the drift region. However, as shown in Customer FIG. 9 of Shea, the drift region of Shea is the drift region 43, and the Element 49 is not lower than the drift region 43, so the Element 49 cannot be interpreted as "the first portion" and "the second portion" of the limitation (II). Therefore, Applicant respectfully submits that Shea fails to disclose the foregoing limitation (II) of the claim 1 of the present application. FIG. 9 of Shea…”
Examiner disagrees because Lin teaches a first portion of 802 being lower than drift region 703 (Lin Figure 9) and even though Shea does not have a portion of 49 lower than drift region 43 shea does teach that the layer should be placed in the deepest portion of the base layer and should be should be electrically connected to source region (Shea Para [0052]). Therefore, to include the highly doped layer taught in Shea into the first portion taught by Lin would have been obvious because it is the deepest portion of the base layer such that it does not significantly affect the threshold voltage and electrically connected to the source such that it lowers the base resistance of the semiconductor device.
Applicant argued on page 8 of the response: “…On the other hand, other cited arts Burr, Kitamura, Imada, Schneider, and Bulucea cannot cure the deficiencies of Lin and Shea.
As such, the amended claim 1 is patentable over the cited arts, and should be allowed. For at least the same reasons, dependent claims depending on the claim 1 also patently define over the prior art as a matter of law. In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir.1988).”
Examiner disagrees because examiner disagrees with aforementioned deficiencies of Lin and Shea.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Thursday, 7:30a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/Examiner, Art Unit 2893 /J.L.S./Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893