DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group I, (claims 1-14 and 21-26), in the reply filed on
01/14/2026 is acknowledged. Claims 15-20 are canceled by Applicant. Claims 21-26 are new. Claims 1-14 and 21-26 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-2, 5 and 6 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ma et al. (US 6219243 B1, hereinafter Ma).
Re: Independent Claim 1, Ma teaches an integrated circuit system (Fig. 1) comprising:
a circuit board (130 circuit board in Col. 4, line 14, Fig.1) having a top side (top130 Fig.1-Annotated) and a bottom side (bottom130 Fig.1-Annotated) and defining an opening (135 in Col. 4, line 14, Fig.1) from the top side to the bottom side;
a bottom boiling plate (140 heat spreader, a metal as a boiling material in Col. 4, line 12, Fig.1) having a recessed portion (R140 Fig.1-Annotated) and having a projection (P140 Fig.1-Annotated) with a terminal surface (165 in Col. 4, line 13, Fig.1), wherein the recessed portion (R140 Fig.1-Annotated) is located below the bottom side (bottom130 Fig.1-Annotated) of the circuit board (130), wherein the projection (P140 Fig.1-Annotated) extends through the opening (135), and wherein the terminal surface (165 Fig.1) is located above the top side (top130 Fig.1-Annotated) of the circuit board (130);
a semiconductor substrate (110 an integrated circuit die as a semiconductor die in Col. 3, line 44-45, Fig.1) located over the top side of the circuit board (130) and including semiconductor devices (including integrated circuits in Col. 3, lines 18-20, 44-45, Fig.1); and
a top boiling plate (150 heat spreader a metal as a boiling material in Col. 4, lines 35-36, Fig.1) located over the semiconductor substrate (110), wherein the bottom boiling plate (140) and the top boiling plate (150) are configured to dissipate heat away from the integrated circuit system (in Col. 4, lines 41-46, Fig.1).
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Ma’s Figure 1-Annotated.
Re: Claim 2, Ma discloses the integrated circuit system of claim 1, wherein the semiconductor substrate (110) has a back side facing the terminal surface (165 Fig.1) of the bottom boiling plate (140 heat spreader in Col. 4, line 12, Fig.1) and a front side, wherein the semiconductor devices (including integrated circuits in Col. 3, lines 18-20, 44-45, Fig.1) are formed on the front side.
Re: Claim 5, Ma discloses the integrated circuit system of claim 2, further comprising a connector (136 conductive material in Col. 3, lines 51-52, Fig.1) electrically connecting the semiconductor devices (including integrated circuits in Col. 3, lines 18-20, 44-45, Fig.1) to the circuit board (130), wherein the connector (136) is located between the top side of the circuit board (130) and the back side of the semiconductor substrate (110).
Re: Claim 6, Ma discloses the integrated circuit system of claim 1, wherein the semiconductor substrate (110) has a back side facing the terminal surface (165 Fig.1) of the bottom boiling plate (140 heat spreader in Col. 4, line 12, Fig.1) and a front side, wherein the semiconductor devices (including integrated circuits in Col. 3, lines 18-20, 44-45, Fig.1) are formed on dies (as a semiconductor die in Col. 3, lines 18-20, 44-45), and wherein the dies (110 including dies) are located on the front side of the semiconductor substrate (110).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Matsushiba et al. (US 20090116194 A1) in view of Gupta et al. (US 20080155990 A1, hereinafter Gupta).
Re: Independent Claim 10, Matsushiba discloses an integrated circuit system (Fig. 2) comprising:
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Matsushiba’s Figure 2-Annotated.
a circuit board (32 circuit board in [0013], Fig.2) having a top side (top32 Fig.2-Annotated) and a bottom side (bottom32 Fig.2-Annotated) and defining an opening (44 opening in [0014], Fig.2) from the top side to the bottom side;
a semiconductor substrate (34 semiconductor chip, a semiconductor substrate including a CPU or an ASIC in [0013], Fig.2) having a front side (front34 Fig.2-Annotated) and a back side (back34 Fig.2-Annotated), located over the top side (top32 Fig.2-Annotated) of the circuit board (32), and including semiconductor devices ([0013]) on the front side (front34 Fig.2-Annotated);
a bottom thermally conductive member (30,42,40 bottom plate 30, thermally conductive member 42, thermally conductive elastic member 40, in [0015], Fig.2) extending through the opening (44) in the circuit board (32).
Matsushiba does not expressly disclose a voltage regulator module (VRM) on the back side of the semiconductor substrate and electrically connected to at least one of the semiconductor devices; a bottom thermally conductive member in thermal communication with the VRM to dissipate heat away from the back side of the semiconductor substrate.
However, in the same semiconductor device field of endeavor, Gupta discloses a voltage regulator module (VRM) (112 voltage regulator in [0009], Fig. 2) on the back side of the semiconductor substrate (110 substrate in [0009], Fig. 2) and electrically connected to at least one of the semiconductor devices (108 die in [0009], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gupta’s feature of a voltage regulator module (VRM) on the back side of the semiconductor substrate and electrically connected to at least one of the semiconductor devices to Matsushiba’s device to have a bottom thermally conductive member in thermal communication with the VRM to dissipate heat away from the back side of the semiconductor substrate to remove system board parasitic influences and improve a voltage droop ([0002], Gupta).
Re: Claim 11, Matsushiba modified by Gupta discloses the integrated circuit system of claim 10, wherein: the bottom thermally conductive member (30,42,40, Fig.2, Matsushiba) includes a recessed portion (R30,42,40, Fig.2-Annotated, Matsushiba) and has a projection (P30,42,40, Fig.2-Annotated, Matsushiba) with a terminal surface (54 upper surface, Fig.2, Matsushiba); the recessed portion (R30,42,40, Fig.2-Annotated, Matsushiba) is located below the bottom side of the circuit board (32, Fig.2, Matsushiba); the projection (P30,42,40, Fig.2-Annotated, Matsushiba) extends through the opening (44, Fig.2, Matsushiba); the terminal surface (54, Fig.2, Matsushiba) is located above the top side of the circuit board (32, Fig.2, Matsushiba); the terminal surface (54, Fig.2, Matsushiba) is in thermal communication with the VRM (112 from Gupta applied to Matsushiba).
Re: Claim 12, Matsushiba modified by Gupta discloses the integrated circuit system of claim 11,
Matsushiba modified by Gupta does not disclose further comprising a thermal interface material interconnecting the terminal surface and the VRM.
However, in the same semiconductor device field of endeavor, Gupta discloses a thermal interface material (130 in [0016]) interconnecting a thermoelectric cooler 122 and the VRM (112 in [0016]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gupta’s feature of a thermal interface material interconnecting a thermoelectric cooler and a VRM to Matsushiba’s device to have a thermal interface material interconnecting the terminal surface and the VRM to promote adhesion and promote heat transfer ([0016], Gupta).
Re: Claim 13, Matsushiba modified by Gupta discloses the integrated circuit system of claim 10, further comprising: a top thermally conductive member (36 heat sink in [0016], Fig.2, Matsushiba) located over the front side of the semiconductor substrate (34, Fig.2, Matsushiba), wherein the top thermally conductive member (36, Fig.2, Matsushiba) is in thermal communication with the semiconductor devices (34 including devices, Fig.2, Matsushiba) to dissipate heat away (in [0016], Fig.2, Matsushiba) from the front side of the semiconductor substrate (34, Fig.2, Matsushiba).
Re: Claim 14, Matsushiba modified by Gupta discloses the integrated circuit system of claim 13, further comprising a thermal interface material (thermally conductive material in [0016], Matsushiba) interconnecting the top thermally conductive member (36, Fig.2, Matsushiba) and the semiconductor devices (34 including devices, Fig.2, Matsushiba).
Claim(s) 3-4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ma in view of Gupta et al. (US 20080155990 A1, hereinafter Gupta).
Re: Claim 3, Ma discloses the integrated circuit system of claim 2,
Ma does not disclose further comprising a voltage regulator module (VRM) on the back side of the semiconductor substrate and electrically connected to at least one of the semiconductor devices.
However, in the same semiconductor device field of endeavor, Gupta discloses a voltage regulator module (VRM) (112 voltage regulator in [0009], Fig. 2) on the back side of the semiconductor substrate (110 substrate in [0009], Fig. 2) and electrically connected to at least one of the semiconductor devices (108 die in [0009], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gupta’s feature of a voltage regulator module (VRM) on the back side of the semiconductor substrate and electrically connected to at least one of the semiconductor devices to Matsushiba’s device to remove system board parasitic influences and improve a voltage droop ([0002], Gupta).
Re: Claim 4, Ma modified by Gupta discloses the integrated circuit system of claim 3, further comprising a thermal interface material (TIM) (160 thermal grease in Col. 4, lines 31-34, Fig.1, Ma) contacting the terminal surface (165, Fig.1, Ma) of the bottom boiling plate (140, Fig.1, Ma) and the VRM (112 from Gupta applied to Ma).
Claim(s) 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ma in view of Vandentop et al. (US 6580611 B1, hereinafter Vandentop).
Re: Claim 7, Ma discloses the integrated circuit system of claim 6,
Ma does not expressly disclose further comprising a thermal interface material (TIM) contacting the dies and the top boiling plate.
However, in the same semiconductor device field of endeavor, Vandentop discloses a thermal interface material (TIM) (TIM in Col. 3, lines 31-36, Fig.3) contacting the dies (4 in Col. 3, lines 31-36, Fig.3) and the top boiling plate (12 in Col. 3, lines 31-36, Fig.3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Vandentop’s feature of a thermal interface material (TIM) contacting the dies and the top boiling plate to Ma’s device to provide cooling on both sides of the device while eliminating the large thermal barrier of the substrate (Col. 1, lines 39-41, Vandentop).
Claim(s) 8-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ma in view of Liang et al. (US 20220375821 A1, hereinafter Liang).
Re: Claim 8, Ma discloses the integrated circuit system of claim 1,
Ma does not disclose further comprising: a top bolt coupling the top boiling plate to the circuit board; and a bottom bolt coupling the bottom boiling plate to the circuit board.
However, in the same semiconductor device field of endeavor, Liang discloses a top bolt (52 first fastener in [0093], Fig. 2) coupling the top boiling plate (4,41 heat sink 4 including a heat dissipation substrate 41 in [0083], Figs. 1,2) to the circuit board (11 PCB in [0091], Fig. 2); and a bottom bolt (51 second fastener in [0093], Fig. 2) coupling the bottom boiling plate (12 protection plate in [0091], Fig. 2) to the circuit board (11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ma’s top boiling plate according to the Liang’s feature of a top bolt coupling the top boiling plate to the circuit board; and a bottom bolt coupling the bottom boiling plate to the circuit board to increase rigidity of the PCB assembly at the corresponding bare die, so as to mitigate deformation of the PCB assembly at the bare die, and improve reliability of a connection between the bare die and the PCB assembly ([0062], Liang).
Re: Claim 9, Ma discloses the integrated circuit system of claim 1,
Ma does not disclose further comprising a ring enclosing an outer periphery of the semiconductor substrate, wherein: the top boiling plate has base portion and a sag portion; the ring terminates at an uppermost surface located below the base portion of the top boiling plate; and the sag portion of the top boiling plate is surrounded by the ring.
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Liang’s Figure 2-Annotated.
However, in the same semiconductor device field of endeavor, Liang discloses a ring (3 reinforcing frame surrounding the die 2 in [0083], Fig. 2) enclosing an outer periphery ([0083]) of the semiconductor substrate (2 bare die in [0083], Fig. 2), wherein: the top boiling plate (4,41 heat sink 4 including a heat dissipation substrate 41 in [0083], Figs. 1,2) has base portion (base-4,41 Fig. 2-Annotated) and a sag portion (sag-4,41 Fig. 2-Annotated); the ring (3) terminates at an uppermost surface located below the base portion (base-4,41 Fig. 2-Annotated) of the top boiling plate (4,41); and the sag portion (sag-4,41 Fig. 2-Annotated) of the top boiling plate (4,41) is surrounded by the ring (3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ma’s top boiling plate according to the Liang’s feature of a ring enclosing an outer periphery of the semiconductor substrate, wherein: the top boiling plate has base portion and a sag portion; the ring terminates at an uppermost surface located below the base portion of the top boiling plate; and the sag portion of the top boiling plate is surrounded by the ring to increase rigidity of the PCB assembly at the corresponding bare die, so as to mitigate deformation of the PCB assembly at the bare die, and improve reliability of a connection between the bare die and the PCB assembly ([0062], Liang).
Claim(s) 21,24-25 and 26 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Mallik et al. (US 20040173901 A1) in view of Nagesh et al. (US 5155661 A, hereinafter Nagesh).
Re: Independent Claim 21, Mallik discloses an integrated circuit system (Fig. 3) comprising:
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Mallik’s Figure 3-Annotated.
a semiconductor substrate (390 chip in [0033], Fig. 3) having a front side (front-390 Fig. 3-Annotated) and a back side (back-390 Fig. 3-Annotated) and a periphery (P-390 Fig. 3-Annotated);
a die (die included in 390 in [0033], Fig. 3) on the front side of the semiconductor substrate (390);
a top thermally conductive member (310-120 heat sink 310 and heat-conducting substrate 120 in [0033], Fig. 3) having a base portion (base-310-120 Fig. 3-Annotated) and a sag portion (sag-310-120 Fig. 3-Annotated) extending from the base portion (base-310-120 Fig. 3-Annotated); and
a bottom thermally conductive member (320 heat sink in [0033], Fig. 3) having a base portion (base-320 Fig. 3-Annotated) and a mesa portion (mesa-320 Fig. 3-Annotated) extending from the base portion (base-320 Fig. 3-Annotated).
Mallik does not expressly disclose a top ring located on the front side of the semiconductor substrate at the periphery, the top ring defining a top inner gap between opposite sides of the top ring; a bottom ring located on the back side of the semiconductor substrate at the periphery, the bottom ring defining a bottom inner gap between opposite sides of the bottom ring; a die located in the top inner gap, wherein the sag portion is located in the top inner gap, wherein the mesa portion is located in the bottom inner gap.
However, in the same semiconductor device field of endeavor, Nagesh discloses a top ring (32 ring in Col. 2, line 64, Fig.2) located on the front side of the PCB (12 PCB in Col. 2, lines 55-56, Fig. 2) at the periphery (outer sides of 12, Fig. 2), the top ring (32) defining a top inner gap (Fig. 2) between opposite sides of the top ring (32); a bottom ring (34 ring in Col. 2, lines 64-65, Fig.2) located on the back side of the PCB (12 PCB in Col. 2, lines 55-56, Fig. 2) at the periphery (outer sides of 12, Fig. 2), the bottom ring (34) defining a bottom inner gap (Fig. 2) between opposite sides of the bottom ring (34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Nagesh’s top ring on the front side of the Mallik’s PCB and to include Nagesh’s bottom ring to the back side of the Mallik’s PCB to obtain a top ring located on the front side of the semiconductor substrate at the periphery, the top ring defining a top inner gap between opposite sides of the top ring; a bottom ring located on the back side of the semiconductor substrate at the periphery, the bottom ring defining a bottom inner gap between opposite sides of the bottom ring; a die located in the top inner gap, wherein the sag portion is located in the top inner gap, wherein the mesa portion is located in the bottom inner gap for providing electrical connection between the substrate and the printed circuit board (Col. 2, lines 33-35, Nagesh).
Re: Claim 24, Mallik modified by Nagesh discloses the integrated circuit system of claim 21, wherein the top ring (32 from Nagesh applied to Mallik) and the bottom ring (34 from Nagesh applied to Mallik) clamp the periphery of the semiconductor substrate (390, Mallik).
Re: Claim 25, Mallik modified by Nagesh discloses the integrated circuit system of claim 21, further comprising a circuit board (94 printed circuit board in [0031], Fig. 3) having a top side (top-94 in [0031], Fig. 3-Annotated) and a bottom side (bottom-94 in [0031], Fig. 3-Annotated) and defining an opening (O-94 in [0031], Fig. 3-Annotated) from the top side to the bottom side, wherein the mesa portion (mesa-320 Fig. 3-Annotated) of the bottom thermally conductive member (320 Fig. 3) extends through the opening (O-94 in [0031], Fig. 3-Annotated).
Re: Claim 26, Mallik modified by Nagesh discloses the integrated circuit system of claim 21, wherein the top ring (32 from Nagesh applied to Mallik) terminates at an uppermost surface located below the base portion (base-310-120 Fig. 3-Annotated) of the top thermally conductive member (310-120 Fig. 3-Annotated), and wherein the sag portion (sag-310-120 Fig. 3-Annotated) of the top thermally conductive member (310-120 Fig. 3) is surrounded by the top ring (32 from Nagesh applied to Mallik).
Claim(s) 22 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Mallik in view of Nagesh and further in view of Gupta et al. (US 20080155990 A1, hereinafter Gupta).
Re: Claim 22, Mallik modified by Nagesh discloses the integrated circuit system of claim 21,
Mallik modified by Nagesh does not disclose further comprising a voltage regulator module (VRM) located in the bottom inner gap and on the back side of the semiconductor substrate.
However, in the same semiconductor device field of endeavor, Gupta discloses a voltage regulator module (VRM) (112 voltage regulator in [0009], Fig. 2) on the back side of the semiconductor substrate (110 substrate in [0009], Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gupta’s feature of a voltage regulator module (VRM) on the back side of the semiconductor substrate to the combination of Mallik and Nagesh to obtain a voltage regulator module (VRM) located in the bottom inner gap and on the back side of the semiconductor substrate to remove system board parasitic influences and improve a voltage droop ([0002], Gupta).
Claim(s) 23 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Mallik in view of Nagesh, in view of Gupta and further in view of Vandentop et al. (US 6580611 B1, hereinafter Vandentop).
Re: Claim 23, Mallik modified by Nagesh discloses the integrated circuit system of claim 22,
Mallik modified by Nagesh does not disclose further comprising: a top thermal interface material (TIM) layer located in the top inner gap and contacting the die and the sag portion of the top thermally conductive member; and a bottom thermal interface material (TIM) layer located in the bottom inner gap and contacting the VRM and the mesa portion of the bottom thermally conductive member.
However, in the same semiconductor device field of endeavor, Vandentop discloses a thermal interface material (TIM) (TIM in Col. 3, lines 31-36, Fig.3) on the top (12 in Col. 3, lines 31-36, Fig.3) and bottom (18 in Col. 3, lines 31-36, Fig.3) heat sinks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Vandentop’s feature of a thermal interface material (TIM) on the top and bottom heat sinks to the combination of Mallik, Nagesh and Gupta to obtain a top thermal interface material (TIM) layer located in the top inner gap and contacting the die and the sag portion of the top thermally conductive member; and a bottom thermal interface material (TIM) layer located in the bottom inner gap and contacting the VRM and the mesa portion of the bottom thermally conductive member to provide cooling on both sides of the device while eliminating the large thermal barrier of the substrate (Col. 1, lines 39-41, Vandentop).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Cai et al (US 11646240 B2) teaches “THROUGH-HOLE MOUNTED SEMICONDUCTOR ASSEMBLIES”. This document is related to a printed circuit board (“PCB”) having first and second PCB sides and has a through hole therein. The through hole defines a hole area. A semiconductor package may be disposed in the hole area such that the semiconductor package is at least partially exposed on one or more of the first and the second PCB sides. Package contacts on the semiconductor package may be electrically coupled to PCB contacts disposed on one or more of the PCB sides. In some embodiments, one or more support structures may be coupled to the PCB and may touch the semiconductor package. In some embodiments, cooling devices may be placed in thermal communication with the semiconductor package on both sides of the PCB.
Lynch (US 7706144 B2) teaches “HEAT DISSIPATION SYSTEM AND RELATED METHOD”. This document is related to a heat sink bonded to an integrated circuit package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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