DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group II, claims 1-15 and new claims 21-25, in the reply filed on January 23, 2026 is acknowledged. Therefore, claims 1-15 and 21-25 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14 and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 14 and 24, it is not clear how the second nMOS device structure is identical to the first nMOS device structure, because Applicants originally disclosed in Fig. 2I of the present application and describe in claim 1 that the gate of the first nMOS device structure is doped with a n-type dopant, whereas the gate of the second nMOS device structure is doped with a p-type dopant, therefore, since the conductivity types of the gates are different, the two device structures are not “identical” in composition or structure; because Applicants do not specifically claim whether the term “identical” refers only to geometrical features or physical dimensions, it remains unclear how the second nMOS device structure is identical to the first nMOS device structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over by Weng et al. (US 2023/0197725, Provisional application: Dec. 16, 2021; Foreign Priority: Jul. 12, 2022 (TW); hereinafter Weng).
Regarding claim 1, Weng discloses for a method of fabricating an electronic device (integrated structure 50, Fig. 3T-3U), the method comprising that
forming a first nMOS device structure (NMOS53 in RV2 region, Fig. 3U) and a second nMOS device structure (NMOS51 in UHV2 region, Fig. 3T), each nMOS device structure (NMOS53/NMOS51, Fig. 3T-3U) including a gate oxide (gate dielectric 57’, Fig. 3O) disposed on a p-type base material (substrate 51/semiconductor layer 51’, Fig. 3U), because “the substrate 51 can be for example a P-type or an N-type” (emphasis added, [0055]) and “the semiconductor layer 51’, for example, is formed by an epitaxial process step, or is a part of the substrate 51” (emphasis added, [0055]), therefore, a composite layer of the substrate 51 and the semiconductor layer 51’ by Weng can correspond to the p-type base material in the claimed invention, and the gate dielectric 57’ is disposed on the substrate 51 (Fig. 3O), and a gate (fifth gate 57e, Fig. 3U) disposed on the gate oxide (57’, Fig. 3U);
performing n-type dopant implantation to form source (third N-type source 58c, Fig. 3U) and drain (third N-type drain 59c, Fig. 3U) regions in the p-type substate (51/51’, Fig. 3U) of the first nMOS device structure (NMOS53, Fig. 3U) and source (first N-type source 58a, Fig. 3T) and drain (first N-type drain 59a, Fig. 3T) regions in the p-type substate (51/51’, Fig. 3T) of the second nMOS device structure (NMOS51, Fig. 3T) and to further dope the gate of the first nMOS device structure (fifth gate 57e, Fig. 3U) n-type (N+Ply3, Fig. 3U) whereby a first nMOS device (NMOS53, Fig. 3U) is formed comprising the first nMOS device structure (NMOS53, Fig. 3U) with the gate doped n-type (fifth gate 57e, N-Ply3, Fig. 3U), because “the third N-type source 58c and the third N-type drain 59c are formed in the semiconductor layer 51’ of the middle threshold device region RV by the one same ion implantation process step that forms the first N-type source 58a and the first N-type drain 59a” (emphasis added, [0076]); and
the gate of the second nMOS device structure (first gate 57a of NMOS51, Fig. 3T) p-type (P-Ply1, Fig. 3T) whereby a second nMOS device (NMOS51 in UHV2 region, Fig. 3T) is formed comprising the second nMOS device structure (NMOS51, Fig. 3T) with the gate anti-doped p-type (P-Ply1, Fig. 3T), because Applicants do not specifically claim an entirety of the gate of the second NMOS device structure is p-type, the first gate 57a of NMOS51 by Weng includes the first P-type polysilicon layer P+Ply1 (Fig. 3T). Examiner notes that Applicants did not originally disclose or do not specifically claim the definition of “anti-doped” and a word “anti-doped” is not a standard semiconductor term.
Weng does not explicitly discloses performing p-type dopant implantation to dope the gate of the second nMOS device structure p-type.
However, Weng further discloses that the ion implantation process steps using P-type dopant impurities are employed to form various p-type regions, such as a P-type well, a P-type source and a P-type drain ([0006]-[0009] of Weng), therefore, ion implantation was well known in the semiconductor art at the time of the invention as a conventional technique for introducing dopants into semiconductor and polysilicon layers with controlled conductivity types. In view of Weng’s disclosure of forming p-type regions using ion implantation, one of ordinary skill in the art would have reasonably understood that the first P-type polysilicon layer (P+Ply1) of NMOS51 in Weng could likewise be doped with P-type dopants using ion implantation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ ion implantation to introduce p-type dopants into the polysilicon gate of the NMOS device, as such doping technique was well known and routinely used in semiconductor manufacturing to control the conductivity type and electrical characteristics of polysilicon gate structure.
Regarding claim 6, Weng further discloses that the forming of each of the first nMOS device structure (NMOS53, Fig. 3U) and the second nMOS device structure (NMOS51, Fig. 3T) includes: forming a well structure (P-type well 53c/N-type well 55e of NMOS53 and P-type well 53a/N-type well 55c of NMOS51, Figs. 3T-3U) by dopant implantation in a p-type substrate (51, Fig. 3U), the well structure (53c/55e of NMOS51 and 53a/55c of NMOS 51, Figs. 3T-3U) comprising a p-type well (53c or 53a, Figs. 3T-3U) containing the p-type base material of the well structure (portion of 51/51’, Figs. 3T-3U) and an n-type well (55e or 55c, Figs. 3T-3U) containing the p-type well (53c or 53a, Figs. 3T-3U); forming the gate oxide (57’, Fig. 3O) on the p-type base material (51/51’, Fig. 3U); and forming the gate (57e and 57a, Figs. 3T-3U) on the gate oxide (57’, Fig. 3O).
Weng does not explicitly disclose that the p-type well has higher p-type doping than the p-type base material.
However, Weng further discloses that P-type well is formed by ion implantation with p-type dopants into the p-type substrate ([0006], [0055]), and it is obvious to one of ordinary skill in the art that the ion implanted P-type well has higher dopant concentration than the substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the P-type well with a higher p-type dopant concentration than the p-type substrate, in order to control MOSFET device characteristics, as varying dopant concentration in wells relative to the substrate.
Regarding claim 8, Weng further discloses that the gate of the first nMOS device structure (fifth gate 57e of NMOS53, Fig. 3U) is a polysilicon gate, because “the fifth gate has a third N-type polysilicon layer (emphasis added, [0006]), and the gate of the second nMOS device structure (first gate 57a of NMOS51, Fig. 3T) is a polysilicon gate, because “the first gate has a first P-type polysilicon layer and two first N-type polysilicon sub-layers” (emphasis added, [0006]).
Regarding claim 9, Weng further discloses that forming a voltage reference circuit including the first nMOS device (NMOS53, Fig. 3U) and the second nMOS device (NMOS51, Fig. 3T), because Applicants do not specifically claim what a voltage reference circuit does, the device by Weng includes the ultra high threshold device region UHV, a high threshold device region HV, a middle threshold device region RV and a low threshold device region LV (Figs. 3T-3U, [0022]) and Weng further explains “in the CMOS device UHV2 having an ultra high threshold voltage… In the CMOS device HV2 having a high threshold voltage… In the CMOS device RV2 having a middle threshold voltage… In the CMOS device LV2 having a low threshold voltage…” ([0059]), therefore, since NMOS51 is formed in the UHV2 device region and NMOS53 is formed in the RV2 device region (Figs. 3T-3U), NMOS51 and NMOS53 would have different threshold voltages, thereby enabling the formation of a voltage reference circuit.
Claims 2 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (US 2023/0197725, Provisional application: Dec. 16, 2021; Foreign Priority: Jul. 12, 2022 (TW); hereinafter Weng) in view of May et al. (“Threshold Voltage Adjustment on 4H-SiC MOSFETs Using p-Doped Polysilicon as a Gate Material”, Key Engineering Materials, ISSN: 1662-9795, Vol. 947, pp 57-62, Published online 05-31-2023; hereinafter May). The teachings of Weng are discussed above.
Regarding claim 2, Weng differs from the claimed invention by not showing that the p-type dopant implantation dopes the entire gate of the second nMOS device structure p-type whereby the second nMOS device is formed comprising the gate entirely anti-doped p-type.
However, May discloses a MOSFET device in which a p-doped polysilicon gate electrode (pPolySi, page 58) is formed over NMOS structure (Fig. 1, page 58) and specifically, the pPolySi gate is doped with p-type dopants via ion implantation of boron ions (line 1, page 58); as shown in Fig. 1 of May, the entire gate electrode of the NMOS is p-doped polysilicon. In view of May’s teaching that a p-doped polysilicon gate may be formed over an NMOS device, one of ordinary skill in the art would have found it obvious to modify the first gate 57a of NMOS51 in Weng, which corresponds to the second NMOS device structure in the claimed invention, by employing a p-doped polysilicon gate electrode, as disclosed by May. Such a modification would have been motivated by advantages of adjusting gate work function and electrical characteristics of the MOSFET device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ p-doped polysilicon for the gate electrode of the NMOS device in Weng in view of May, in order to optimize the electrical properties of the MOSFET device.
Regarding claim 11, Weng further discloses for a method of fabricating an electronic device (integrated structure 50, Fig. 3T-3U), the method comprising that
forming a first nMOS device structure (NMOS53 in RV2 region, Fig. 3U) and a second nMOS device structure (NMOS51 in UHV2 region, Fig. 3T);
performing an n-type doping step to dope a gate of the first nMOS device structure (fifth gate 57e of NMOS53, Fig. 3U) with an n-type dopant to form a first nMOS device having an n-type gate (N+Ply3, 57e, Fig. 3U); and
performing a p-type doping step to dope a gate of the second nMOS device structure (first gate 57a of NMOS51, Fig. 3T) with a p-type dopant to form a second nMOS device having a p-type gate (P-Ply1, Fig. 3T)
Weng differs from the claimed invention by not showing that a p-type gate includes no n-type portion.
However, May discloses a MOSFET device in which a p-doped polysilicon gate electrode (pPolySi, page 58) is formed over NMOS structure (Fig. 1, page 58) and specifically, the pPolySi gate is doped with p-type dopants via ion implantation of boron ions (line 1, page 58); as shown in Fig. 1 of May, the entire gate electrode of the NMOS is p-doped polysilicon without n-type portion. In view of May’s teaching that a p-doped polysilicon gate may be formed over an NMOS device, one of ordinary skill in the art would have found it obvious to modify the first gate 57a of NMOS51 in Weng, which corresponds to the second NMOS device structure in the claimed invention, by employing a p-doped polysilicon gate electrode, as disclosed by May. Such a modification would have been motivated by advantages of adjusting gate work function and electrical characteristics of the MOSFET device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ p-doped polysilicon for the gate electrode of the NMOS device in Weng in view of May, in order to optimize the electrical properties of the MOSFET device.
Regarding claim 12, Weng further discloses that the n-type doping step also: dopes p-type base material (51/51’, Figs. 3T-3U) of the first nMOS device structure (NMOS53, Fig. 3U) to form source (third N-type source 58c, Fig. 3U) and drain (third N-type drain 59c, Fig. 3U) regions of the first nMOS device (NMOS53, Fig. 3U); and dopes p-type base material (51/51’, Fig. 3T) of the second nMOS device structure (NMOS51, Fig. 3T) to form source (first N-type source 58a, Fig. 3T) and drain (first N-type drain 59a, Fig. 3T) regions of the second nMOS device (NMOS51, Fig. 3T), because “the third N-type source 58c and the third N-type drain 59c are formed in the semiconductor layer 51’ of the middle threshold device region RV by the one same ion implantation process step that forms the first N-type source 58a and the first N-type drain 59a” (emphasis added, [0076]).
Regarding claim 13, Weng further discloses that the n-type doping step is an n-type dopant implantation step, because “the third N-type source 58c and the third N-type drain 59c are formed in the semiconductor layer 51’ of the middle threshold device region RV by the one same ion implantation process step that forms the first N-type source 58a and the first N-type drain 59a” (emphasis added, [0076]).
Weng does not explicitly disclose that the p-type doping step is a p-type dopant implantation step.
However, Weng further discloses that the ion implantation process steps using P-type dopant impurities are employed to form various p-type regions, such as a P-type well, a P-type source and a P-type drain ([0006]-[0009] of Weng), therefore, ion implantation was well known in the semiconductor art at the time of the invention as a conventional technique for introducing dopants into semiconductor and polysilicon layers with controlled conductivity types. In view of Weng’s disclosure of forming p-type regions using ion implantation, one of ordinary skill in the art would have reasonably understood that the first P-type polysilicon layer (P+Ply1) of NMOS51 in Weng could likewise be doped with P-type dopants using ion implantation. Furthermore, May further discloses that the pPolySi gate is doped with p-type dopants via ion implantation of boron ions (line 1, page 58).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ ion implantation to introduce p-type dopants into the polysilicon gate of the NMOS device, as such doping technique was well known and routinely used in semiconductor manufacturing to control the conductivity type and electrical characteristics of polysilicon gate structure.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (US 2023/0197725, Provisional application: Dec. 16, 2021; Foreign Priority: Jul. 12, 2022 (TW); hereinafter Weng) in view of Kim (US 2006/0148148). The teachings of Weng are discussed above.
Regarding claim 4, Weng does not explicitly disclose prior to performing the n-type dopant implantation, disposing photoresist on the gate of the second nMOS device structure; wherein the photoresist disposed on the gate of the second nMOS device structure prevents the n-type dopant implantation from doping the gate of the second nMOS device structure.
However, Weng further discloses that the ion implanatation process steps using N-type dopant impurities are employed to form various n-type regions, such as a N-type well, a N-type source and a N-type drain ([0006]-[0009] of Weng) and the use of photoresist pattern for the protection of semiconductor layer was well known in the semiconductor art at the time of the invention as a conventional technique for photolithography. Furthermore, Kim discloses for a fabrication of MOSFET device that prior to ion implantation with n+ dopant ions, pMOS region is protected with the photoresist pattern 150a (Fig. 2C), in order to prevent pMOS region from doping n-type dopants, therefore, one of ordinary skill in the art would have reasonably understood that photoresist mask would be used for n-type doping by ion implantation process in order to selectively dope n-type dopants only in the selected region.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispose a photoresist pattern over the gate electrode during the n-type ion implantation process in order to prevent dopant introduction into the gate electrode, as the use of photoresist pattern as an ion implantation mask is a well-known and routine technique in semiconductor manufacturing.
Regarding claim 5, Weng in view of Kim further discloses that after performing the n-type dopant implantation, removing the photoresist on the gate of the second nMOS device structure and, prior to performing the p- type dopant implantation, disposing photoresist on the gate of the first nMOS device structure; wherein the photoresist disposed on the gate of the first nMOS device structure prevents the p-type dopant implantation from doping the gate of the first nMOS device structure, because as discussed in claim 4 above, Weng further discloses that the ion implantation process steps using P-type dopant impurities are employed to form various p-type regions, such as a P-type well, a P-type source and a P-type drain ([0006]-[0009] of Weng) and the use of photoresist pattern for the protection of semiconductor layer was well known in the semiconductor art at the time of the invention as a conventional technique for photolithography. Furthermore, Kim discloses for a fabrication of MOSFET device that prior to ion implantation with p+ dopant ions, nMOS region is protected with the photoresist pattern 151a (Fig. 2E), in order to prevent nMOS region from doping p-type dopants, therefore, one of ordinary skill in the art would have reasonably understood that photoresist mask would be used for p-type doping by ion implantation process in order to selectively dope p-type dopants only in the selected region.
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (US 2023/0197725, Provisional application: Dec. 16, 2021; Foreign Priority: Jul. 12, 2022 (TW); hereinafter Weng) in view of Kim (US 2006/0148148), and further in view of May et al. (“Threshold Voltage Adjustment on 4H-SiC MOSFETs Using p-Doped Polysilicon as a Gate Material”, Key Engineering Materials, ISSN: 1662-9795, Vol. 947, pp 57-62, Published online 05-31-2023; hereinafter May). The teachings of Weng are discussed above.
Regarding claim 21, Weng discloses for a method of fabricating an electronic device (integrated structure 50, Fig. 3T-3U), the method comprising that
forming a first nMOS device structure (NMOS53 in RV2 region, Fig. 3U) and a second nMOS device structure (NMOS51 in UHV2 region, Fig. 3T);
performing an n-type doping step to dope a gate of the first nMOS device structure (fifth gate 57e of NMOS53, Fig. 3U) with an n-type dopant to form a first nMOS device having an n-type gate (N+Ply3, Fig. 3U).
Weng does not explicitly disclose that disposing photoresist on a gate of the second nMOS device structure; the photoresist on the gate of the second nMOS device structure prevents the n-type doping step from doping the gate of the second nMOS device structure; after the n-type doping step, removing the photoresist from the gate of the second nMOS device structure; and after removing the photoresist from the gate of the second nMOS device structure, performing a p-type doping step to dope the gate of the second nMOS device structure with a p-type dopant to form a second nMOS device.
However, Weng further discloses that the ion implantation process steps using N-type dopant impurities are employed to form various n-type regions, such as a N-type well, a N-type source and a N-type drain and P-type dopant impurities are employed to form various p-type regions, such as a P-type well, a P-type source and a P-type drain ([0006]-[0009] of Weng), and the use of photoresist pattern for the protection of semiconductor layer was well known in the semiconductor art at the time of the invention as a conventional technique for photolithography. Furthermore, Kim discloses for a fabrication of MOSFET device that prior to ion implantation with n+ dopant ions, pMOS region is protected with the photoresist pattern 150a (Fig. 2C) and prior to ion implantation with p+ dopant ions, nMOS region is protected with the photoresist pattern 151a (Fig. 2E), in order to prevent pMOS region from doping n-type dopants (Fig. 2C) and nMOS region from doping p-type dopants (Fig. 2E), therefore, one of ordinary skill in the art would have reasonably understood that photoresist mask would be used for n-type or p-type doping by ion implantation process in order to selectively dope p-type dopants or n-type dopants only in the selected region.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispose a photoresist pattern over the gate electrode during the n-type or p-type ion implantation process in order to prevent dopant introduction into the gate electrode, as the use of photoresist pattern as an ion implantation mask is a well-known and routine technique in semiconductor manufacturing.
Further regarding claim 21, Weng in view of Kim differs from the claimed invention by not showing that a p-type gate includes no n-type portion.
However, May discloses a MOSFET device in which a p-doped polysilicon gate electrode (pPolySi, page 58) is formed over NMOS structure (Fig. 1, page 58) and specifically, the pPolySi gate is doped with p-type dopants via ion implantation of boron ions (line 1, page 58); as shown in Fig. 1 of May, the entire gate electrode of the NMOS is p-doped polysilicon. In view of May’s teaching that a p-doped polysilicon gate may be formed over an NMOS device, one of ordinary skill in the art would have found it obvious to modify the first gate 57a of NMOS51 in Weng, which corresponds to the second NMOS device structure in the claimed invention, by employing a p-doped polysilicon gate electrode, as disclosed by May. Such a modification would have been motivated by advantages of adjusting gate work function and electrical characteristics of the MOSFET device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ p-doped polysilicon for the gate electrode of the NMOS device in Weng in view of May, in order to optimize the electrical properties of the MOSFET device.
Regarding claim 22, Weng does not explicitly disclose that prior to performing the p-type doping step, disposing photoresist on the gate of the first nMOS device structure, wherein the photoresist disposed on the gate of the first nMOS device structure prevents the p-type doping step from doping the gate of the first nMOS device structure.
However, Weng further discloses that the ion implantation process steps using P-type dopant impurities are employed to form various p-type regions, such as a P-type well, a P-type source and a P-type drain ([0006]-[0009] of Weng) and the use of photoresist pattern for the protection of semiconductor layer was well known in the semiconductor art at the time of the invention as a conventional technique for photolithography. Furthermore, Kim discloses for a fabrication of MOSFET device that prior to ion implantation with p+ dopant ions, nMOS region is protected with the photoresist pattern 151a (Fig. 2E), in order to prevent nMOS region from doping p-type dopants, therefore, one of ordinary skill in the art would have reasonably understood that photoresist mask would be used for p-type doping by ion implantation process in order to selectively dope p-type dopants only in the selected region.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispose a photoresist pattern over the gate electrode during the n-type or p-type ion implantation process in order to prevent dopant introduction into the gate electrode, as the use of photoresist pattern as an ion implantation mask is a well-known and routine technique in semiconductor manufacturing.
Regarding claim 23, Weng further discloses that the n-type doping step also dopes p-type base material (51/51’, Figs. 3T-3U) of the first nMOS device structure (NMOS53, Fig. 3U) to form source and drain regions (third N-type source 58c and third N-type drain 59c, Fig. 3U) of the first nMOS device (NMOS53, Fig. 3U), and also dopes p-type base material (51/51’, Fig. 3T) of the second nMOS device structure (NMOS51, Fig. 3T) to form source and drain regions (first N-type source 58a and first N-type drain 59a, Fig. 3T) of the second nMOS device.
Allowable Subject Matter
Claims 3, 7, 10, 15 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior arts cited in this Office Action do not teach the claimed limitations, “the first nMOS device and the second nMOS device are identical except that the gate of the first nMOS device is doped n-type and the gate of the second nMOS device is doped entirely p-type with no n-type portion” of claim 3, “the p-type dopant implantation increases a p-type doping level of a periphery of the p-type well of each of the first nMOS device structure and the second nMOS device structure” of claim 7, “connecting the gates of the first and second nMOS devices to form a common gate node of the voltage reference circuit” of claim 10, “the circuit includes a node with operating voltage that is equal to or proportional to ΔVGS where ΔVGS is a difference between a gate-source voltage VGS,1 of the first nMOS device and a gate-source voltage VGS,2 of the second nMOS device” of claims 15 and 25.
Conclusion
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