DETAILED ACTION
This correspondence is in response to the communications received 12/16/2025. Claim 3 has been withdrawn. Claims 1-8 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1, 2, and 4-8 in the reply filed on 12/16/2025 is acknowledged.
Claim 3 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/16/2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/18/2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5, and 6 and the claims that depend therefrom are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the pad" in line 17. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the pad” will be interpretated as “the signal pad”.
Claim 5 recites the limitation "the pad" in line 17. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the pad” will be interpretated as “the signal pad”.
Claim 6 recites the limitation "between the pads" in line 5. There is insufficient antecedent basis for this limitation in the claim. Further, it is unclear if "the pads" in line 5 is referring to the signal pad of claim 5 or the plurality of pads of claim 6 or a combination thereof. For the purposes of examination “between the pads” will be interpretated as “between pads of the plurality of pads”.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a semiconductor device (20) comprising:
a semiconductor element (40) having a first main electrode ("emitter electrode 42") and a signal pad (44) on one surface (as seen in Fig. 3, 42 and 44 are on the upper surface of 40), and having a second main electrode ("collector electrode 43") on a back surface opposite to the one surface in a thickness direction (as seen in Fig. 3, 43 is on the lower surface of 40 opposite the upper surface in the Z direction);
a first wiring member (50) electrically connected to the first main electrode (see [0072]);
a second wiring member (60) electrically connected to the second main electrode (see [0072]), the semiconductor element being disposed between the first wiring member and the second wiring member in the thickness direction (see Fig. 3);
a conductive spacer (70) interposed between the semiconductor element and the first wiring member (see Fig. 3); and
a solder (91, 92, 93) disposed between the second wiring member and the second main electrode (as seen in Fig. 3, 93 is between 60 and 43), between the first main electrode and the conductive spacer (as seen in Fig. 3, 91 is between 42 and 70), and between the conductive spacer and the first wiring member (as seen in Fig. 3, 92 is between 70 and 50), wherein
the conductive spacer has an end surface (70a) facing the semiconductor element (see Fig. 3) and a side surface (70c) continuous with the end surface (see Figs. 3 and 7),
the side surface has
a recess (71) open in the end surface and located at least adjacent to the pad in a plan view along the thickness direction (see Figs. 3 and 7),
a roughened region (72) in which a roughened oxide film is formed to have a continuously roughened surface, excluding an inner surface of the recess (see [0104]), and
a non-roughened region (73), in which the roughened oxide film is not formed, on the inner surface of the recess (see [0104]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kadoguchi et al. (US 8,884,411 B2) in view of Murasaki (US 20220216313 A1).
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Regarding claim 5, Figs. 1-6 of Kadoguchi disclose a semiconductor device (“semiconductor device 100”) comprising:
a semiconductor element (together “first semiconductor element 10”, “collector electrode 11”, “emitter electrode 12”, and “gate electrode 13” form a semiconductor element) including a semiconductor substrate (as 10 is the base on which 11, 12, and 13 are formed, 10 is therefore a substrate), a first main electrode (“emitter electrode 12”) and a signal pad (“gate electrode 13”) provided on one surface of the semiconductor substrate (as seen in Fig. 1, 12 and 13 are on the upper surface of 10), and a second main electrode (“collector electrode 11”) provided on a back surface opposite to the one surface in a thickness direction (as seen in Fig. 1, 11 is mounted on the lower surface of 10 which is opposite to the upper surface in the vertical direction);
a first wiring member (“third thick plate portion 41”) electrically connected to the first main electrode (“41 is formed by a conductor and is electrically connected to the emitter electrode 12 of the IGBT 10 via a spacer 14”, col. 7, lines 54-56);
a second wiring member (“first thick plate portion 31”) electrically connected to the second main electrode (“31 is formed by a conductor, and is electrically connected to the collector electrode 11 of the IGBT 10 via joining material 11a”, col. 7, lines 23-25), the semiconductor element being disposed between the first wiring member and the second wiring member in the thickness direction (as seen in Fig. 1, 10-13 are between 41 and 31 in the vertical direction);
a conductive spacer (“spacer 14”, as 41 is electrically connected to 12 via 14, 14 must necessarily be conductive, further Fig. 2 shows a direct connection between 12 and “collector electrode 21” which indicates that the elements connecting 12 and 21 function as conductors, as seen in Fig. 1, this includes 14) interposed between the semiconductor element and the first wiring member (as seen in Fig. 1, 14 is interposed between 10-13 and 41); and
a solder disposed between the second wiring member and the second main electrode (“joining material 11a” where “tin-type solder, for example, may be used as the joining material 11a and 21a”, col. 7, lines 52-53, as seen in Fig. 1, 11a is between 31 and 11), between the first main electrode and the conductive spacer (“joining material 12a” where “tin-type solder, for example, may be used as the joining material 12a, 14a, 22a, and 24a”, col 8, lines 21-22, as seen in Fig. 1, 12a is between 12 and 14), and between the conductive spacer and the first wiring member (“joining material 14a”, a seen in Fig. 1, 14a is between 14 and 41), wherein
the first main electrode has a bonding portion (the upper surface of 12 is a bonding portion) bonded with the conductive spacer (as seen in Fig. 1, the upper surface of 12 is bonded with 14 via 12a),
the bonding portion and the pad are arranged in a first direction (as seen in Fig. 1, the upper surface of 12 and 13 are arranged in the horizontal direction) orthogonal to the thickness direction (the horizontal direction is orthogonal to the vertical direction), and
Figs. 1-6 of Kadoguchi fail to disclose “the semiconductor element includes a dummy wiring extending from an end of the bonding portion of the first main electrode adjacent to the pad and arranged in parallel with the pad in a second direction orthogonal to the thickness direction and the first direction.”
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However, in a similar field of endeavor, Figs. 1-4 of Murasaki teach the semiconductor element includes a dummy wiring (as “emitter pad region 5a serves as a bonding pad to which a bonding wire is bonded”, [0023], the portion of “emitter electrode 5” denoted “DW” in Fig. 1 is therefore a dummy region as DW is not part of the conduction pathway from “active region 3” to 5a in “normal line direction Z”) extending from an end of the bonding portion of the first main electrode adjacent (as seen in Fig. 1, DW extend from 5a where 5a of Murasaki is equivalent to the upper surface of 12 of Kadoguchi) to the pad (as seen in Fig. 1, DW extend to “gate pad region 6a”, where 6a of Muraskai is equivalent to 13 of Kadoguchi) and arranged in parallel with the pad in a second direction (as seen in Fig. 1, DW are in parallel with 6a in “second direction Y” where Y of Murasaki is equivalent to the direction into and out of the page of Fig. 1 of Kadoguchi) orthogonal to the thickness direction and the first direction (the direction into and out of the page of Fig. 1 of Kadoguchi is orthogonal to the vertical and horizontal directions of Kadoguchi).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the semiconductor element includes a dummy wiring extending from an end of the bonding portion of the first main electrode adjacent to the pad and arranged in parallel with the pad in a second direction orthogonal to the thickness direction and the first direction” as taught by Murasaki in the system of Kadoguchi for the purpose of maximizing the contact area between an electrode and the underlying active region while providing room for additional contact pads.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kadoguchi et al. (US 8,884,411 B2) in view of Murasaki (US 20220216313 A1) in view of Okura (US 20210028085 A1) in view of Sdrulla et al. (US 20230022394 A1).
Regarding claim 6, Figs. 1-6 of Kadoguchi in combination with Figs. 1-4 of Murasaki disclose the semiconductor device according to claim 5.
Figs. 1-6 of Kadoguchi do not specify “wherein the semiconductor element includes a plurality of pads arranged in the second direction, and
the dummy wiring extends from the bonding portion of the first main electrode to a space between the pads.”
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However, in a similar field of endeavor, Fig. 3 of Okura teaches wherein the semiconductor element includes a plurality of pads (“pads 20P” where 20P of Okura are equivalent to 13 of Kadoguchi) arranged in the second direction (as seen in Fig. 3, 20P are arranged in the “X direction” where X of Okura is equivalent to the direction into and out of the page of Fig. 1 of Kadoguchi).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the semiconductor element includes a plurality of pads arranged in the second direction” as taught by Okura in the system of Kadoguchi in combination with Murasaki for the purpose of increasing the bandwidth to the semiconductor element by including additional signal pads.
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However, in a similar field of endeavor, Figs. 2A and 2B of Sdrulla teach the dummy wiring extends from the bonding portion of the first main electrode to a space between the pads (after the combination of Murasaki and Okura with Kadoguchi, DW would extend from the upper surface of 12 to a space between each of the plurality of 13 in the manner taught by Sdrulla where “The gate contact 126 includes a plurality of fingers. The source contact 124 includes a plurality of fingers inter-digitated with the plurality of fingers of the gate contact 126”, [0090]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the dummy wiring extends from the bonding portion of the first main electrode to a space between the pads” as taught by Sdrulla in the system of Kadoguchi in combination with Murasaki and Okura for the purpose of increasing contact density to maximize bandwidth and minimize device size.
Allowable Subject Matter
Claim 1 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 2, 4, 7, and 8 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the semiconductor device as recited in the claims of the instant application.
Regarding claim 1, the prior art of Kadoguchi et al. (US 8,884,411 B2) in combination with Nishida (US 10,937,727 B2) discloses a semiconductor device but fails to disclose the specific claims of the instant application e.g. the geometry and location of the roughened oxide film, specifically “a roughened region in which a roughened oxide film is formed to have a continuously roughened surface, excluding an inner surface of the recess, and
a non-roughened region, in which the roughened oxide film is not formed, on the inner surface of the recess.”
Claims 2 and 4 would be allowable by virtue of their dependence on claim 1.
Regarding claim 7, the prior art of Kadoguchi et al. (US 8,884,411 B2) in combination with Murasaki (US 20220216313 A1), Okura (US 20210028085 A1), and Sdrulla et al. (US 20230022394 A1) discloses a semiconductor device but fails to disclose the specific claims of the instant application e.g. the geometry and structure of the protective film, specifically “the protective film has a dummy opening continuous with the main opening and extending from the main opening in the second direction, and
the dummy wiring includes
an overlapping portion overlapping with the dummy opening in a plan view along the thickness direction, which is a peripheral portion of the base layer, and
an extension portion which is continuous with a portion of the base layer exposed from the main opening and is disposed in the dummy opening.”
Claim 8 would be allowable by virtue of its dependence on claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893