Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 03/03/2026. Currently, claims 1-13 and 26-37 are pending in the application. Claims 14-25 have been withdrawn and cancelled from consideration. Claims 26-37 have been added new.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7, 26 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al (US 20190295972 A1).
Regarding claim 1, Figures 1-14 of Tsai disclose a method of making a semiconductor device, comprising:
providing a semiconductor die (114, [0025]);
depositing an encapsulant (130, [0023]) over the semiconductor die to form a reconstituted wafer;
forming a first insulating layer (136, [0032]) over the reconstituted wafer;
forming a first dummy opening (Figure 9, dummy opening in between 114, for 142B in Figure 13) in the first insulating layer, wherein the encapsulant is exposed (in Figure 9) through the first dummy opening for an entire footprint of the first dummy opening; and
forming a first conductive layer (138, [0031]) on the first insulating layer including a first contact pad over the first dummy opening, wherein the first contact pad (138 in region 150) is formed directly on the encapsulant exposed in the first dummy opening.
Regarding claim 7, Figures 1-14 of Tsai disclose a method of making a semiconductor device, comprising:
providing a substrate (130, [0032]) comprising an insulating material;
forming a first insulating layer (136, [0032]) over the substrate;
forming a first opening (in region 150 for 138) in the first insulating layer, wherein the insulating material of the substrate is exposed (in Figure 9) in the first opening; and
forming a first conductive layer (138, [0031]) including a first contact pad (138) over the first opening.
Regarding claim 26, Figures 1-14 of Tsai disclose a method of making a semiconductor device, comprising:
providing a semiconductor die (114, [0029]);
depositing an encapsulant (130, [0030]) over the semiconductor die to form a reconstituted wafer;
forming a first insulating layer (136, [0034]) over the reconstituted wafer;
forming a first dummy opening (in region 150 for 138) in the first insulating layer, wherein the encapsulant is exposed (in Figure 9) through the first dummy opening;
forming a first conductive layer (138) on the first insulating layer including a first contact pad (138 in region 150, Figure 14A) over the first dummy opening;
forming a second insulating layer (140, [0036]) over the first conductive layer;
forming an opening (for 142, [0036]) in the second insulating layer to expose the first contact pad;
forming a second contact pad (142, [0037]) on the first contact pad and second insulating layer; and disposing a solder bump (144, [0037]) over the second contact pad.
Regarding claim 31, Figures 1-14 of Tsai disclose a method of making a semiconductor device, comprising:
providing a semiconductor die (114, [0024]);
depositing an encapsulant (130, [0030]) over the semiconductor die to form a reconstituted wafer;
forming a first insulating layer (136, [0033]) over the reconstituted wafer;
forming a first dummy opening (for 138 in region 150) in the first insulating layer, wherein the encapsulant is exposed (in Figure 9) through the first dummy opening;
forming a first conductive layer (138, [0034]) on the first insulating layer including a first contact pad (138) over the first dummy opening; and
disposing a solder bump (144, [0037]) over the first contact pad.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13, 26-32 and 34-37 are rejected under 35 U.S.C. 103 as being obvious over Huang et al (US 20150303158 A1) in view of Tsai et al (US 20190295972 A1).
Regarding claim 1, Figure 2 of Huang discloses a method of making a semiconductor device, comprising:
providing a semiconductor die (121, [0017]);
depositing an encapsulant (123+128, [0017]-[0018]) over the semiconductor die to form a reconstituted wafer;
forming a first insulating layer (212, [0027]) over the reconstituted wafer;
forming a first dummy opening (recess for 213 in 212, [0029]) in the first insulating layer; and
forming a first conductive layer (213, [0029]) on the first insulating layer including a first contact pad (portion of 213 in the opening in 212 is a contact pad) over the first dummy opening.
Huang does not teach wherein the encapsulant is exposed through the first dummy opening for an entire footprint for the first dummy opening, wherein the first contact pad is formed directly on the encapsulant exposed in the first dummy opening.
However, Tsai is a pertinent art which teaches a semiconductor package, wherein Figures 1-14 of Tsai disclose a method of making a semiconductor device by providing a semiconductor die (114, [0024]); depositing an encapsulant (130, [0030]) over the semiconductor die to form a reconstituted wafer; forming a first insulating layer (136, [0033]) over the reconstituted wafer; forming a first dummy opening (for 138 in region 150) in the first insulating layer, wherein the encapsulant is exposed (in Figure 9) through the first dummy opening; forming a first conductive layer (138, [0034]) on the first insulating layer including a first contact pad (138) over the first dummy opening; and disposing a solder bump (144) over the first contact pad and forming a second insulating layer (140, Figure 11, [0035]) over the first conductive layer (138). Tsai teaches that the region 150 ([0031]) is for adding an integrated component for higher integration density of variety of electronic components in a semiconductor package ([0002]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Huang by having a region wherein the encapsulant is exposed through the first dummy opening for an entire footprint for the first dummy opening, wherein the first contact pad is formed directly on the encapsulant exposed in the first dummy opening according to the teaching of Tsai in order to add variety of electronic components in a semiconductor package for higher integration ([0002], Tsai).
Regarding claim 2, Figure 2 of Huang discloses that the method of claim 1, further including: forming a second insulating layer (214, [0030]) over the first conductive layer (213); forming an opening (for 215 under 216) in the second insulating layer to expose the first contact pad; and forming a second contact pad (215 under 216) on the first contact pad and second insulating layer (214).
Regarding claim 3, Figure 2 of Huang discloses that the method of claim 1, further including: forming a redistribution layer (conductive layers on both sides of the die 121) over the reconstituted wafer; and forming the first insulating layer (212) over the redistribution layer.
Regarding claim 4, Figure 2 of Huang discloses that the method of claim 1, further including: forming a second insulating layer (214, [0030]) over the first insulating layer; and forming the first conductive layer (215, [0031]) over the second insulating layer.
Regarding claim 5, Figure 2 of Huang discloses that the method of claim 4, further including forming a second dummy opening (in 214 for 215 under 216) in the second insulating layer over the first dummy opening (recess in 212, directly under 216).
Regarding claim 6, Figure 2 of Huang discloses that the method of claim 1, further including forming the first dummy opening (considering the opening in 212 not under the bump 216) off-centered to the first contact pad (portion of 213 under 216, [0032]).
Regarding claim 7, Figure 2 of Huang discloses a method of making a semiconductor device, comprising:
providing a substrate (201, [0020]) comprising insulating material (123+128, [0017]-[0018]);
forming a first insulating layer (212, [0027]) over the substrate;
forming a first opening (for 213 in 212) in the first insulating layer; and
forming a first conductive layer (213, [0029]) including a first contact pad (portion of 213 directly under 216) over the first opening.
Huang does not teach that the insulating material of the substrate is exposed in the first opening.
However, Tsai is a pertinent art which teaches a semiconductor package, wherein Figures 1-14 of Tsai disclose a method of making a semiconductor device by providing a semiconductor die (114, [0024]); depositing an encapsulant (130, [0030]) over the semiconductor die to form a reconstituted wafer; forming a first insulating layer (136, [0033]) over the reconstituted wafer; forming a first dummy opening (for 138 in region 150) in the first insulating layer, wherein the encapsulant is exposed (in Figure 9) through the first dummy opening; forming a first conductive layer (138, [0034]) on the first insulating layer including a first contact pad (138) over the first dummy opening; and disposing a solder bump (144) over the first contact pad and forming a second insulating layer (140, Figure 11, [0035]) over the first conductive layer (138). Tsai teaches that the region 150 ([0031]) is for adding an integrated component for higher integration density of variety of electronic components in a semiconductor package ([0002]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Huang by having a region wherein the insulating material of the substrate is exposed in the first opening for making additional contact pad according to the teaching of Tsai in order to add variety of electronic components in a semiconductor package for higher integration ([0002], Tsai).
Regarding claim 8, Figure 2 of Huang discloses that the method of claim 7, further including: forming a second insulating layer (214, [0030]) over the first conductive layer (213); forming a second opening (in 214 under 216) in the second insulating layer over the first contact pad; and forming a second contact pad (215, [0032]) on the first contact pad and second insulating layer.
Regarding claim 9, Figure 2 of Huang discloses that the method of claim 7, further including: forming a redistribution layer (conductive layers on both sides of the die 121) over the substrate; and forming the first insulating layer (212) over the redistribution layer.
Regarding claim 10, Figure 2 of Huang discloses that the method of claim 7, further including: forming a second insulating layer (214, [0030]) over the first insulating layer; and forming the first conductive layer (215, [0032]) over the second insulating layer.
Regarding claim 11, Figure 2 of Huang discloses that the method of claim 10, further including forming a second opening (for 215 in 216) in the second insulating layer over the first opening.
Regarding claim 12, Figure 2 of Huang discloses that the method of claim 7, further including forming a second insulating layer (203) under the first insulating layer (212).
Regarding claim 13, Figure 2 of Huang discloses that the method of claim 7, further including forming the first opening (considering the opening in 212 not under 216) off-centered to the first contact pad (in 212 under 216).
Regarding claim 26, Figure 2 of Huang discloses a method of making a semiconductor device, comprising:
providing a semiconductor die (121, [0029]);
depositing an encapsulant (123+128, [0017]-[0018]) over the semiconductor die to form a reconstituted wafer;
forming a first insulating layer (212, [0028]) over the reconstituted wafer;
forming a first dummy opening (in 212 under 216) in the first insulating layer;
forming a first conductive layer (213, [0030]) on the first insulating layer (212) including a first contact pad (in opening 212 under 216) over the first dummy opening;
forming a second insulating layer (214, [0030]) over the first conductive layer;
forming an opening (in 214 under 216) in the second insulating layer (214) to expose the first contact pad;
forming a second contact pad (215, [0032]) on the first contact pad and second insulating layer; and disposing a solder bump (216, [0032]) over the second contact pad.
Huang does not teach that the encapsulant is exposed through the first dummy opening.
However, Tsai is a pertinent art which teaches a semiconductor package, wherein Figures 1-14 of Tsai disclose a method of making a semiconductor device by providing a semiconductor die (114, [0024]); depositing an encapsulant (130, [0030]) over the semiconductor die to form a reconstituted wafer; forming a first insulating layer (136, [0033]) over the reconstituted wafer; forming a first dummy opening (for 138 in region 150) in the first insulating layer, wherein the encapsulant is exposed (in Figure 9) through the first dummy opening; forming a first conductive layer (138, [0034]) on the first insulating layer including a first contact pad (138) over the first dummy opening; and disposing a solder bump (144) over the first contact pad and forming a second insulating layer (140, Figure 11, [0035]) over the first conductive layer (138). Tsai teaches that the region 150 ([0031]) is for adding an integrated component for higher integration density of variety of electronic components in a semiconductor package ([0002]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Huang by having a region wherein the encapsulant is exposed through the first dummy opening for making additional contact pad according to the teaching of Tsai in order to add variety of electronic components in a semiconductor package for higher integration ([0002], Tsai).
Regarding claim 27, Figure 2 of Huang discloses that the method of claim 26, further including: forming a redistribution layer (conductive layers around the middle portions) over the reconstituted wafer; and forming the first insulating layer (212) over the redistribution layer.
Regarding claim 28, Figure 2 of Huang discloses that the method of claim 26, further including forming a third insulating layer (203, [0021]) under the first insulating layer (212).
Regarding claim 29, Figure 2 of Huang discloses that the method of claim 26, further including forming a second dummy opening (under 216) in the second insulating layer over the first dummy opening.
Regarding claim 30, Figure 2 of Huang discloses that the method of claim 26, further including forming the first dummy opening off-centered to the first contact pad (considering opening in 212 not directly under 216 if off-centered).
Regarding claim 31, Figure 2 of Huang discloses a method of making a semiconductor device, comprising:
providing a semiconductor die (121, [0017]);
depositing an encapsulant (123+128, [0017]-[0018]) over the semiconductor die to form a reconstituted wafer;
forming a first insulating layer (212, [0028]) over the reconstituted wafer;
forming a first dummy opening (for 213 in 212 under 216) in the first insulating layer;
forming a first conductive layer (213, [0030]) on the first insulating layer including a first contact pad (213 in the opening of 212 under 216, [0029]) over the first dummy opening; and
disposing a solder bump (216, [0031]) over the first contact pad.
Huang does not teach that the encapsulant is exposed through the first dummy opening.
However, Tsai is a pertinent art which teaches a semiconductor package, wherein Figures 1-14 of Tsai disclose a method of making a semiconductor device by providing a semiconductor die (114, [0024]); depositing an encapsulant (130, [0030]) over the semiconductor die to form a reconstituted wafer; forming a first insulating layer (136, [0033]) over the reconstituted wafer; forming a first dummy opening (for 138 in region 150) in the first insulating layer, wherein the encapsulant is exposed (in Figure 9) through the first dummy opening; forming a first conductive layer (138, [0034]) on the first insulating layer including a first contact pad (138) over the first dummy opening; and disposing a solder bump (144) over the first contact pad and forming a second insulating layer (140, Figure 11, [0035]) over the first conductive layer (138). Tsai teaches that the region 150 ([0031]) is for adding an integrated component for higher integration density of variety of electronic components in a semiconductor package ([0002]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Huang by having a region wherein the encapsulant is exposed through the first dummy opening for making additional contact pad according to the teaching of Tsai in order to add variety of electronic components in a semiconductor package for higher integration ([0002], Tsai).
Regarding claim 32, Figure 2 of Huang discloses that the method of claim 31, further including: forming a second insulating layer (214, [0030]) over the first conductive layer (213); forming an opening (for 215 in 214) in the second insulating layer to expose the first contact pad ( 213 in 212); and forming a second contact pad (215, [0032]) on the first contact pad and second insulating layer (214).
Regarding claim 34, Figure 2 of Huang discloses that the method of claim 31, further including: forming a redistribution layer (conductive layers around the middle portion) over the reconstituted wafer; and forming the first insulating layer (212) over the redistribution layer.
Regarding claim 35, Figure 2 of Huang discloses that the method of claim 31, further including: forming a second insulating layer (214, [0030]) over the first insulating layer (212); and forming the first conductive layer (215) over the second insulating layer (214).
Regarding claim 36, Figure 2 of Huang discloses that the method of claim 35, further including forming a second dummy opening (for 215 in 214 under 216) in the second insulating layer over the first dummy opening (for 213 in 212 under 216).
Regarding claim 37, Figure 2 of Huang discloses that the method of claim 31, further including forming the first dummy opening off-centered to the first contact pad (considering opening in 212 not directly under 216 if off-centered).
Claim 33 is rejected under 35 U.S.C. 103 as being obvious over Huang et al (US 20150303158 A1) in view of Tsai et al (US 20190295972 A1) as applied to claim 32 above, and further in view of Choi (US 20140312512 A1).
Regarding claim 33, Figure 2 of Huang does not teach that the method of claim 32, further including reflowing the solder bump onto the second contact pad.
However, Choi is a pertinent art which teaches that the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps 140 (Figure 4. In some applications, bumps 140 are reflowed a second time to improve electrical contact to UBM 138. Bumps 140 can also be compression bonded to UBM 138. Bumps 140 represent one type of interconnect structure that can be formed over UBM 138 ([0043]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a method of reflowing the solder bump onto the second contact pad in the method of Huang according to the teaching of Choi in order to improve electrical contact ([0043] of Choi).
Response to Arguments
Applicant’s arguments/amendments regarding the rejection of claims 1-13 and 26-37, filed on 03/03/2026, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813