DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Amended claim 21 is directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
This application contains claims directed to the following patentably distinct species.
Species A, directed to the embodiment shown in Figure 4, claims 2-5 and 9-14, wherein the backside interconnect structures 208B are disposed between the device substrate 202 and the backside substrate 230. The backside substrate 230 has a plurality of vias 240 extending through it and electrically coupled to the backside interconnect structures 208B.
Species B, directed to the embodiment shown in Figure 5, claim 21, wherein a lower die 200-2 is coupled to an upper die 200-1. The lower die 200-2 includes a device substrate 260 and a plurality of frontside metallization layers 270. Vias extend through the device substrate 260 of the lower die 200-2 to electrically couple portions of upper die 200-1 to portions of the lower die 200-2.
The species are independent or distinct because they require materially different backside integration structures. In addition, these species are not obvious variants of each other based on the current record.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-27 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on June 30, 2026. Claims 1, 9 and 21-22 have been amended. No new claims have been added. Claims 7 and 15-20 have been
canceled. Claims 21-27 have been withdrawn. Currently, claims 1-6, 8-14 are pending.
Applicant’s amendment to claims 21 and 22 successfully overcomes the 112(b) rejection of claim 22 set forth in the previous Office Action.
Response to Arguments
Applicant’s amendment to claim 1 does not overcome the 112b rejection set forth in the previous Office Action. Although each of the components including the frontside interconnect, heat distribution layer and second substrate, are disposed or coupled to the front side of the first substrate, the claim does not specify whether the heat distribution layer is disposed between the first interconnect structures and the second substrate, above the second substrate, within the second substrate or laterally adjacent thereto. Accordingly, the relative arrangement of the recited components and thus the metes and bounds of the claimed semiconductor structure cannot be determined with reasonable clarity.
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim recites the frontside interconnect, heat distribution layer and second substrate, are disposed or coupled to the front side of the first substrate however, the claim does not specify whether the heat distribution layer is disposed between the first interconnect structures and the second substrate, above the second substrate, within the second substrate or laterally adjacent thereto. Accordingly, the relative arrangement of the recited components and thus the metes and bounds of the claimed semiconductor structure cannot be determined with reasonable clarity.
Claims 1-6 and 8 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0028752 A1; hereafter Huang) in view of Nelson et al. (US 2019/0122985 A1; hereafter Nelson).
Regarding claim 1, Huang teaches a semiconductor structure (see e.g., Figures 19-27), comprising:
a first substrate having a frontside and a backside opposite the frontside (see e.g., substrate 50 having a frontside and a backside opposite the frontside, Para [0020], Figure 19);
devices on the frontside (see e.g., nano-FETs formed on the frontside of the substrate 50, Para [0018], Figure 19);
first interconnect structures disposed on and coupled to the devices (see e.g., interconnect structure 120, has conductive features 122 including conductive lines and vias, formed over the second ILD 106, referred to as the frontside interconnect structure because it is formed on a front-side of the substrate 50 and coupled to the nano-FETs. The interconnect structure 120 may be electrically connected to gate contacts 114 and source/drain vias 112 to form functional circuits, Paras [0050], [0055], Figure 20);
a heat distribution layer (see e.g., 154B made of AlN, Para [0100], Figure 22) on the frontside (see e.g., 154B disposed on the frontside interconnect 120, Para [0100], Figure 22) and electrically isolated from the first interconnect structures (see e.g., 154A made of Al.sub.2O.sub.3 disposed between the frontside interconnect 120 and 154B, Para [0100], Figure 22), the heat distribution layer including a thermally conductive material (see e.g., 154B has a high thermal conductivity, Para [0100], Figure 22);
a second substrate coupled to the first substrate on the frontside; and (see e.g., carrier substrate 150 coupled to the frontside of the substrate 50, Para [0099], Figure 22)
second interconnect structures on the backside and coupled to the devices (see e.g., second interconnect structure 136, has conductive features 160 including conductive lines and vias, formed over the dielectric layer 126, referred to as the backside interconnect structure because it is formed on the backside of the substrate 50 and coupled to the nano-FETs, Paras [0065], [0067], Figure 26).
Huang does not explicitly teach
“wherein dimensions of the first interconnect structures increase from a first interconnect layer proximal to the first substrate to a second interconnect layer proximal to the heat distribution layer”.
In a similar field of endeavor Nelson teaches increasing the dimensions of interconnect structures as the interconnect layers extend away from a device layer 220. In Figure 5 Nelson discloses a frontside interconnect structure 250 disposed over a device layer 220 and including interconnect layers 2505, 2506 and 2507. The plurality of interconnects 250 have a dimension selected for a function, purpose or operation of the interconnect and the different ones of plurality of interconnects 250 are selected to perform different functions or operations. The thickness of the interconnect layers progressively increases in a direction away from the device layer 220 such that interconnect layer 2506 is thicker than interconnect layer 2505 and interconnect layer 2507 is thicker than interconnect layer 2506 (see e.g., Paras [0027], [0032]).
Therefore, it would have been obvious to one skilled dint he art at the time the invention was effectively filed to implement Nelson’s teachings of progressively increasing the dimensions of the frontside interconnect structure away from the device layer in the device of Huang in order to provide thicker upper-level interconnects having reduced electrical resistance and increased current carrying capability.
Regarding claim 6, Huang, as modified by Nelson, teaches the limitations of claim 1 as mentioned above. Huang further teaches
wherein the second substrate directly contacts the heat distribution layer (see e.g., the carrier substrate 150 is in direct contact with 154B, Paras [0062], [0100], Figure 22).
Regarding claim 8, Huang, as modified by Nelson, teaches the limitations of claim 1 as mentioned above. Huang further teaches
wherein the thermally conductive material includes at least one material selected from the group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, aluminum, copper, gallium, germanium, gold, iron, magnesium, nickel, platinum, silver, titanium, tungsten, and zinc (see e.g., 154B is made of aluminum nitride, Para [0100], Figure 22).
Claims 2-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0028752 A1; hereafter Huang) in view of Nelson et al. (US 2019/0122985 A1; hereafter Nelson) and further in view of Bhattacherjee et al. (US 2021/0265253 A1; hereafter Bhattacherjee).
Regarding claim 2, Huang, as modified by Nelson, teaches the limitations of claim 1 as mentioned above. Huang further teaches
further comprising:
a third substrate on the backside of the first substrate; and (see e.g., passivation layer 164 disposed on the backside interconnect structure 136, Para [0068], Figure 27)
a plurality of vias extending through the third substrate and coupled to the second interconnect structures (see e.g., UBMs 166 extending through the passivation layer 164 and are coupled to the backside interconnect structure 136, Paras [0068], [0069], Figure 27; Examiner’s interpretation: Although one UBM 166 is shown in the Figure 27 however, there would be other UBMs for purposes of providing external connections).
Although Huang teaches UBMs extending through the passivation layer 164, these functional elements could be implemented as vias, as explicitly taught by Bhattacherjee, where through-substrate vias (TSVs) 213 extend through the bulk material 210 and are connected to the electrical contacts 230 to facilitate external connection to electrical devices or internal connection to other substates.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bhattacherjee’s teachings of vias extending through a substrate into Huang’s passivation layer to provide robust vertical electrical connections.
Regarding claim 3, Huang, as modified by Nelson and Bhattacherjee, teaches the limitations of claim 2 as mentioned above. Huang further teaches
further comprising a plurality of conductive connectors each coupled to a corresponding one of the vias (see e.g., external connectors 168 are formed on the UBMs 166, Para [0068], Figure 27; Examiner’s interpretation: Although one external connector 168 is shown in the Figure 27 however, there would be other external connectors for purposes of providing external connections).
Regarding claim 5, Huang, as modified by Nelson and Bhattacherjee, teaches the limitations of claim 2 as mentioned above. Huang further teaches
wherein the third substrate includes at least one thermally conductive material selected from the group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, gallium, and germanium (see e.g., the passivation layer 164 is formed of materials such as silicon carbide, Para [0068], Figure 27).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0028752 A1; hereafter Huang) in view of Nelson et al. (US 2019/0122985 A1; hereafter Nelson) and Bhattacherjee et al. (US 2021/0265253 A1; hereafter Bhattacherjee) and further in view of Cheng et al. (US 10,854,530 B1; hereafter Cheng).
Regarding claim 4, Huang, as modified by Nelson and Bhattacherjee, teaches the limitations of claim 2 as mentioned above. Huang further teaches
wherein the heat distribution layer is a first heat distribution layer (see e.g., 154B disposed on the frontside interconnect 120, Para [0100], Figure 22),
Huang does not explicitly teach
“further comprising a second heat distribution layer between the second interconnect structures and the third substrate”.
In a similar field of endeavor Cheng teaches
further comprising a second heat distribution layer (see e.g., heat dissipation layer 142, Column 6, Lines 49-55, Figure 1) between the second interconnect structures (see e.g., metallization layers 118, Column 5, Lines 55-60, Figure 1) and the third substrate (see e.g., dielectric layer 126 for the chip 106/interlayer dielectric 128/substrate 114, Column 3, Lines 30-35, Column 4, Lines, 20-25, 43-45, Figure 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of further comprising a second heat distribution layer between the second interconnect structures and the third substrate in the device of Huang in order to achieve a predictable, improved result that is, enhanced heat dissipation and thermal management in a densely packed interconnection structure.
Claims 9-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0028752 A1; hereafter Huang) in view of Chung et al. (US 2021/0375861 A1; hereafter Chung) and Bhattacherjee et al. (US 2021/0265253 A1; hereafter Bhattacherjee).
Regarding claim 9, Huang teaches a semiconductor structure (see e.g., Figures 19-27), comprising:
a first substrate having a frontside and a backside opposite the frontside (see e.g., substrate 50 having a frontside and a backside opposite the frontside, Para [0020], Figure 19);
devices on the frontside (see e.g., nano-FETs formed on the frontside of the substrate 50, Para [0018], Figure 19);
first interconnect structures on the frontside and coupled to the devices (see e.g., interconnect structure 120, has conductive features 122 including conductive lines and vias, formed over the second ILD 106, referred to as the frontside interconnect structure because it is formed on a front-side of the substrate 50 and coupled to the nano-FETs. The interconnect structure 120 may be electrically connected to gate contacts 114 and source/drain vias 112 to form functional circuits, Paras [0050], [0055], Figure 20);
second interconnect structures on the backside and coupled to the devices (see e.g., second interconnect structure 136, has conductive features 160 including conductive lines and vias, formed over the dielectric layer 126, referred to as the backside interconnect structure because it is formed on the backside of the substrate 50 and coupled to the nano-FETs, Paras [0065], [0067], Figure 26);
a second substrate coupled to the backside such that the second interconnect structures are between the first substrate and the second substrate; and (see e.g., passivation layer 164 disposed on the backside interconnect structure 136 such that the backside interconnect structure 136 is between the substrate 50 and the passivation layer 164, Para [0068], Figure 27)
a via extending through the second substrate and coupled to the second interconnect structures (see e.g., UMBs 166 extend through the passivation layer 164 and are coupled to the backside interconnect structure 136, Para [0068], Figure 27).
Although Huang teaches UBMs extending through the passivation layer 164, these functional elements could be implemented as vias, as explicitly taught by Bhattacherjee, where through-substrate vias (TSVs) 213 extend through the bulk material 210 and are connected to the electrical contacts 230 to facilitate external connection to electrical devices or internal connection to other substates.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bhattacherjee’s teachings of vias extending through a substrate into Huang’s passivation layer to provide robust vertical electrical connections.
Huang does not explicitly teach
“wherein dimensions of the second interconnect structures increase from the first substrate to the second substrate”.
In a similar field of endeavor Chung teaches
wherein dimensions of the second interconnect structures increase from the first substrate to the second substrate (see e.g., first backside interconnect structure 166 and a second backside interconnect structure 136 disposed between the substrate 50 and the passivation layer 144. The first backside interconnect structure 166 can be formed with smaller pitches and critical dimensions than the second backside interconnect structure 136, which reduces device size and increases device density, Paras [0095], [0096], [0098], Figure 31C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chung’s teachings of wherein dimensions of the second interconnect structures increase from the first substrate to the second substrate in the device of Huang in order to reduce device size and increase device density.
Regarding claim 10, Huang, as modified by Chung and Bhattacherjee, teaches the limitations of claim 9 as mentioned above. Huang further teaches
further comprising:
a heat distribution layer over the first interconnect structures on the frontside; and (see e.g., 154B, made of AlN, disposed on the frontside interconnect 120, Para [0100], Figure 22)
a third substrate over the heat distribution layer and coupled to the frontside (see e.g., carrier substrate 150 coupled to the frontside of the substrate 50, Para [0099], Figure 22).
Regarding claim 11, Huang, as modified by Chung and Bhattacherjee, teaches the limitations of claim 10 as mentioned above. Huang further teaches
wherein the heat distribution layer and the second substrate each include at least one material selected from the group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, gallium, and germanium (see e.g., 154B is made of aluminum nitride and the passivation layer 164 is made of materials such as silicon carbide, Paras [0068], [0100], Figures 22, 27).
Regarding claim 12, Huang, as modified by Chung and Bhattacherjee, teaches the limitations of claim 9 as mentioned above. Huang further teaches
further comprising a conductive connector coupled to the via (see e.g., external connectors 168 are formed on the UBMs 166, Para [0068], Figure 27).
Regarding claim 14, Huang, as modified by Chung and Bhattacherjee, teaches the limitations of claim 9 as mentioned above. Huang further teaches
wherein the first interconnect structures include conductive lines and vias (see e.g., the frontside interconnect structure 120 has conductive features 122 which include conductive lines and vias interconnecting the layers of conductive lines.), and
While Huang does not explicitly teach that a density of the vias is about 1% to about 5%, Huang teaches that, “it should be appreciated that the interconnect structure 120 may include any number of conductive features disposed in any number of dielectric layers…..”.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize the number of vias in the interconnect layer as per device requirements e.g., to balance parasitic capacitance, resistance and mechanical reliability such as using different via densities in different parts of the layout, including densities that may fall within 1% to 5% range.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0028752 A1; hereafter Huang) in view of Chung et al. (US 2021/0375861 A1; hereafter Chung) and Bhattacherjee et al. (US 2021/0265253 A1; hereafter Bhattacherjee) and further in view of Cheng et al. (US 10,854,530 B1; hereafter Cheng).
Regarding claim 13, Huang, as modified by Chung and Bhattacherjee, teaches the limitations of claim 9 as mentioned above. Huang does not explicitly teach
“further comprising a bonding layer between the second interconnect structures and the second substrate”.
In a similar field of endeavor Cheng teaches
further comprising a bonding layer between the second interconnect structures and the second substrate (see e.g., passivation layer 132 (formed by bonding the two passivation layers 132 of chips 106 and 104 with an interface 134) positioned the metallization layer 118 of chip 104 and the dielectric 126/128 of chip 106, Column 4, Lines 57-65, Figures 1 and 4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of further comprising a bonding layer between the second interconnect structures and the second substrate in the device of Huang in order to improve structural adhesion, enhance thermal stability and reduce manufacturing defects between layers.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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