DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group 1, Species A, directed to claims 1-14 and new claims 21-27 in the reply filed on February 09, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 8 and 21-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim recites, “first interconnect structures on the frontside and coupled to the devices;… a heat distribution layer on the frontside and electrically isolated from the first interconnect structures… a second substrate coupled to the first substrate on the frontside;”, which is indefinite as there is an ambiguity in the ordering of these various layers.
Claims 2-6 and 8 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
Regarding claim 21, the claim recites, “a second substrate coupled to the first substrate” which is indefinite as it fails to specify whether the coupling occurs on the frontside or backside of the first substrate. Furthermore, it is unclear if the second substrate is physically disposed directly on the first substrate or on the first interconnect structure.
The claim further recites, “a third substrate on the backside of the first substrate” which is also indefinite. It is not clear whether this third substrate is disposed directly on the backside surface of the first substrate or to the second interconnect structure.
Claims 22-27 depend upon claim 21 and do not rectify the problem therefore, they are also rejected.
Regarding claim 22, the claim recites, “a heat distribution layer on the frontside and electrically isolated from the plurality of first interconnect structures” which is indefinite. It is unclear whether this heat distribution layer is disposed directly on the frontside surface of the first substrate or on the first interconnect structures.
Claim 23 depends upon claim 22 and does not rectify the problem therefore, it is also rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2022/0028752 A1; hereafter Huang).
Regarding claim 1, Huang teaches a semiconductor structure (see e.g., Figures 19-27), comprising:
a first substrate having a frontside and a backside opposite the frontside (see e.g., substrate 50 having a frontside and a backside opposite the frontside, Para [0020], Figure 19);
devices on the frontside (see e.g., nano-FETs formed on the frontside of the substrate 50, Para [0018], Figure 19);
first interconnect structures on the frontside and coupled to the devices (see e.g., interconnect structure 120, has conductive features 122 including conductive lines and vias, formed over the second ILD 106, referred to as the frontside interconnect structure because it is formed on a front-side of the substrate 50 and coupled to the nano-FETs. The interconnect structure 120 may be electrically connected to gate contacts 114 and source/drain vias 112 to form functional circuits, Paras [0050], [0055], Figure 20);
a heat distribution layer (see e.g., 154B made of AlN, Para [0100], Figure 22) on the frontside (see e.g., 154B disposed on the frontside interconnect 120, Para [0100], Figure 22) and electrically isolated from the first interconnect structures (see e.g., 154A made of Al.sub.2O.sub.3 disposed between the frontside interconnect 120 and 154B, Para [0100], Figure 22), the heat distribution layer including a thermally conductive material (see e.g., 154B has a high thermal conductivity, Para [0100], Figure 22);
a second substrate coupled to the first substrate on the frontside; and (see e.g., carrier substrate 150 coupled to the frontside of the substrate 50, Para [0099], Figure 22)
second interconnect structures on the backside and coupled to the devices (see e.g., second interconnect structure 136, has conductive features 160 including conductive lines and vias, formed over the dielectric layer 126, referred to as the backside interconnect structure because it is formed on the backside of the substrate 50 and coupled to the nano-FETs, Paras [0065], [0067], Figure 26).
Regarding claim 6, Huang, as referred in claim 1, further teaches
wherein the second substrate directly contacts the heat distribution layer (see e.g., the carrier substrate 150 is in direct contact with 154B, Paras [0062], [0100], Figure 22).
Regarding claim 8, Huang, as referred in claim 1, further teaches
wherein the thermally conductive material includes at least one material selected from the group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, aluminum, copper, gallium, germanium, gold, iron, magnesium, nickel, platinum, silver, titanium, tungsten, and zinc (see e.g., 154B is made of aluminum nitride, Para [0100], Figure 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5, 9-12, 14, 21-22 and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0028752 A1; hereafter Huang) in view of Bhattacherjee et al. (US 2021/0265253 A1; hereafter Bhattacherjee).
Regarding claim 2, Huang, as referred in claim 1, further teaches
further comprising:
a third substrate on the backside of the first substrate; and (see e.g., passivation layer 164 disposed on the backside interconnect structure 136, Para [0068], Figure 27)
a plurality of vias extending through the third substrate and coupled to the second interconnect structures (see e.g., UBMs 166 extending through the passivation layer 164 and are coupled to the backside interconnect structure 136, Paras [0068], [0069], Figure 27; Examiner’s interpretation: Although one UBM 166 is shown in the Figure 27 however, there would be other UBMs for purposes of providing external connections).
Although Huang teaches UBMs extending through the passivation layer 164, these functional elements could be implemented as vias, as explicitly taught by Bhattacherjee, where through-substrate vias (TSVs) 213 extend through the bulk material 210 and are connected to the electrical contacts 230 to facilitate external connection to electrical devices or internal connection to other substates.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bhattacherjee’s teachings of vias extending through a substrate into Huang’s passivation layer to provide robust vertical electrical connections.
Regarding claim 3, Huang, as modified by Bhattacherjee, teaches the limitations of claim 2 as mentioned above. Huang further teaches
further comprising a plurality of conductive connectors each coupled to a corresponding one of the vias (see e.g., external connectors 168 are formed on the UBMs 166, Para [0068], Figure 27; Examiner’s interpretation: Although one external connector 168 is shown in the Figure 27 however, there would be other external connectors for purposes of providing external connections).
Regarding claim 5, Huang, as modified by Bhattacherjee, teaches the limitations of claim 2 as mentioned above. Huang further teaches
wherein the third substrate includes at least one thermally conductive material selected from the group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, gallium, and germanium (see e.g., the passivation layer 164 is formed of materials such as silicon carbide, Para [0068], Figure 27).
Regarding claim 9, Huang teaches a semiconductor structure (see e.g., Figures 19-27), comprising:
a first substrate having a frontside and a backside opposite the frontside (see e.g., substrate 50 having a frontside and a backside opposite the frontside, Para [0020], Figure 19);
devices on the frontside (see e.g., nano-FETs formed on the frontside of the substrate 50, Para [0018], Figure 19);
first interconnect structures on the frontside and coupled to the devices (see e.g., interconnect structure 120, has conductive features 122 including conductive lines and vias, formed over the second ILD 106, referred to as the frontside interconnect structure because it is formed on a front-side of the substrate 50 and coupled to the nano-FETs. The interconnect structure 120 may be electrically connected to gate contacts 114 and source/drain vias 112 to form functional circuits, Paras [0050], [0055], Figure 20);
second interconnect structures on the backside and coupled to the devices (see e.g., second interconnect structure 136, has conductive features 160 including conductive lines and vias, formed over the dielectric layer 126, referred to as the backside interconnect structure because it is formed on the backside of the substrate 50 and coupled to the nano-FETs, Paras [0065], [0067], Figure 26);
a second substrate coupled to the backside such that the second interconnect structures are between the first substrate and the second substrate; and (see e.g., passivation layer 164 disposed on the backside interconnect structure 136 such that the backside interconnect structure 136 is between the substrate 50 and the passivation layer 164, Para [0068], Figure 27)
a via extending through the second substrate and coupled to the second interconnect structures (see e.g., UMBs 166 extend through the passivation layer 164 and are coupled to the backside interconnect structure 136, Para [0068], Figure 27).
Although Huang teaches UBMs extending through the passivation layer 164, these functional elements could be implemented as vias, as explicitly taught by Bhattacherjee, where through-substrate vias (TSVs) 213 extend through the bulk material 210 and are connected to the electrical contacts 230 to facilitate external connection to electrical devices or internal connection to other substates.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bhattacherjee’s teachings of vias extending through a substrate into Huang’s passivation layer to provide robust vertical electrical connections.
Regarding claim 10, Huang, as modified by Bhattacherjee, teaches the limitations of claim 9 as mentioned above. Huang further teaches
further comprising:
a heat distribution layer over the first interconnect structures on the frontside; and (see e.g., 154B, made of AlN, disposed on the frontside interconnect 120, Para [0100], Figure 22)
a third substrate over the heat distribution layer and coupled to the frontside (see e.g., carrier substrate 150 coupled to the frontside of the substrate 50, Para [0099], Figure 22).
Regarding claim 11, Huang, as modified by Bhattacherjee, teaches the limitations of claim 10 as mentioned above. Huang further teaches
wherein the heat distribution layer and the second substrate each include at least one material selected from the group consisting of silicon, carbon nanotubes, carbon fibers, diamond, boron nitride, titanium nitride, titanium oxide, silicon carbide, aluminum nitride, beryllium oxide, gallium, and germanium (see e.g., 154B is made of aluminum nitride and the passivation layer 164 is made of materials such as silicon carbide, Paras [0068], [0100], Figures 22, 27).
Regarding claim 12, Huang, as modified by Bhattacherjee, teaches the limitations of claim 9 as mentioned above. Huang further teaches
further comprising a conductive connector coupled to the via (see e.g., external connectors 168 are formed on the UBMs 166, Para [0068], Figure 27).
Regarding claim 14, Huang, as modified by Bhattacherjee, teaches the limitations of claim 9 as mentioned above. Huang further teaches
wherein the first interconnect structures include conductive lines and vias (see e.g., the frontside interconnect structure 120 has conductive features 122 which include conductive lines and vias interconnecting the layers of conductive lines.), and
While Huang does not explicitly teach that a density of the vias is about 1% to about 5%, Huang teaches that, “it should be appreciated that the interconnect structure 120 may include any number of conductive features disposed in any number of dielectric layers…..”.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize the number of vias in the interconnect layer as per device requirements e.g., to balance parasitic capacitance, resistance and mechanical reliability such as using different via densities in different parts of the layout, including densities that may fall within 1% to 5% range.
Regarding claim 21, Huang teaches a semiconductor structure (see e.g., Figures 19-27), comprising:
a first substrate having a frontside and a backside opposite the frontside (see e.g., substrate 50 having a frontside and a backside opposite the frontside, Para [0020], Figure 19);
a plurality of devices disposed on the frontside (see e.g., nano-FETs formed on the frontside of the substrate 50, Para [0018], Figure 19);
a plurality of first interconnect structures on the frontside and coupled to the plurality of devices (see e.g., interconnect structure 120, has conductive features 122 including conductive lines and vias, formed over the second ILD 106, referred to as the frontside interconnect structure because it is formed on a front-side of the substrate 50 and coupled to the nano-FETs. The interconnect structure 120 may be electrically connected to gate contacts 114 and source/drain vias 112 to form functional circuits, Paras [0050], [0055], Figure 20);
a second substrate coupled to the first substrate (see e.g., carrier substrate 150 coupled to the frontside of the substrate 50, Para [0099], Figure 22);
a plurality of second interconnect structures on the backside and coupled to the plurality of devices (see e.g., second interconnect structure 136, has conductive features 160 including conductive lines and vias, formed over the dielectric layer 126, referred to as the backside interconnect structure because it is formed on the backside of the substrate 50 and coupled to the nano-FETs, Paras [0065], [0067], Figure 26;
a third substrate on the backside of the first substrate; and (see e.g., passivation layer 164 disposed on the backside interconnect structure 136 such that the backside interconnect structure 136 is between the substrate 50 and the passivation layer 164, Para [0068], Figure 27)
a plurality of vias extending through the third substrate and coupled to the plurality of second interconnect structures (see e.g., UMBs 166 extend through the passivation layer 164 and are coupled to the backside interconnect structure 136, Para [0068], Figure 27; Examiner’s interpretation: Although one UMB 166 is shown in the Figure 27 however, there would be other UMBs for purposes of providing external connections).
Although Huang teaches UBMs extending through the passivation layer 164, these functional elements could be implemented as vias, as explicitly taught by Bhattacherjee, where through-substrate vias (TSVs) 213 extend through the bulk material 210 and are connected to the electrical contacts 230 to facilitate external connection to electrical devices or internal connection to other substates.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bhattacherjee’s teachings of vias extending through a substrate into Huang’s passivation layer to provide robust vertical electrical connections.
Regarding claim 22, Huang, as modified by Bhattacherjee, teaches the limitations of claim 21 as mentioned above. Huang further teaches
further comprising a heat distribution layer (see e.g., 154B made of AlN, Para [0100], Figure 22) on the frontside (see e.g., 154B disposed on the frontside interconnect 120, Para [0100], Figure 22) and electrically isolated from the plurality of first interconnect structures (see e.g., 154A made of Al.sub.2O.sub.3 disposed between the frontside interconnect 120 and 154B, Para [0100], Figure 22), the heat distribution layer including a thermally conductive material (see e.g., 154B has a high thermal conductivity, Para [0100], Figure 22).
Regarding claim 24, Huang, as modified by Bhattacherjee, teaches the limitations of claim 21 as mentioned above. Huang further teaches
further comprising a via extending through the second substrate and coupled to the plurality of second interconnect structures (see e.g., UBMs 166 extending through the passivation layer 164 and are coupled to the backside interconnect structure 136, Paras [0068], [0069], Figure 27).
Although Huang teaches UBMs extending through the passivation layer 164, these functional elements could be implemented as vias, as explicitly taught by Bhattacherjee, where through-substrate vias (TSVs) 213 extend through the bulk material 210 and are connected to the electrical contacts 230 to facilitate external connection to electrical devices or internal connection to other substates.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bhattacherjee’s teachings of vias extending through a substrate into Huang’s passivation layer to provide robust vertical electrical connections.
Regarding claim 25, Huang, as modified by Bhattacherjee, teaches the limitations of claim 21 as mentioned above. Huang further teaches
wherein the plurality of first interconnect structures comprise conductive lines and vias (see e.g., the frontside interconnect structure 120 has conductive features 122 which include conductive lines and vias interconnecting the layers of conductive lines.), and
While Huang does not explicitly teach that a density of the vias is about 1% to about 5%, Huang teaches that, “it should be appreciated that the interconnect structure 120 may include any number of conductive features disposed in any number of dielectric layers…..”.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize the number of vias in the interconnect layer as per device requirements e.g., to balance parasitic capacitance, resistance and mechanical reliability such as using different via densities in different parts of the layout, including densities that may fall within 1% to 5% range.
Regarding claim 26, Huang, as modified by Bhattacherjee, teaches the limitations of claim 21 as mentioned above. Huang further teaches
further comprising a plurality of conductive connectors each coupled to a corresponding one of the plurality of vias (see e.g., external connectors 168 are formed on the UBMs 166; Examiner’s interpretation: Although one external connector 168 is shown in the figure however, there would be other external connectors for purposes of providing external connections, Para [0068], Figure 27).
Claims 4, 13 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0028752 A1; hereafter Huang) in view of Bhattacherjee et al. (US 2021/0265253 A1; hereafter Bhattacherjee) and further in view of Cheng et al. (US 10,854,530 B1; hereafter Cheng).
Regarding claim 4, Huang, as modified by Bhattacherjee, teaches the limitations of claim 2 as mentioned above. Huang further teaches
wherein the heat distribution layer is a first heat distribution layer (see e.g., 154B disposed on the frontside interconnect 120, Para [0100], Figure 22),
Huang does not explicitly teach
“further comprising a second heat distribution layer between the second interconnect structures and the third substrate”.
In a similar field of endeavor Cheng teaches
further comprising a second heat distribution layer (see e.g., heat dissipation layer 142, Column 6, Lines 49-55, Figure 1) between the second interconnect structures (see e.g., metallization layers 118, Column 5, Lines 55-60, Figure 1) and the third substrate (see e.g., dielectric layer 126 for the chip 106/interlayer dielectric 128/substrate 114, Column 3, Lines 30-35, Column 4, Lines, 20-25, 43-45, Figure 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of further comprising a second heat distribution layer between the second interconnect structures and the third substrate in the device of Huang in order to achieve a predictable, improved result that is, enhanced heat dissipation and thermal management in a densely packed interconnection structure.
Regarding claim 13, Huang, as modified by Bhattacherjee, teaches the limitations of claim 9 as mentioned above. Huang does not explicitly teach
“further comprising a bonding layer between the second interconnect structures and the second substrate”.
In a similar field of endeavor Cheng teaches
further comprising a bonding layer between the second interconnect structures and the second substrate (see e.g., passivation layer 132 (formed by bonding the two passivation layers 132 of chips 106 and 104 with an interface 134) positioned the metallization layer 118 of chip 104 and the dielectric 126/128 of chip 106, Column 4, Lines 57-65, Figures 1 and 4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of further comprising a bonding layer between the second interconnect structures and the second substrate in the device of Huang in order to improve structural adhesion, enhance thermal stability and reduce manufacturing defects between layers.
Regarding claim 23, Huang, as modified by Bhattacherjee, teaches the limitations of claim 22 as mentioned above. Huang does not explicitly teach
“further comprising a bonding layer disposed on the heat distribution layer”.
In a similar field of endeavor Cheng teaches
further comprising a bonding layer disposed on the heat distribution layer (see e.g., chip 102 is bonded to carrier substrate 108 by a passivation layer 132. This passivation layer 132 is disposed on the heat distribution layer 144 that is, it is in between the heat dissipation layer 144 and the carrier substrate 108, Column 4, Lines 57-65, Figures 1 and 4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of further comprising a bonding layer disposed on the heat distribution layer in the device of Huang in order to improve the interfacial adhesion between the heat distribution layer and the substrate and enhance overall structural integrity and thermal reliability of the semiconductor package.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2022/0028752 A1; hereafter Huang) in view of Bhattacherjee et al. (US 2021/0265253 A1; hereafter Bhattacherjee) and further in view of Chang et al. (US 2021/0376155 A1; hereafter Chang).
Regarding claim 27, Huang, as modified by Bhattacherjee, teaches the limitations of claim 21 as mentioned above. Huang further teaches
wherein …. the third substrate include at least one material selected from the group consisting of germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP (see e.g., the passivation layer 164 may include materials such as silicon carbide, Para [0068], Figure 27).
Huang does not explicitly teach
“wherein the first substrate …. include at least one material selected from the group consisting of germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP”.
In a similar field of endeavor Chang teaches
wherein the first substrate …. include at least one material selected from the group consisting of germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP (see e.g., substrate 110 can be semiconductor-on-insulator (SOI) substrate or the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof., Para [0016], Figure 30).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chang’s teachings of wherein the first substrate …. include at least one material selected from the group consisting of germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP in the device of Huang as these are standard alternative materials for high performance semiconductor devices.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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