DETAILED ACTION
Election/Restrictions
Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/06/2026.
Applicant has also added claims 21-33 which are drawn to figures 2A-2C and 5A-5C. However, claims 7 and 32 are drawn to an embodiment having a dual-channel transistor structure which is a species drawn to figure 7B as disclosed in ¶0118 of the applicant’s specification. Therefore, claims 7 and 32 will not be considered in this office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/05/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 28, 29 and 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HSIAO et al. (US 20220336576 A1), hereinafter “Hsiao.”
Re: Claim 1, Hsiao discloses a semiconductor device (See Fig. 1A: source 15S, drain 15D, gate labeled “Word Line”; ¶0020: FET’s disposed over the substrate), comprising:
a plurality of back end dielectric layers (Fig. 1A: ¶0021: multiple wiring layers Mx are formed over the FETs… wiring layers includes an ILD or IMD layer, a metal layer and a via connected to the metal layer in some embodiments); and
a memory cell structure (Fig. 1A: MIM capacitors 100; ¶0016: semiconductor device includes a volatile memory cell; ¶0063: The MIM capacitor includes: electrodes including one or more first electrodes and one or more second electrodes; and one or more insulating layers disposed between adjacent electrodes), in the plurality of back end dielectric layers (See Figs. 2-7 show various stages of a sequential manufacturing operation; ¶0018: MIM capacitors 100, ILD or IMD layer 40; ¶0022: insulating layer 108 … ILD layers if the MIM capacitors is disposed between the ILD layer 40 and ILD layer 50. As shown in FIG. 1A, an ILD layer 30 is formed below the ILD layer 40...), comprising:
a transistor structure (Fig. 1A: gate 20, source 15S and drain 15D; ¶0025: gate electrodes 20 of the transistors function as a word line WL and a complementary world line WL; ¶0064: a first transistor and a second transistor which are disposed over a substrate); and
a capacitor structure (Fig. 1A: first and second MIM capacitors 102 and 104; Fig. 20A shows an embodiment having a first MIM capacitor with 3 electrode layers 112, 135, and 152 as well as layers in between which include layers 120 and 140; See ¶0050), above the transistor structure (¶0061: MIM capacitors are formed in the ILD layer above the switching transistors of a DRAM structure), comprising:
a first bottom electrode layer (Fig. 20A: electrode 112);
a second bottom electrode layer over the first bottom electrode layer (Fig. 20A: electrode 135);
a hydrogen absorption layer between the first bottom electrode layer and the second bottom electrode layer (Fig. 20A: insulating layer 120 over the first bottom electrode 112; ¶0038: as shown in FIGS. 11A and 11B, a first insulating layer 120 is formed over the first data storage electrodes 112 and 114… the first insulating layer 120 includes one or more layers of a metal oxide or a silicate of Hf, Al, Zr, combinations thereof, and multi-layers thereof… Other suitable materials include La, Mg, Ba, Ti, Pb, Zr, in the form of metal oxides, metal alloy oxides, and combinations thereof; In other words, Hsiao discloses using a metal oxide including an oxide of Titanium, i.e., TiOx which claim 3 discloses is a metal capable of absorbing hydrogen.);
a dielectric layer over the second bottom electrode layer (Fig. 20A: second insulating layer 140 over second bottom electrode layer 135; ¶0038: In some embodiments, the first insulating layer 120 includes one or more high-k dielectric layers; ¶0041: second insulating layer 140… In some embodiments, the configuration of the second insulating layer 140 is the same as the configuration of the first insulating layer 120; In other words, an embodiment may have a TiOx layer 120 and may also have a high-k dielectric on layer 140); and
a top electrode layer over the dielectric layer (Fig. 20A: third conductive layer 152 over second insulating layer 140; ¶0043: the third conductive layer 150 is patterned into a second data storage electrode 152 for the first MIM capacitor 102.).
Re: Claim 2, Hsiao discloses the semiconductor device of claim 1, and also
wherein the hydrogen absorption layer comprises one or more metal-oxide materials (Fig. 20A: layer 120; ¶0038: …a first insulating layer 120 is formed over the first data storage electrodes 112 and 114… the first insulating layer 120 includes one or more layers of a metal oxide … Other suitable materials include La, Mg, Ba, Ti, Pb, Zr, in the form of metal oxides, metal alloy oxides, and combinations thereof.).
Re: Claim 3, Hsiao discloses the semiconductor device of claim 1, and also
wherein the hydrogen absorption layer comprises at least one of:
an indium oxide (InxOy), a titanium oxide (TiOx), an indium tin oxide (ITO), a cerium oxide (CeOx), a zinc oxide (ZnO), or an indium gallium zinc oxide (IGZO) (¶0038: Other suitable materials include … Ti, … in the form of metal oxides, metal alloy oxides, i.e., TiOx).
Re: Claim 4, Hsiao discloses the semiconductor device of claim 1, and also
wherein a thickness of the hydrogen absorption layer is included in a range of approximately 1 nanometer to approximately 100 nanometers (¶0038: first insulating layer 120 has a thickness in a range from about 1 nm to about 10 nm).
Re: Claim 5, Hsiao discloses the semiconductor device of claim 1, and also
wherein the capacitor structure comprises a deep trench capacitor structure (Fig. 3: trench 42; ¶0030: as shown in FIG. 4, stacked layers of conductive material and insulating material are formed in the trenches and over the upper surface of the second ILD layer 40); and
wherein the hydrogen absorption layer conforms to a profile of the deep trench capacitor structure (Fig. 2 shows insulation layer 120 which conforms to the deep trench profile.).
Re: Claim 28, Hsiao discloses a semiconductor device (See Fig. 1A: source 15S, drain 15D, gate labeled “Word Line”; ¶0020: FET’s disposed over the substrate), comprising:
a memory cell structure (Fig. 1A: semiconductor device includes MIM capacitors 100), comprising:
a transistor structure (Fig. 1A: gate 20, source 15S and drain 15D; ¶0025: gate electrodes 20 of the transistors function as a word line WL and a complementary world line WL; ¶0064: a first transistor and a second transistor which are disposed over a substrate); and
a capacitor structure, above the transistor structure (Fig. 1A: capacitors 100 over 20, 15S and 15D), comprising:
a first bottom electrode layer disposed on sidewalls and a bottom surface of a recess in a passivation layer (Fig. 3: first trench 42 and second trench 44 formed in ILD 40; Fig. 20A: electrode 112; ¶0029: the first and second ILD layers 30 and 40 include one or more layers of silicon oxide, SiON, SiOCN, SiCN, SiOC, an organic material, a low-k dielectric material, or an extreme low-k dielectric material…as shown in FIG. 3, a first trench 42 and a second trench 44 are formed in the second ILD layer 40; Note: applicant’s specification states that the passivation may include SiON, for example.);
a hydrogen absorption layer disposed on sidewalls and a bottom portion of the first bottom electrode layer (Fig. 20A: insulating layer 120 over the first bottom electrode 112; ¶0038: as shown in FIGS. 11A and 11B, a first insulating layer 120 is formed over the first data storage electrodes 112 and 114… the first insulating layer 120 includes one or more layers of a metal oxide or a silicate of Hf, Al, Zr, combinations thereof, and multi-layers thereof… Other suitable materials include La, Mg, Ba, Ti, Pb, Zr, in the form of metal oxides, metal alloy oxides, and combinations thereof; In other words, Hsiao discloses using a metal oxide including an oxide of Titanium, i.e., TiOx which claim 3 discloses is a metal capable of absorbing hydrogen.);
a second bottom electrode layer disposed on sidewalls and a bottom portion of the hydrogen absorption layer (Fig. 20A: electrode 135);
a dielectric layer over the second bottom electrode layer (Fig. 20A: layer 140 over electrode 135; ¶0041: second insulating layer 140… In some embodiments, the configuration of the second insulating layer 140 is the same as the configuration of the first insulating layer 120); and
a top electrode layer over the dielectric layer (Fig. 20A: electrode 152).
Re: Claim 29, Hsiao discloses the semiconductor device of claim 28, and also
wherein the hydrogen absorption layer comprises one or more metal-oxide materials (Fig. 20A: layer 120; ¶0038: …a first insulating layer 120 is formed over the first data storage electrodes 112 and 114… the first insulating layer 120 includes one or more layers of a metal oxide … Other suitable materials include La, Mg, Ba, Ti, Pb, Zr, in the form of metal oxides, metal alloy oxides, and combinations thereof.).
Re: Claim 33, Hsiao discloses the semiconductor device of claim 28, and also
wherein a thickness of the absorption layer is included in a range of approximately 1 nanometer to approximately 100 nanometers (¶0038: first insulating layer 120 has a thickness in a range from about 1 nm to about 10 nm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 21-27, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over HSIAO et al. (US 20220336576 A1) in view of SHARMA et al. (US 20200343379 A1), hereinafter “Sharma.”
Re: Claim 6, Hsiao discloses the semiconductor device of claim 1.
Hsiao further discloses wherein the transistor structure comprises a single-channel transistor structure that includes (Fig. 1A: Source 15S and drain 15D and gate labeled “Word Line” are connected to structure 62 which connects to capacitor 102 which make up a single-channel):
a gate structure (Fig. 1A: gate labeled “Word Line”);
However, Hsiao does not specifically disclose
a channel layer over the gate structure;
a first source/drain region on the channel layer and directly above the gate structure; and
a second source/drain region on the channel layer and directly above the gate structure.
In a similar field of endeavor, Sharma discloses
a channel layer over the gate structure (Fig. 2: channel 209 is located over gate 205);
a first source/drain region on the channel layer and directly above the gate structure (Fig. 2: source area 291 is located on channel 209 and directly above gate 205); and
a second source/drain region on the channel layer and directly above the gate structure (Fig. 2: drain area 293 is located on channel 209 and directly above gate 205).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to substitute the encapsulated TFT taught by Sharma into the transistor structure of Hsiao because both references disclose known switching transistors suitable for use in a 1T-1C DRAM memory cell (Sharma, ¶0064: 1T1C configuration). Sharma provides explicit motivation by teaching that its metallic and insulating encapsulation layers protect the TFT against subsequence process operations so that the TFTs may be protected from hydrogen or moisture exposure, or oxygen loss which can improve subthreshold swing and have better ON/OFF ratio (Sharma, ¶0012). Also see MPEP 2144.06(II): Substituting Equivalents Know For The Same Purpose.
Re: Claim 21, Hsiao discloses a semiconductor device (See Fig. 1A: source 15S, drain 15D, gate labeled “Word Line” and 20; ¶0020: FET’s disposed over the substrate), comprising:
a gate structure of a transistor structure (Fig. 1A: gate labeled “Word Line”);
a gate dielectric layer of the transistor structure over the gate structure (Fig. 2: ILD layer 30 which is over the gate structure: ¶0029: the first and second ILD layers 30 and 40 include one or more layers of silicon oxide, SiON, SiOCN, SiCN, SiOC, an organic material, a low-k dielectric material, or an extreme low-k dielectric material.);
…
…
a source/drain interconnect structure on a source/drain region of the plurality of source/drain regions (Fig. 1A: lower wiring patterns 60; ¶0028: lower wiring patterns 60 including the first, second and third lower wiring patterns 62, 64 and 65 are formed over the FETs);
a bottom electrode, of a capacitor structure (Fig. 20A: electrode 112 of capacitor), on the source/drain interconnect structure (Fig. 20A: electrode 112 on via electrode 72, i.e., S/D interconnect structure; See ¶0023: As shown in FIG. 1A, the data storage electrodes of the MIM capacitors 102 and 104 are connected to a first via electrode 72);
a hydrogen absorption layer of the capacitor structure over the bottom electrode (Fig. 20A: insulating layer 120 over the first bottom electrode 112; ¶0038: as shown in FIGS. 11A and 11B, a first insulating layer 120 is formed over the first data storage electrodes 112 and 114… the first insulating layer 120 includes one or more layers of a metal oxide … Other suitable materials include …Ti, Pb, Zr, in the form of metal oxides, metal alloy oxides, and combinations thereof; In other words, Hsiao discloses using a metal oxide including an oxide of Titanium, i.e., TiOx which claim 3 discloses is a metal capable of absorbing hydrogen.); and
a top electrode of the capacitor structure over the hydrogen absorption layer (Fig. 20A: electrode 152 over layer 120).
However, Hsiao does not specifically disclose a channel layer of the transistor structure on the gate dielectric layer; a plurality of source/drain regions of the transistor structure on the channel layer;
In a similar field of endeavor, Sharma discloses
a channel layer of the transistor structure on the gate dielectric layer (Fig. 2: channel 209 on gate dielectric layer 207);
a plurality of source/drain regions of the transistor structure on the channel layer (Fig. 2: S/D regions 293 and 291 on channel layer 209);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to substitute the encapsulated TFT taught by Sharma into the transistor structure of Hsiao because both references disclose known switching transistors suitable for use in a 1T-1C DRAM memory cell (Sharma, ¶0064: 1T1C configuration). Sharma provides explicit motivation by teaching that its metallic and insulating encapsulation layers protect the TFT against subsequence process operations so that the TFTs may be protected from hydrogen or moisture exposure, or oxygen loss which can improve subthreshold swing and have better ON/OFF ratio (Sharma, ¶0012). Also see MPEP 2144.06(II): Substituting Equivalents Know For The Same Purpose.
Re: Claim 22, the combination of Hsiao and Sharma discloses the semiconductor device of claim 21.
Hsiao further discloses wherein the bottom electrode comprises:
a first bottom electrode layer on the source/drain interconnect structure (Fig. 20A: electrode 112), wherein the hydrogen absorption layer is on the first bottom electrode layer (Fig. 20A: insulating layer 120 over the first bottom electrode 112; ¶0038: …the first insulating layer 120 includes one or more layers of a metal oxide … Other suitable materials include La, Mg, Ba, Ti, Pb, Zr, in the form of metal oxides, metal alloy oxides, and combinations thereof; In other words, Hsiao discloses using a metal oxide including an oxide of Titanium, i.e., TiOx which claim 3 discloses is a metal capable of absorbing hydrogen.); and
a second bottom electrode layer on the hydrogen absorption layer (Fig. 20A: electrode 135 on layer 120).
Re: Claim 23, the combination of Hsiao and Sharma discloses the semiconductor device of claim 22.
Hsiao further discloses further comprising a high dielectric constant (high-k) dielectric layer on the second bottom electrode layer (Fig. 20A: electrode 135, i.e., second bottom electrode layer, is over underneath layer 140 which may be a high-k dielectric layer; ¶0038: In some embodiments, the first insulating layer 120 includes one or more high-k dielectric layers; ¶0041: second insulating layer 140… In some embodiments, the configuration of the second insulating layer 140 is the same as the configuration of the first insulating layer 120; In other words, an embodiment may have a TiOx layer 120 and may also have a high-k dielectric on layer 140.).
Re: Claim 24, the combination of Hsiao and Sharma discloses the semiconductor device of claim 23.
Hsiao further discloses wherein the top electrode is on the high dielectric constant (high-k) dielectric layer (Fig. 20A: top electrode 152 over second layer 140 which may be a high-k dielectric layer; ¶0038: In some embodiments, the first insulating layer 120 includes one or more high-k dielectric layers; ¶0041: second insulating layer 140… In some embodiments, the configuration of the second insulating layer 140 is the same as the configuration of the first insulating layer 120; In other words, an embodiment may have a TiOx layer 120 and may also have a high-k dielectric on layer 140.).
Re: Claim 25, the combination of Hsiao and Sharma discloses the semiconductor device of claim 21.
Hsiao further discloses wherein the hydrogen absorption layer comprises a metal-oxide material (¶0038: Other suitable materials include … Ti, … in the form of metal oxides, metal alloy oxides, i.e., TiOx).
Re: Claim 26, the combination of Hsiao and Sharma discloses the semiconductor device of claim 25.
Hsiao further discloses wherein the metal-oxide material comprises at least one of:
an indium oxide (InxOy), a titanium oxide (TiOx), an indium tin oxide (ITO), a cerium oxide (CeOx), a zinc oxide (ZnO), or an indium gallium zinc oxide (IGZO) (¶0038: Other suitable materials include … Ti, … in the form of metal oxides, metal alloy oxides, i.e., TiOx).
Re: Claim 27, the combination of Hsiao and Sharma discloses the semiconductor device of claim 21.
Hsiao further discloses wherein a thickness of the hydrogen absorption layer is included in a range of approximately 1 nanometer to approximately 100 nanometers (¶0038: first insulating layer 120 has a thickness in a range from about 1 nm to about 10 nm).
Re: Claim 31. The semiconductor device of claim 28,
wherein the transistor structure comprises a single-channel transistor structure that includes (Fig. 1A: Source 15S and drain 15D and gate labeled “Word Line” are connected to structure 62 which connects to capacitor 102 which make up a single-channel):
a gate structure (Fig. 1A: gate labeled “Word Line”);
…
However, Hsiao does not specifically disclose a channel layer over the gate structure;
a first source/drain region on the channel layer and above the gate structure; and
a second source/drain region on the channel layer and above the gate structure.
In a similar field of endeavor, Sharma discloses
a channel layer over the gate structure (Fig. 2: channel 209 is located over gate 205);
a first source/drain region on the channel layer and above the gate structure (Fig. 2: source area 291 is located on channel 209 and directly above gate 205); and
a second source/drain region on the channel layer and above the gate structure (Fig. 2: drain area 293 is located on channel 209 and directly above gate 205).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to substitute the encapsulated TFT taught by Sharma into the transistor structure of Hsiao because both references disclose known switching transistors suitable for use in a 1T-1C DRAM memory cell (Sharma, ¶0064: 1T1C configuration). Sharma provides explicit motivation by teaching that its metallic and insulating encapsulation layers protect the TFT against subsequence process operations so that the TFTs may be protected from hydrogen or moisture exposure, or oxygen loss which can improve subthreshold swing and have better ON/OFF ratio (Sharma, ¶0012). Also see MPEP 2144.06(II): Substituting Equivalents Know For The Same Purpose.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over HSIAO et al. (US 20220336576 A1) in view of LEE et al. (US 20230143124 A1), hereinafter “Lee.”
Re: Claim 30, Hsiao discloses the semiconductor device of claim 28.
However, Hsiao does not specifically disclose wherein the hydrogen absorption layer comprises one or more metal-hydroxide materials.
In a similar field of endeavor, Lee discloses wherein the hydrogen absorption layer comprises one or more metal-hydroxide materials (Fig. 6: S1022; ¶0081-0082: Operation s1022 of exposing the lower electrode 10 to the second gas including a hydroxyl group (OH) and operation s1023 of exposing the lower electrode 10 to the third gas including an oxygen radical (O) may be sequentially performed after the lower electrode 10 is exposed to the first gas. In this way, a Ti precursor may be adsorbed on the lower electrode 10 during the ALD operation of exposing the lower electrode 10 to the first gas, the second gas, and the third gas, and in this operation, a Ti—O binder may be formed on the lower electrode 10.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the structure disclosed in Hsiao to include a hydroxyl group on layer 120 in order to prevent or reduce the likelihood of the lower electrode from being oxidized during an operation of forming a dielectric layer (See Lee, ¶0008).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
MAEKAWA (US 7767569 B2) – Fig. 1 is relevant to the overall claimed structure
LU et al. (US 20240365530 A1) – Fig. 13A is relevant to the overall claimed structure
MUN et al. (US 20200058731 A1) – Figs. 9 and 10 are relevant to the overall claimed structure
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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