Attorney’s Docket Number: 0941-5013PUS1
Filing Date: 09/18/2023
Claimed Priority Date: N/A
Applicants: Lo et al.
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the election filed on 01/09/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s elections without traverse of Group I Invention, directed to method in the reply filed on 09/24/2025, is acknowledged. Applicant cancelled claims 16-20, added new claims 21-25, and indicated that claims 1-15 and 21-25 read on the elected Group I.
Claim Rejections - 35 USC § 112
Claim 8 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 8 depends on itself. The examiner assumes a typographical mistake, and that the applicant intended claim 8 to depend from claim 7, which introduces the limitation “a light-absorbing layer” recited again in claim 8. Accordingly, and for the purpose of examination, claim 8 will be construed as reciting – The LED Device of claim 7,-- until further clarifications are provided.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 8 are rejected under 35 U.S.C. 102 (a)(2) as anticipated by Chung et al (US 20240312836 A1, Hereinafter Chung).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 102 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding Claim 1, Chung et al shows (e.g., Fig 1-12, [0001]-[0048]) shows all aspects of the instant invention, including, a method for forming a semiconductor device, comprising:
forming a device layer over a device substrate (e.g., substrate 217 including transistors [0021]);
forming a front-side interconnect structure over the device layer (e.g., interconnect structure 219);
forming a bevel oxide over an edge portion of the device substrate, an edge portion of the device layer, and an edge portion of the front-side interconnect structure; (dielectric layer 225)
forming an oxide layer over the device layer, the front-side interconnect structure, and the bevel oxide (bonding layer 221 [0023]);
polishing the bevel oxide and the oxide layer until a top surface of the bevel oxide is substantially level with a top surface of the oxide layer (planarization process, such as a CMP, etch-back, or the like, to remove excess portions of the dielectric material [0024])and
attaching a carrier substrate to the bevel oxide and the oxide layer (Carrier 102 as attached in Fig 11 [0024] [0040]).
Regarding Claim 2, Chung shows flipping and thinning the device substrate (e.g., Fig 14 shows thinning during singulation).
Regarding Claim 8, Chung (Fig 2) shows trimming the bevel oxides and the interconnect layer (planarization process, such as a CMP, etch-back, or the like, to remove excess portions of the dielectric material [0024])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7, 11, 12, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Choi (US 20240420961 A1, Hereinafter Choi).
Regarding claim 4, while Chung shows a device substrate with a bevel oxide and a dielectric layer that is late polished using a CMP process, it does not show the polish rates for both layers to be different.
Choi (e.g., fig 11A and [0064] [0059]), on the other hand and in a related field of dielectric films, teaches a oxide film 130 on the bevel of a substrate, with another dielectric film placed on top. The second dielectric film (150) is doped to reduce over polishing during a trimming process. Since the doped dielectric film 150 is more hydrophobic than the first dielectric film 130 in which impurities are not implanted, with respect to the chemical mechanical polishing slurry composition used in the chemical mechanical polishing process, a selectivity of the doped dielectric film 150 may be less than a selectivity of the first dielectric film 130, and a polishing rate of the doped dielectric film 150 may be less than a polishing rate of the first dielectric film 130.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have oxide layers with different polishing rates in the method of Chung, as taught by Choi, to selectively polish a surface and reduce the chance of over polishing.
Regarding Claim 5, Chung does not show a recessed portion, however, Choi, on the other hand and in a related field (Fig 8 and 9) teaches a recessed portion (ET [0076]-[0085]) on the edge of the wafer that is formed prior to CMP ([0083]) filled with an oxide layer (bonding layer 190 [0060]) to enable bonding with another surface or carrier. The ET assists in reducing the possibility of over polishing during subsequent CMP process.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have formed a recessed portion in the method of Chung to selectively polish a surface and reduce the chance of over polishing.
Regarding Claim 6, See comments in Par XXX or claim 5, as they would be considered repeated here.
Regarding Claim 7, Choi teaches that the oxide layer is exposed after CMP (Fig 9 and corresponding paragraphs)
Regarding Claim 11, Chung et al shows (e.g., Fig 1-12, [0001]-[0048]) shows most aspects of the instant invention, including, a method for forming a semiconductor device, comprising:
forming transistors over a front-side surface of a device substrate; forming a first interconnect structure over the transistors (e.g., substrate 217 including transistors [0021]);
forming an oxide layer and a bevel oxide over the device substrate; partially removing the oxide layer and the bevel oxide until a top surface of the oxide layer is substantially level with a top surface of the bevel oxide ( (dielectric layer 225 and bonding layer 221 [0023] including planarization process, such as a CMP, etch-back, or the like, to remove excess portions of the dielectric material [0024]);
attaching a carrier substrate to the oxide layer and the bevel oxide (102); and
polishing a back-side surface of the device substrate (e.g., Fig 14 shows thinning during singulation).,
Chung is silent about the following :
wherein the device substrate has a device recessed portion formed on the front-side surface.
However, Choi (Fig 8 and 9) teaches a recessed portion (ET [0076]-[0085]) on the edge of the wafer that is formed prior to CMP ([0083]) filled with an oxide layer (bonding layer 190 [0060]) to enable bonding with another surface or carrier. The ET assists in reducing the possibility of over polishing during subsequent CMP process.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have formed a recessed portion in the method of Chung to selectively polish a surface and reduce the chance of over polishing.
Regarding Claim 12, See comments in Par XXX or claim 5, as they would be considered repeated here.
Regarding Claim 15, Chung shows a seal formed between the carrier substrate and the bevel oxide (Fig 13, Bevel oxide 225 is joined to 116 [0037]-[0040])
Claims 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sung (US 20230178446 A1, Hereinafter Sung).
Regarding Claim 21, Sung (Fig 1-10)shows most aspects of the invention including a method for forming a semiconductor device, comprising:
forming a device layer over a device substrate (e.g., Fig 1 substrate 32 with circuit devices 34) ;
forming a front-side interconnect structure (interconnect structure 40) over a front-side surface of the device layer ;
forming a back-side interconnect structure over a back-side surface of the device layer (FIG. 9, backside interconnect structure 68);
forming an oxide layer covering a central region of the front-side interconnect structure (bonding layer 54 [0027]-[0029]); and
forming a bevel oxide covering a bevel region of the front-side interconnect structure, and the oxide layer and the bevel oxide are formed of different dielectric materials (e.g., sidewall protection layers 62, specifically sublayer 62A or 62B, may be formed of oxides [0035]-[0042]).
The prior art seems to disclose an arrangement of top/bottom surface widths satisfying the limitation “wherein a width of the bevel oxide is less than a width of the oxide layer” (62A or B are about 3-1000nm compared to bonding layer 54 at 1000A-10000A) Additionally, with regards to the particular ratio of surface dimensions claimed, it is also noted that the specification fails to provide teachings about the criticality of having a width of the bevel oxide is less than a width of the oxide layer, and the courts have held that differences in (widths) will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such widths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed ratio between widths and since Sung teaches an arrangement of widths known in the art, it would have been obvious to one of ordinary skill in the art to use these widths in the device of Sung. Further, [0059] in the instant application states the width of the bevel oxide may alternatively be greater, or even “substantially the same as” the maximum thickness of the oxide layer.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed dimensions ratios or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions ratios or upon another variable recited in a claim, the applicant must show that the chosen ratios are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1939 (Fed. Cir. 1990).
Regarding Claim 22, While sung shows a bonding layer as the oxide layer as claimed, it does not show a recessed portion. Choi, on the other hand and in a related field (Fig 8 and 9) teaches a recessed portion (ET [0076]-[0085]) on the edge of the wafer that is formed prior to CMP ([0083]) filled with an oxide layer (bonding layer 190 [0060]) to enable bonding with another surface or carrier. The ET assists in reducing the possibility of over polishing during subsequent CMP process.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have formed a recessed portion in in forming the bonding layers Chung to selectively polish a surface and reduce the chance of over polishing.
Allowable Subject Matter
Claims 3,9,10 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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