Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Restriction Requirement mailed on 11/14/2025, the Applicant elected without traverse Group I encompassing method claims 1-15 on 01/14/2026. Non-elected Group II encompassing device claims 16-20 is withdrawn from examination.
Currently, claims 1-20 are pending and the elected claims 1-15 are examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
Two information disclosure statements submitted on 09/18/2023 ("09-18-23 IDS") and 09/02/2024 (“09-02-24 IDS”) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the 09-18-23 IDS and 09-02-24 IDS are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: [[SEMICONDUCTOR DEVICE AND]] METHOD FOR [[MAKING THE SAME]] SINGULATING SEMCONDUCTOR SUBSTRATE BY ETCHING FRONT AND BACK SURFACES OF SEMICONDUCTOR SUBSTRATE
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2021/0225806 A1 to Shen et al. ("Shen").
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Regarding independent claim 1, Shen teaches a method for singulating a semiconductor substrate into individual semiconductor devices, comprising:
providing a semiconductor substrate 102 (para [0013] - “In some embodiments, the conductive pads 106 are formed on a first surface 102a of the core substrate 102 (first surface 102a of interposer structure 100).”) having a front surface 102a and a back (para [0024] - “a second surface 102b”), wherein the semiconductor substrate 102 comprises device regions DV (para [0014] - “device regions DV”) that are separated from each other by respective predetermined saw streets DR or PSS (para [0014] - “dicing region DR”; see Fig. 1A. The term “predetermined” is a statement of intent so it does not structurally distinguish the saw streets. The extent of an area of what is a saw street can be is an area between two devices.);
forming an interconnect layer 106 (para [0013] - “In some embodiments, the conductive pads 106 are formed on a first surface 102a of the core substrate 102 (first surface 102a of interposer structure 100).”) on the front surface 102a of the semiconductor substrate 102 (see Fig. 1A);
attaching a semiconductor element 21 and/or 22 (para [0018] - “In some embodiments, the semiconductor dies 21 and the semiconductor dies 22 are attached to the first surface 102a of the core substrate 102, for example, through flip-chip bonding by way of the conductive bumps 110.”) onto the front surface 102a of the semiconductor substrate 102 in each device region DV (see Fig. 1A);
etching the front surface of the semiconductor substrate 102 at the predetermined saw streets DR or PSS to form respective frontside openings TR1 (para [0019] - “a first trench TR1”) each having a first depth (see Fig. 1B), wherein the first depth is smaller than a thickness of the semiconductor substrate 102 (see Fig. 1B);
etching the back surface 102b of the semiconductor substrate 102 at the respective predetermined saw streets DR or PSS to form respective backside openings TR2 (para [0025] - “a second trench TR2”) each having a second depth, wherein each frontside opening TR1 is at least partially aligned with the backside opening TR2 at the same saw street to singulate the device regions DV of the semiconductor substrate 102 into individual semiconductor devices (see Fig. 1J).
Regarding claim 5, Shen teaches each frontside opening TR1 that has a width smaller than a width of the corresponding predetermined saw street PSS.
Regarding claim 6, Shen teaches the width of the frontside openings TR1 that falls within 20% to 90% of the width of the predetermined saw streets PSS.
Regarding claim 8, Shen teaches each backside opening TR2 that has a width that is substantially equal to a width of the corresponding saw street DR or PSS.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 2.
Claim 3 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 3.
Claim 4 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 4.
Claim 7 is objected to for depending on a rejected base claim 1 and the intervening claim 5, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 5 or the base claim 1 is amended to include all of the limitations of claim 7 and the intervening
claim 5.
Claim 9 is allowable for depending on the allowable claim 7.
Claim 10 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 10.
Claim 11 is allowable for depending on the allowable claim 10.
Independent claim 12 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12,
wherein each frontside opening is partially aligned with the backside opening with an offset at the same saw street to singulate the device regions of the semiconductor substrate into individual semiconductor devices and form a step at an edge of the corresponding semiconductor device at the saw street; and
attaching onto the step of each semiconductor device an auxiliary structure.
Claims 13-15 are allowed, because they depend from the allowed independent claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2021/0296194 A1 to Shah et al.
Pub. No. US 2015/0334823 A1 to Hu
Pub. No. US 2005/0263854 A1 to Shelton et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 28 January 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status