DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on January 14, 2026 is acknowledged. The traversal is on the ground(s) that “the inventions do not appear to be seriously burdensome, especially in view of the fact that the Groups I and II are deemed closely classified as indicated above”. This is not found persuasive because the groups have separate classifications and would require at least the searching of different terms and a separate determination of allowability. Group I is drawn to a method of making an electronic package classified in H10W 74/014, and H10W 74/016. Group II is drawn to an electronic package classified in H10W 74/117, H10P 72/0614, H10W 70/611, and H10W 70/635. Therefore, the groups have separate classifications. Furthermore, search terms and keywords that would be used to find art pertinent to one group are not likely to find art pertinent to the other. For example, search terms and strategies used to find art disclosing an electronic device with a substrate, a plurality of electronic components and an encapsulant cap (Group II) are not likely to result in finding art pertinent to the method steps specific to Group I.
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on January 14, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20130175701 A1) herein after “Park” in view of Kasai et al. (US 20160189986 A1) herein after “Kasai”.
Regarding claim 8, Figs. 3a-4h of Park disclose a method for making an electronic package (Figs. 3a-4h, “a method of making a semiconductor device”, ¶ [0012]), the method comprising:
placing a plurality of electronic packages (Fig. 3b, plurality of semiconductor die or components 124, ¶ [0041]) on a bottom mold chase (Fig. 4c, carrier 140, ¶ [0046]);
disposing a top mold chase (Fig. 4c, chase mold 146, ¶ [0048]) over the electronic packages (124), wherein the top mold chase (146) has a molding cavity (Fig. 4c, cavity 152, ¶ [0048]) to receive the electronic packages (124), and the molding cavity (152) has a molding surface (Fig. 4c, upper interior surface 154, ¶ [0048]) facing towards the electronic packages (124), and wherein the molding surface (154) has a first molding region (Fig. 4c, smooth area 158, ¶ [0048]) with a first roughness and a second molding region (Fig. 4c, rough area 160, ¶ [0048]) with a second roughness greater than the first roughness (“Smooth area 158 includes a roughness or offset between high and low regions that is less than a roughness of rough area 160”, ¶ [0048]);
injecting an encapsulant material (Fig. 4c, “a volume of encapsulant or molding compound 164 is injected”, ¶ [0050]) into the molding cavity (152) to form an encapsulant cap (Fig. 4c, encapsulant 164, ¶ [0050]) encapsulating the substrate (Fig. 4e, interconnect structure 184, ¶ [0053]) and the plurality of electronic components (124) of each electronic package (124), wherein the encapsulant cap (164) comprises a top surface having a first region (Fig. 4e, semiconductor die area 178, ¶ [0051]) and a second region (Fig. 4e, peripheral area 180, ¶ [0051]) which correspond to the first molding region (158) and the second molding region (160) of the molding surface (154), respectively;
detaching the electronic packages (124) each encapsulated with an encapsulant cap (164) from the bottom mold chase (140) and the top mold chase (146) (Fig. 4e, “carrier 140 and interface layer 142 are removed”, ¶ [0053]); and
separating the plurality of electronic packages (124) from each other by singulation (Fig. 4h, “reconstituted wafer 170 together with build-up interconnect structure 184 and bumps 190 singulated through encapsulant 164 and build-up interconnect structure 184 using a saw blade or laser cutting tool 194 into individual semiconductor devices or packages 196”, ¶ [0058]) such that each electronic package (124) is encapsulated with the encapsulant cap (164).
Park fails to disclose placing a substrate strip with a plurality of electronic packages on a bottom mold chase, wherein each electronic package comprises a substrate and a plurality of electronic components disposed on the substrate.
In the similar field of endeavor of producing semiconductor packages, Fig. 10 of Kasai discloses placing a substrate strip with a plurality of electronic packages (Fig. 4, plurality of semiconductor chips 12, ¶ [0170]) on a bottom mold chase (Fig. 4, lower mold 52, ¶ [0170]), wherein each electronic package (Fig. 4, batch sealed body 110, ¶ [0172]) comprises a substrate (Fig. 4, substrate 10, ¶ [0170]) and a plurality of electronic components (12) disposed on the substrate (10).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Park with the substrate strip as disclosed by Kasai, to suppress damage to the semiconductor chips (see Kasai, ¶ [0154]).
Regarding claim 9, Park and Kasai together disclose the method of claim 8 as applied above, and Fig. 6 of Park discloses wherein the top mold chase (146) has a first depth in the first molding region (158) greater than a second depth in the second molding region (160) (Fig. 6, “thickness of the encapsulant T4 that is less than T3”, ¶ [0066]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130175701 A1) and Kasai (US 20160189986 A1) in further view of Moon (US 20230268198 A1).
Regarding claim 10, Park and Kasai together disclose the method of claim 8 as applied above, and Fig. 5 of Park further discloses wherein the first roughness is less than 0.8 μm (Fig. 5, “semiconductor die area 178 includes a roughness less than… 0.5 .mu.m”, ¶ [0051]), but Park and Kasai fail to disclose the second roughness is greater than 1.8 μm.
However, Park discloses that varying the first and second roughness reduces damage to the dies and increases productivity (see Park, ¶ [0052]).
In the similar field of endeavor of molding semiconductor devices, Fig. 3C of Moon discloses the second roughness is greater than 1.8 μm (Fig. 3C, “the first regions 322 can have a single roughness depth… between about 4 micrometers (μm) and about 25 μm”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Park with the second roughness as disclosed by Moon, to reduce damage to the semiconductor chips (see Moon, ¶ [0017]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130175701 A1) and Kasai (US 20160189986 A1) in further view of Kim et al. (US 20210066154 A1) herein after “Kim”.
Regarding claim 11, Park and Kasai together disclose the method of claim 8 as applied above, but Park and Kasai fail to disclose further comprising:
forming a laser marking in the first region of the top surface of the encapsulant cap.
In the similar field of endeavor of semiconductor packages, Fig. 39 of Kim discloses forming a laser marking (Fig. 39, “a laser marking method may be used to mark semiconductor information in the marking regions 402a_III”, ¶ [0344]) in the first region (Fig. 39, marking regions 402a_III, ¶ [0340]) of the top surface of the encapsulant cap (Fig. 39, “a base 404_III located on an upper surface of a sealing material”, ¶ [0340]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Park to include laser marking as disclosed by Kim, to provide information about the semiconductor chips (see Kim, ¶ [0340]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893