DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed June 9, 2026. Claim 8 has been amended. No claims have been added. No claims have been canceled. Claims 1-7 stand withdrawn. Currently, claims 8-11 are pending.
Response to Arguments
Applicant’s arguments with respect to claim 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al. (US 20150366085 A1) herein after “Shih” in view of Park et al. (US 20130175701 A1) herein after “Park” and Kasai et al. (US 20160189986 A1) herein after “Kasai”.
Regarding claim 8, Figs. 2A-2D of Shih disclose a method for making an electronic package (“Figs. 2A to 2D are schematic cross-sectional views showing a method for fabricating a package structure 2”, ¶ [0030]), the method comprising:
placing an electronic package (Fig. 2C″, package structure 2, ¶ [0030]) on a bottom mold chase (Fig. 2C″, bottom portion of mold 9, ¶ [0041]), wherein each electronic package (2) comprises a substrate (Fig. 2C, substrate 20, ¶ [0031]) and a first electronic component (Fig. 2C, electronic elements 21b, ¶ [0031]) and a second electronic component (Fig. 2C, electronic elements 21a, ¶ [0031]) disposed on the substrate (20), wherein the first electronic component (21b) is higher than the second electronic component (21a);
disposing a top mold chase (Fig. 2C″, top portion of mold 9, ¶ [0041]) over the electronic packages (2), wherein the top mold chase (9) has a molding cavity to receive the electronic packages (2), and the molding cavity has a molding surface facing towards the electronic packages (2), and wherein the molding surface has a first molding region (Fig. 2C″, portion of mold 9 above component 21b) where the first electronic component (21b) is disposed thereon with a first roughness and a second molding region (Fig. 2C″, portion of mold 9 above component 21a) where the second electronic component (21a) is disposed thereon with a second roughness;
depositing an encapsulant material (Fig. 2C″, “the electronic elements 21a, 21b, 21c are disposed in a mold 9 and an encapsulant 23 having a non-rectangular shape is formed in the mold 9”, ¶ [0041]) into the molding cavity to form an encapsulant cap (23) encapsulating the substrate (20) and the plurality of electronic components (102) of each electronic package (2), wherein the encapsulant cap (23) comprises a top surface having a first region (Fig. 2C″, region of 23 above 21b) and a second region (Fig. 2C″, region of 23 above 21a) which correspond to the first molding region and the second molding region of the molding surface, respectively, the first region is higher than the second region (shown in Fig. 2C″), and a thickness of the encapsulant cap in the first region which encapsulates the first electronic component (21b) is greater than a thickness of the encapsulant cap in the second region which encapsulates the second electronic component (21a); and
detaching the electronic package (2) encapsulated with an encapsulant cap (23) from the bottom mold chase and the top mold chase (“the mold 9 is removed and a package structure 2”, ¶ [0041]).
Shih fails to disclose placing a substrate strip with a plurality of electronic packages on a bottom mold chase, wherein each electronic package comprises a substrate and a plurality of electronic components disposed on the substrate;
the second roughness greater than the first roughness;
injecting the encapsulant material into the molding cavity; and
separating the plurality of electronic packages from each other by singulation such that each electronic package is encapsulated with the encapsulant cap.
In the similar field of endeavor of producing semiconductor packages, Figs. 24 of Kasai discloses placing a substrate strip with a plurality of electronic packages (Fig. 4, plurality of semiconductor chips 12, ¶ [0170]) on a bottom mold chase (Fig. 4, lower mold 52, ¶ [0170]), wherein each electronic package (Fig. 4, batch sealed body 110, ¶ [0172]) comprises a substrate (Fig. 4, substrate 10, ¶ [0170]) and a plurality of electronic components (12) disposed on the substrate (10),
injecting the encapsulant material into the molding cavity (Figs. 2-3, “A step wherein the mold is clamped, and a plunger 64 of a resin placement portion 62 of the lower mold 52 is pushed up, to fill a curable resin 40”, ¶ [0171]); and
separating the plurality of electronic packages from each other by singulation such that each electronic package is encapsulated with the encapsulant cap (“A step wherein the batch sealed body 110 is cut (singulated) so that the plurality of semiconductor chips 12 are separated to obtain a plurality of semiconductor devices”, ¶ [0174]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Shih with the substrate strip and plurality of electronic devices as disclosed by Kasai, to suppress damage to the semiconductor chips and allow for batch processing (see Kasai, ¶ [0154] and [0174]).
Kasai fails to disclose the second roughness greater than the first roughness.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 6 of Park discloses the second roughness greater than the first roughness (“Smooth area 158 includes a roughness or offset between high and low regions that is less than a roughness of rough area 160”, ¶ [0048]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Shih with the roughness as disclosed by Park, to reduce sticking within the mold (see Park, ¶ [0052]).
Regarding claim 9, Shih, Kasai and Park together disclose the method of claim 8 as applied above, and Fig. 2C″ of Shih further disclose wherein the top mold chase (9) has a first depth in the first molding region greater than a second depth in the second molding region (shown in Fig. 2C″).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 20150366085 A1), Park (US 20130175701 A1) and Kasai (US 20160189986 A1) in further view of Moon (US 20230268198 A1).
Regarding claim 10, Shih, Kasai and Park together disclose the method of claim 8 as applied above, but Shih and Kasai fail to disclose wherein the first roughness is less than 0.8 μm and the second roughness is greater than 1.8 μm.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 6 of Park further discloses wherein the first roughness is less than 0.8 μm (“semiconductor die area 178 includes a roughness less than… 0.5 .mu.m”, ¶ [0051]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Shih with the roughness as disclosed by Park, to reduce sticking within the mold (see Park, ¶ [0052]) and/or because it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05, citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Park fails to disclose the second roughness is greater than 1.8 μm.
In the similar field of endeavor of molding semiconductor devices, Fig. 3C of Moon discloses the second roughness is greater than 1.8 μm (Fig. 3C, “the first regions 322 can have a single roughness depth… between about 4 micrometers (μm) and about 25 μm”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Park with the second roughness as disclosed by Moon, to reduce damage to the semiconductor chips (see Moon, ¶ [0017]) and/or because it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05, citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 20150366085 A1), Park (US 20130175701 A1) and Kasai (US 20160189986 A1) in further view of Kim et al. (US 20210066154 A1) herein after “Kim”.
Regarding claim 11, Shih, Kasai and Park together disclose the method of claim 8 as applied above, but Shih, Kasai and Park fail to disclose further comprising:
forming a laser marking in the first region of the top surface of the encapsulant cap.
In the similar field of endeavor of semiconductor packages, Fig. 39 of Kim discloses forming a laser marking (Fig. 39, “a laser marking method may be used to mark semiconductor information in the marking regions 402a_III”, ¶ [0344]) in the first region (Fig. 39, marking regions 402a_III, ¶ [0340]) of the top surface of the encapsulant cap (Fig. 39, “a base 404_III located on an upper surface of a sealing material”, ¶ [0340]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Park to include laser marking as disclosed by Kim, to provide information about the semiconductor chips (see Kim, ¶ [0340]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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