Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Species I, which is directed to FIGs. 6, 9 in the reply filed on 12/08/2025 is acknowledged. Claims 1-3 and 5- 20, along with new claim 21, read on the elected Species I . Claim Objections Claim 15 is objected to because of the following informalities: the following limitation cited in line 3 “ the first via extends through the isolation feature to direct contact the second gate structure ” should read “ the first via extends through the isolation feature to direct ly contact the second gate structure ”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 12 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 12 recites the limitation "a read bit line" in line 7 which causes ambiguity in the claim as to whether it is referring to the same read bit line cited in line 3 or a different one. For the purpose of examination, they will be interpreted as same. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 9- 10, 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sisodia et al. (US 20220223514 A1; hereinafter “Sisodia”) In re claim 1, Sisodia discloses in figs. 1, 3, a semiconductor structure, comprising: a two-port static random access memory (SRAM) cell (¶9) comprising: a write port portion (T1-T6) (¶13) ; and a read port portion (a read port portion comprising transistors T8-T7; ¶13) electrically coupled to the write port portion and comprising a transistor having a gate structure (e.g., a gate structure of transistor T7 ; hereinafter “G7” ) ; a first plurality of metal lines M0 , M1, M2, M4 comprising a write bit line BL and a complementary write bit line NBL (¶13 , 20 ) , wherein the first plurality of metal lines M1, M0 are positioned at a first interconnect layer ( a first interconnect layer comprising M0 and M1 ) disposed over the gate structure G7 ; and a read word line RWL positioned at a second interconnect layer BM0/BM1 and electrically coupled to the gate structure, wherein the second interconnect layer BM0/BM1 is disposed under the gate structure G7 . In re claim 9 , Sisodia discloses in figs. 1, 3, the semiconductor structure of claim 1, wherein the gate structure G7 shown as M0 in fig. 3 and the read word line RWL extend lengthwise along a same direction (e.g., east-west direction in fig. 3) . In re claim 10, Sisodia discloses in figs. 1, 3, a semiconductor structure, comprising: a memory cell 104 connected to a write word line WWL and a read word line RWL (¶13) ; a first interconnect structure 314, via, WWL disposed over the memory cell 104 and comprising the write word line WWL (¶22) ; and a second interconnect structure 31 8 , via, R WL disposed under the memory cell 104 and comprising the read word line RWL (¶22) . In re claim 17, Sisodia discloses in figs. 1, 3, a semiconductor structure, comprising: a first memory cell 108 comprising: a write port portion (T1-T6) (¶13); and a read port portion (a read port portion comprising transistors T8-T7; ¶13) comprising a transistor T7 having a first source/drain feature (e.g., a first source/drain feature connected to RBL) and a second source/drain feature (e.g., a second source/drain feature connected to a S/D of T8) coupled to a channel region (e.g., a channel region of transistor T7 shown as N-well in fig. 3) , and a gate structure (e.g., a gate structure of transistor T7) engaging the channel region (¶13), a backside via (see fig. 3 annotated below) disposed directly under and in direct contact with the gate structure; and a first interconnect layer 318 disposed under and electrically coupled to the backside via, wherein a read word line RWL is positioned at the first interconnect layer (¶22). In re claim 18, Sisodia discloses in figs. 1, 3, the semiconductor structure of claim 17, wherein the first memory cell is connected to a first power line VDD for receiving a first power supply voltage, and a second power line VSS for receiving a second power supply voltage (¶13), wherein the first power line VDD and the second power line VSS are positioned at a second interconnect layer disposed over the gate structure (fig. 3). In re claim 19, Sisodia discloses in figs. 1, 3, the semiconductor structure of claim 18, wherein one of the first and second source/drain features is electrically coupled to a read bit line RBL , and the read bit line RBL is positioned at the second interconnect layer (fig. 3 shows the read bit line RBL is positioned at the same interconnect layer as VDD and VSS) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-3, 5- 8 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sisodia, as applied to claim 1 above, and further in view of Liaw et al. (US 20230223455 A1; hereinafter “Liaw”). In re claim 2, Sisodia discloses in fig. 3 annotated below, the semiconductor structure of claim 1, further comprising: a first via disposed above and in direct contact with the gate structure G7 ; a landing pad (the white rectangle as shown in fig. 3 annotated below) disposed directly above and in direct contact with the first via; and a second via (the vertical via as shown in fig. 3 annotated below; hereinafter “ via2 ”) disposed directly under and in direct contact with the landing pad, wherein the second interconnect layer BM0/BM1 is disposed under and in direct contact with the second via via2 . Sisodia does not expressly disclose the first via is disposed under and in direct contact with the gate structure and the landing pad disposed directly under the first via. In the same field of endeavor, Liaw discloses in figs. 1-3, 5A-5D, a semiconductor structure, wherein a first via 702-6 is disposed under and in direct contact with a gate structure 406 and a landing pad 608-1 disposed directly under the first via (¶83) . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the first via and the landing pad of Sisodia ’s transistor to reduce chip footprint at the front while maintaining reasonable processing margins (¶2-3 of Liaw). It would have been obvious to one of ordinary skill in the art to modify the disposition of the via and landing pad underneath the gate structure since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In re claim 3 , Sisodia , as modified by Liaw, discloses t he semiconductor structure of claim 2, wherein the first via (Liaw: fig. 5C, 702-6) is vertically overlapped with a channel region of the transistor (Liaw: fig. 5C, 416 ) . In re claim 5 , Sisodia, as modified by Liaw, discloses the semiconductor structure of claim 2, wherein the landing pad (Liaw: fig s . 2, 5C, 608-1 ) extends lengthwise along a first direction (X) , the gate structure (Liaw: fig s . 2, 5C, 406 ) extends lengthwise along a second direction (Y) substantially perpendicular to the first direction. In re claim 6 , Sisodia, as modified by Liaw, discloses the semiconductor structure of claim 2 . Sisodia further discloses in in figs. 1, 3 , wherein the transistor further comprises a first source/drain (e.g., a first S/D of T7) feature electrically coupled to the write port portion (e.g., S/D of T5/T6 of the write port portion ) and a second source/drain feature (e.g., a second S/D of T7) electrically coupled to a read bit line RBL , and the read bit line RBL is positioned at a third interconnect layer M1 disposed over the gate structure G7 . In re claim 7 , Sisodia, as modified by Liaw, discloses the semiconductor structure of claim 6 . Sisodia further discloses in figs. 1, 3 , a source/drain contact (shown as via underneath RBL in fig. 3) disposed over and in direct contact with the second source/drain feature , wherein the third interconnect layer M1 is disposed over and in direct contact with the source/drain contact. Sisodia does not expressly disclose the semiconductor structure further comprising: a silicide layer disposed over and in direct contact with the second source/drain feature; and a source/drain contact disposed over and in direct contact with the silicide layer . In the same field of endeavor, Liaw discloses in figs. 1-3, 4 A- 4H , the semiconductor structure further comprising: a silicide layer 501 disposed over and in direct contact with a source/drain feature 418 (¶69) ; and a source/drain contact 502-3 disposed over and in direct contact with the silicide layer 501 . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form a silicide layer over the source/drain feature of Sisodia ’s transistor to reduce parasitic resistance in the S/D region and improves transistor performance . In re claim 8, Sisodia discloses the semiconductor structure of claim 1 . Sisodia does not expressly disclose: wherein the transistor further comprises a vertical stack of nanostructures, and the gate structure comprises a first portion over the vertical stack of nanostructures and a second portion wrapping around each nanostructure of the vertical stack of nanostructures. In the same field of endeavor, Liaw discloses in figs. 1-3, 5, a semiconductor structure comprising a transistor 10 (¶42), wherein the transistor 10 further comprises a vertical stack of nanostructures 416 (¶63) , and a gate structure 406 comprises a first portion (e.g., a top portion) over the vertical stack of nanostructures 416 and a second portion (e.g., a middle and bottom portion s ) wrapping around each nanostructure 416 of the vertical stack of nanostructures. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the transistor of Sisodia as a gate-all-around transistor to reduce chip footprint while maintaining reasonable processing margins (¶2-3 of Liaw) . In re claim 21, Sisodia, as modified by Liaw, discloses the semiconductor structure of claim 3. Sisodia does not expressly disclose the semiconductor structure further comprising: an isolation feature disposed alongside a lower portion of the channel region, wherein a top surface of the first via is above a top surface of the isolation feature. In the same field of endeavor, Liaw discloses in figs. 1-3, 5A-5D, the semiconductor structure further comprising: an isolation feature 610 disposed alongside a lower portion of the channel region 416 , wherein a top surface of the first via 702-6 is above a top surface of the isolation feature 610 . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form an isolation feature surrounding the first via in Sisodia’s transistor to isolate neighboring vias and reduce interference between adjacent transistors . Claim(s) 11 -12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sisodia , as applied to claim 10 above , and further in view of Nguyen et al. ( US 20160247555 A1 ; hereinafter “ Nguyen ”) . In re claim 1 1 , Sisodia discloses in figs. 1, 3, t he semiconductor structure of claim 10, wherein the memory cell comprises: a first active region N-well forming Transistor T 6 and a second active region (active region forming transistor T7) extending lengthwise along a first direction (as shown in figs. 2-3, the active regions extending lengthwise along a north-south direction ) ; and first and second gate structures extending lengthwise in a second direction perpendicular to the first direction (as shown in figs. 2-3, the first and second gate structures , M0 extending lengthwise along east-west direction) , wherein the first gate structure engages the first active region in forming an N-type transistor T 6 , and the first gate structure is electrically coupled to the write word line WWL (see fig. 1) , and the second gate structure (i.e., the gate of transistor T7) is electrically coupled to the read word line RWL . Sisodia does not expressly disclose wherein the second gate structure engages the second active region in forming a P-type transistor . In the same field of endeavor, Nguyen discloses in figs. 5A-5B, a semiconductor structure comprising : a PFET read port 528 (0) , wherein a second gate structure (gate structure of 528 ( 0 ) ) engag ing a second active region in forming a P-type transistor (¶45), wherein the second gate structure is electrically coupled to the read word line 506 (¶46; “ the wordline (WL) 506 coupled to gates (G) of the PFET access transistors 528 ( 0 ), 528 ( 1 ) ”) . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the read-port transistor of Sisodia as a PFET transistor to mitigate or avoid a read disturb condition from occurring in the bit cell as taught by Nguyen (¶8-9 of Nguyen ). In re claim 1 2 , Sisodia , as modified by Nguyen , discloses t he semiconductor structure of claim 11 , wherein the P-type transistor (i.e., Sisodia ’s read access transistor modified by Nguyen ’s teaching of pFET read access transistor ) further comprises : a first source/drain feature (a first S/D of transistor T7 in figs. 1-3 of Sisodia ) electrically coupled to a read bit line RBL ( figs. 1-3 of Sisodia ) and a second source/drain feature (a second S/D of transistor T7 in figs. 1-3 of Sisodia ) electrically coupled (e.g., electrically coupled through T8) to a source/drain feature of the N-type transistor T6 in figs. 1-3 of Sisodia , and wherein the first interconnect structure comprises: a source/drain contact (e.g., a contact shown underneath RBL in figs. 1-3 of Sisodia ) disposed over the first source/drain feature; and a read bit line RBL (as best understood, the read bit line) disposed over and in direct contact with the source/drain contact (i.e., contact shown underneath RBL in figs. 1-3 of Sisodia ) . Claim(s) 13 -15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sisodia in view of Nguyen, as applied to claim 1 1 above, and further in view of Liaw et al. (US 20230223455 A1; hereinafter “Liaw”) . In re claim 1 3 , Sisodia, as modified by Nguyen, discloses the semiconductor structure of claim 11 . Sisodia further discloses in fig. 3 annotated below, wherein the second interconnect structure comprises: a first via disposed above and in direct contact with the second gate structure G7 ; a landing pad (the white rectangle as shown in fig. 3 annotated below) disposed directly above and in direct contact with the first via; and a second via (the vertical via as shown in fig. 3 annotated below; hereinafter “ via2 ”) disposed directly under and in direct contact with the landing pad, the read word line RWL is disposed directly under and in direct contact with the second via ( via2 ) . Sisodia does not expressly disclose the first via is disposed under and in direct contact with the second gate structure and the landing pad disposed directly under the first via. In the same field of endeavor, Liaw discloses in figs. 1-3, 5A-5D, a semiconductor structure, wherein a first via 702-6 is disposed under and in direct contact with a gate structure 406 and a landing pad 608-1 disposed directly under the first via (¶83). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the first via and the landing pad of Sisodia’s transistor to reduce chip footprint at the front while maintaining reasonable processing margins (¶2-3 of Liaw). It would have been obvious to one of ordinary skill in the art to modify the disposition of the via and landing pad underneath the gate structure since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In re claim 1 4 , Sisodia, as modified by Nguyen and Liaw , discloses the semiconductor structure of claim 1 3 , wherein the first via (Liaw: fig. 5C, 702-6) is disposed directly under a channel region (Liaw: fig. 5C, 416 ) of the P-type transistor. In re claim 1 5 , Sisodia, as modified by Nguyen and Liaw, discloses the semiconductor structure of claim 13 outlined above. Sisodia, as modified by Nguyen does not expressly disclose wherein the memory cell further comprises an isolation feature configured to isolate the first active region from the second active region, and the first via extends through the isolation feature to direct contact the second gate structure. In the same field of endeavor, Liaw discloses in figs. 1-3, 5A-5D, the semiconductor structure further comprising: wherein the memory cell further comprises an isolation feature 610 , 410 configured to isolate a first active region 404-1 from a second active region 404-2 (¶62) , and the first via 702-6 extends through the isolation feature 610 , 410 to direct contact the gate structure 406 . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form an isolation feature surrounding the first via in Sisodia’s transistor to isolate neighboring vias and reduce interference between adjacent transistors . Claim(s) 1 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sisodia in view of Nguyen , as applied to claim 10 above, and further in view of Houston et al. ( US 20110007580 A1 ; hereinafter “ Houston ”) . In re claim 1 6 , Sisodia, as modified by Nguyen, discloses the semiconductor structure of claim 11 outlined above. Sisodia, as modified by Nguyen, does not expressly disclose wherein the memory cell comprises a seven-transistor static random access memory (SRAM) cell. In the same field of endeavor, Houston discloses in fig. 4 , a memory cell comprises a seven-transistor static random access memory (SRAM) cell (¶45-48) . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the memory cell of Sisodia, as modified by Nguyen, comprising a seven-transistor static random access memory (SRAM) cell to provide an integrated circuit having an SRAM array with reduc ed operating power of the integrated circuit having the SRAM array (¶5-8 of Houston ). Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sisodia in view of Nguyen, as applied to claim 10 above, and further in view of Lee et al. ( US 20220328492 A1 ; hereinafter “Lee”) . In re claim 20, Sisodia discloses in figs. 1, 3, the semiconductor structure of claim 17 outlined above. Sisodia does not expressly disclose the semiconductor structure further comprising a second memory cell, wherein the backside via is further in direct contact with a gate structure of a transistor in a read port portion of the second memory cell. In the same field of endeavor, Lee discloses in fig s . 1A-2B , a semiconductor structure comprising a first and second memory cell s MC1, MC1 , wherein a shared connecting structure is in direct contact with gate structure s of two transistors in adjacent memory cells. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form a shared connecting structure as backside via which is in direct contact with a gate structure of a transistor in a read port portion of the second memory cell of Sisodia, as modified by Nguyen, to facilitate high integration of a memory cell (¶4 of Lee). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT NILUFA RAHIM whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-8926 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9am-5:30pm EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Yara J. Green can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-3035 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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