DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7 and 31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,437,680 B1 (Cheng).
Re claim 1, Cheng teaches a method of forming a composite wafer, comprising:
forming a layer stack comprising a carrier layer (donor wafer 102 having epitaxially grown SiGe buffer layer 104 grown thereon), an ion implantation layer (bubble layer 117), and a transfer material layer comprising a single crystalline semiconductor material (relaxed silicon 116/116’ and epitaxially grown relaxed SiGe layer 106; epitaxial growth requires the grown material to be single crystal [Col 3 lines 55-67 and Col 4 lines 1-21]) by implanting ions into a donor wafer ([Col 4 lines 13-21] Fig. 1(a)-(b));
forming trenches (openings formed in Fig. 2 by lithography process Col. 4 lines 22-34) through the transfer material layer, the ion implantation layer, and an upper portion of the carrier layer;
attaching the layer stack to an acceptor wafer including a stack of a handle substrate (bulk semiconductor layer 118) and a first dielectric oxide layer (oxide layer 120) by bonding the layer stack to the first dielectric oxide layer such that the single crystalline semiconductor material contacts, and is bonded to, the first dielectric oxide layer (Fig. 8); and
cleaving the layer stack at the ion implantation layer (Figs. 8-9 Col. 5 lines 12-27), whereby a composite wafer including the acceptor wafer and patterned portions of the transfer material layer is formed (Fig. 9).
PNG
media_image1.png
510
643
media_image1.png
Greyscale
Re claim 7, Cheng teaches wherein the first dielectric oxide layer is bonded to the patterned portions of the transfer material layer (Fig. 8).
Re claim 31, Cheng teaches wherein: the ion implantation layer remains free of any lateral recess when the patterned portions of the transfer material layer are bonded to the first dielectric oxide layer; and the patterned portions of the transfer material layer are bonded to the first dielectric oxide layer while the ion implantation layer remains free of any lateral recess (Figs. 8-9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 9, 21, 24, 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9,437,680 B1 (Cheng) further in view of US 20070037362 A1 (Bahl).
Re claims 2 and 9, Cheng teaches further comprising:
forming a patterned etch mask layer (hardmask layer 114) including laterally-extending openings over the transfer material layer (Fig. 2); and
forming the trenches by transferring a pattern of the laterally-extending openings into the transfer material layer by performing an anisotropic etch process (Fig. 2 Col. 4 lines 35-51) (claim 2) nor removing a peripheral region of the layer stack that is located outside areas of the patterned portions of the transfer material layer, wherein the peripheral region has a width that is at least twice a width of the trenches (claim 9).
However, Cheng does not explicitly teach wherein the patterns are intersecting lateral openings i.e. a grid, Cheng is completely silent with regards to the shape of the transferred portions but Cheng does teach that these material portions can have different internal stresses for NFET and PFET devices (Col. 5 lines 12-35).
Bahl teaches forming a transfer method wherein small portions of different semiconductor materials are transferred to a wafer and these transferred portions are used to make specific different types of devices on the same handle wafer (Figs. 1-5) and wherein the transferred material portions are separated out in a grid or checkerboard pattern having intersecting lines ([0017]) (Fig. 2).
Re claim 21, Cheng teaches a method of forming a composite wafer, the method comprising:
providing an acceptor wafer comprising a handle substrate (bulk semiconductor layer 118) and a first dielectric oxide layer (oxide layer 120) overlying the handle substrate;
providing a donor wafer comprising a carrier layer (donor wafer 102 having epitaxially grown SiGe buffer layer 104 grown thereon), an ion implantation layer (bubble layer 117) overlying the carrier layer, and a transfer material layer (relaxed silicon 116/116’ and epitaxially grown relaxed SiGe layer 106; epitaxial growth requires the grown material to be single crystal [Col 3 lines 55-67 and Col 4 lines 1-21]) overlying the ion implantation layer and comprising a single crystalline semiconductor material (SiGe [Col 4 lines 13-21] Fig. 1(a)-(b));
forming trenches (openings formed in Fig. 2 by lithography process Col. 4 lines 22-34) through the transfer material layer and a portion of the ion implantation layer in the donor wafer to provide an array of transfer material plates (Fig. 2);
bonding the array of transfer material plates to the first dielectric oxide layer of the acceptor wafer such that the single crystalline semiconductor material contacts, and is bonded to, the first dielectric oxide layer (Figs. 8-9 Col. 5 lines 12-27); and
cleaving the donor wafer along the ion implantation layer to transfer the array of transfer material plates onto the acceptor wafer (Figs. 8-9 Col. 5 lines 12-27).
However, Cheng does not explicitly teach wherein the patterns are intersecting lateral openings i.e. a grid, Cheng is completely silent with regards to the shape of the transferred portions but Cheng does teach that these material portions can have different internal stresses for NFET and PFET devices (Col. 5 lines 12-35).
Bahl teaches forming a transfer method wherein small portions of different semiconductor materials are transferred to a wafer and these transferred portions are used to make specific different types of devices on the same handle wafer (Figs. 1-5) and wherein the transferred material portions are separated out in a grid or checkerboard pattern having intersecting lines ([0017]) (Fig. 2).
PNG
media_image2.png
751
540
media_image2.png
Greyscale
It would have been obvious at the time of filing to alter the invention of Cheng using the teachings in Bahl, specifically wherein the transferred portions are formed in a grid which would require the etched trenches of Cheng to have intersecting lines.
The motivation to do so is that Cheng is silent with regards to the top view shape of the transferred portions but Cheng does teach that each of these portions is made for discrete individual or collections of NFETs and PFETs and making the transferred regions in a grid by etching around the perimeter of each transferred portion allows for discrete regions of active material for making NFETs and PFETs and the etched distance between adjacent transferred portions prevents these portions from bumping into other structures on the wafer when transferring.
Re claim 24, Cheng teaches wherein: the transfer material plates comprise a first material selected from single crystalline silicon, single crystalline germanium, a single crystalline silicon-germanium alloy, single crystalline lithium niobate, single crystalline lithium tantalate, single crystalline zinc oxide, single crystalline titanium oxide, single crystalline indium tin oxide, single crystalline gallium oxide, single crystalline tin oxide, single crystalline tungsten trioxide, or single crystalline indium gallium zinc oxide; the first dielectric oxide layer comprises a material that is selected from undoped silicate glass, a doped silicate glass, or thermally-grown silicon oxide; and the transfer material plates are bonded directly to the first dielectric oxide layer.
Re claim 32, Cheng teaches wherein: the ion implantation layer remains free of any lateral recess when the array of transfer material plates is bonded to the first dielectric oxide layer; and the array of transfer material plates is bonded to the first dielectric oxide layer while the ion implantation layer remains free of any lateral recess (Figs. 8-9)
Allowable Subject Matter
Claims 26, 29-30 are allowed.
Claims 7-8, 10, 22-23, 25, 33-34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Prosecution Insights