DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 3-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/5/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20070134891 A1 (Adetutu).
Re claim 1, Adetutu teaches a method of forming a composite wafer, comprising:
forming a layer stack comprising a carrier layer (portion of 1203 that lies below the damaged region), an ion implantation layer (damaged region 1207 formed by hydrogen ions implanted into 1203), and a transfer material layer (portion of 1203 above damaged region 1207 which is later patterned and bonded to wafer 1401) by implanting ions into a donor wafer (substrate 1203);
forming trenches (openings 1311, 1313, 1315, 1317) through the transfer material layer, the ion implantation layer, and an upper portion of the carrier layer (Fig. 13);
attaching the layer stack to an acceptor wafer (wafer 1401) including a stack of a handle substrate and a first dielectric oxide layer (insulator layer 1403 e.g. silicon oxide [0046]) by bonding the layer stack to the first dielectric oxide layer (Fig. 14-15); and
cleaving the layer stack at the ion implantation layer (Fig. 16), whereby a composite wafer including the acceptor wafer and patterned portions of the transfer material layer is formed (Figs. 12-18).
PNG
media_image1.png
443
528
media_image1.png
Greyscale
PNG
media_image2.png
728
504
media_image2.png
Greyscale
PNG
media_image3.png
690
492
media_image3.png
Greyscale
Re claim 7, Adetutu teaches wherein the first dielectric oxide layer is bonded to the patterned portions of the transfer material layer (Fig. 14-15 [0046-0049]).
Re claim 8, Adetutu teaches further comprising:
forming at least one additional layer stack comprising a respective additional carrier layer, a respective additional ion implantation layer, and a respective additional transfer material layer;
forming additional trenches through an upper portion of each of the at least one additional layer stack;
attaching the at least one additional layer stack to the acceptor wafer by bonding each of the at least one additional layer stack to the first dielectric oxide layer; and
cleaving each of the at least one additional layer stack at the respective additional ion implantation layer (see rejection of claim 1 above and where Adetutu teaches that the wafer can be formed of active material structures having different surface orientations for different devices wherein the other surface orientation portions on the wafer can be formed by the same bonding technique as that described in Figs. 12-18 [0037-0054]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 9, 21-23, 24, 16-27, 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20070134891 A1 (Adetutu) further in view of US 20070037362 A1 (Bahl).
Re claims 2 and 9, Adetutu teaches the method of Claim 1, and Adetutu further teaches:
forming a patterned etch mask layer including laterally-extending openings over the transfer material layer; and
forming the trenches by transferring a pattern of the laterally-extending openings into the transfer material layer by performing an anisotropic etch process (photolithography to etch patterns in the silicon layers [0017-0018]).
However, Adetutu does not explicitly teach wherein the patterns are intersecting lateral openings i.e. a grid, nor removing a peripheral region of the layer stack that is located outside areas of the patterned portions of the transfer material layer, wherein the peripheral region has a width that is at least twice a width of the trenches (claim 9). Adetutu is completely silent with regards to the shape of the transferred portions but Adetutu does teach that these material portions can have any shape/size/dimension that is necessary to form the dissimilar material portion on the wafer ([0039-0043 and 0061-0063]).
Bahl teaches forming a transfer method wherein small portions of different semiconductor materials are transferred to a wafer and these transferred portions are used to make specific different types of devices on the same handle wafer (Figs. 1-5) and wherein the transferred material portions are separated out in a grid or checkerboard pattern having intersecting lines and etching the peripheral area around the wafer edge ([0017]) (Fig. 2).
PNG
media_image4.png
751
540
media_image4.png
Greyscale
It would have been obvious at the time of filing to alter the invention of Adetutu using the teachings in Bahl, specifically wherein the transferred portions are formed in a grid which would require the etched trenches of Adetutu to have intersecting lines.
The motivation to do so is that Adetutu is silent with regards to the top view shape of the transferred portions but Adetutu does teach that each of these portions is made for discrete individual or collections of NFETs and PFETs and making the transferred regions in a grid by etching around the perimeter of each transferred portion allows for discrete regions of active material for making NFETs and PFETs and the etched distance between adjacent transferred portions prevents these portions from bumping into other structures on the wafer when transferring.
Re claim 21, Adetutu teaches a method of forming a composite wafer, the method comprising:
providing an acceptor wafer (wafer 1401) comprising a handle substrate (substrate layer 1402) and a first dielectric oxide layer (insulator layer e.g. silicon oxide [0046]) overlying the handle substrate;
providing a donor wafer (substrate 1203) comprising a carrier layer (portion of 1203 that lies below the damaged region), an ion implantation layer (damaged region 1207 formed by hydrogen ions implanted into 1203) overlying the carrier layer, and a transfer material layer (portion of 1203 above damaged region 1207 which is later patterned and bonded to wafer 1401) overlying the ion implantation layer;
forming trenches (openings 1311, 1313, 1315, 1317) through the transfer material layer and a portion of the ion implantation layer in the donor wafer to provide an array of transfer material plates (Fig. 13);
bonding the array of transfer material plates to the first dielectric oxide layer of the acceptor wafer (Figs. 14-15); and
cleaving the donor wafer along the ion implantation layer (Fig. 16) to transfer the array of transfer material plates onto the acceptor wafer (Figs. 12-18).
PNG
media_image1.png
443
528
media_image1.png
Greyscale
PNG
media_image2.png
728
504
media_image2.png
Greyscale
PNG
media_image3.png
690
492
media_image3.png
Greyscale
Adetutu does not explicitly teach wherein the patterns are intersecting lateral openings i.e. a grid. Adetutu is completely silent with regards to the shape of the transferred portions but Adetutu does teach that these material portions can have any shape/size/dimension that is necessary to form the dissimilar material portion on the wafer ([0039-0043 and 0061-0063]).
Bahl teaches forming a transfer method wherein small portions of different semiconductor materials are transferred to a wafer and these transferred portions are used to make specific different types of devices on the same handle wafer (Figs. 1-5) and wherein the transferred material portions are separated out in a grid or checkerboard pattern having intersecting lines (Fig. 2).
PNG
media_image4.png
751
540
media_image4.png
Greyscale
It would have been obvious at the time of filing to alter the invention of Adetutu using the teachings in Bahl, specifically wherein the transferred portions are formed in a grid which would require the etched trenches of Adetutu to have intersecting lines.
The motivation to do so is that Adetutu is silent with regards to the top view shape of the transferred portions but Adetutu does teach that each of these portions is made for discrete individual or collections of NFETs and PFETs and making the transferred regions in a grid by etching around the perimeter of each transferred portion allows for discrete regions of active material for making NFETs and PFETs and the etched distance between adjacent transferred portions prevents these portions from bumping into other structures on the wafer when transferring.
Re claim 22, Adetutu and Bahl teach further comprising:
providing an additional donor wafer including an additional transfer material layer;
forming additional intersecting trenches through the additional transfer material layer to provide an additional array of additional transfer material plates; and
bonding the additional donor wafer to the acceptor wafer such that the additional array of the additional transfer material plates are bonded to the first dielectric oxide layer of the acceptor wafer without overlapping with the array of the transfer material plates (see rejection of claim 21 above and where Adetutu teaches that the wafer can be formed of active material structures having different surface orientations for different devices wherein the other surface orientation portions on the wafer can be formed by the same bonding technique as that described in Figs. 12-18 [0037-0054]. Bahl additionally teaches performing the transfer with multiple donor wafers (Figs. 1-4)).
Re claim 23, Bahl further teaches wherein the donor wafer and the additional donor wafer have respective maximum lateral dimensions that are less than one half of a maximum lateral dimension of the acceptor wafer (Figs. 3-4).
PNG
media_image5.png
441
484
media_image5.png
Greyscale
PNG
media_image6.png
452
468
media_image6.png
Greyscale
Re claim 24, Adetutu teaches wherein:
the transfer material plates comprise a first material selected from single crystalline silicon, single crystalline germanium, a single crystalline silicon-germanium alloy, single crystalline lithium niobate, single crystalline lithium tantalate, single crystalline zinc oxide, single crystalline titanium oxide, single crystalline indium tin oxide, single crystalline gallium oxide, single crystalline tin oxide, single crystalline tungsten trioxide, or single crystalline indium gallium zinc oxide ([0014, 0044-45]);
the first dielectric oxide layer comprises a material that is selected from undoped silicate glass, a doped silicate glass, or thermally-grown silicon oxide (while Adetutu does not explicitly teach how oxide layer 1403 is formed on the substrate Adetutu does teach forming silicon oxide layers by thermal oxidation [0017, 0036, 0044]); and
the transfer material plates are bonded directly to the first dielectric oxide layer (Figs. 14-15 [0046-0049]).
Re claim 26, Adetutu teaches a method of forming a composite wafer, the method comprising:
providing an acceptor wafer (wafer 1401) comprising a handle substrate (substrate layer 1402) and a first dielectric oxide layer (insulator layer e.g. silicon oxide [0046]) overlying the handle substrate;
providing a donor wafer (substrate 1203) comprising a carrier layer (portion of 1203 that lies below the damaged region) and a transfer material layer (portion of 1203 above damaged region 1207 which is later patterned and bonded to wafer 1401);
forming trenches (openings 1311, 1313, 1315, 1317) through the transfer material layer and a portion of the ion implantation layer in the donor wafer to provide an array of transfer material plates (Fig. 13);
attaching the transfer material layer of the donor wafer to the first dielectric oxide layer of the acceptor wafer either directly or through intermediate dielectric oxide plates (Figs. 14-15); and
cleaving the donor wafer along the ion implantation layer (Fig. 16) to transfer the array of transfer material plates onto the acceptor wafer (Figs. 12-18).
PNG
media_image1.png
443
528
media_image1.png
Greyscale
PNG
media_image2.png
728
504
media_image2.png
Greyscale
PNG
media_image3.png
690
492
media_image3.png
Greyscale
Adetutu does not explicitly teach wherein the patterns are intersecting lateral openings i.e. a grid. Adetutu is completely silent with regards to the shape of the transferred portions but Adetutu does teach that these material portions can have any shape/size/dimension that is necessary to form the dissimilar material portion on the wafer ([0039-0043 and 0061-0063]).
Bahl teaches forming a transfer method wherein small portions of different semiconductor materials are transferred to a wafer and these transferred portions are used to make specific different types of devices on the same handle wafer (Figs. 1-5) and wherein the transferred material portions are separated out in a grid or checkerboard pattern having intersecting lines (Fig. 2).
PNG
media_image4.png
751
540
media_image4.png
Greyscale
It would have been obvious at the time of filing to alter the invention of Adetutu using the teachings in Bahl, specifically wherein the transferred portions are formed in a grid which would require the etched trenches of Adetutu to have intersecting lines.
The motivation to do so is that Adetutu is silent with regards to the top view shape of the transferred portions but Adetutu does teach that each of these portions is made for discrete individual or collections of NFETs and PFETs and making the transferred regions in a grid by etching around the perimeter of each transferred portion allows for discrete regions of active material for making NFETs and PFETs and the etched distance between adjacent transferred portions prevents these portions from bumping into other structures on the wafer when transferring.
Re claim 27, Adetutu and Bahl further teach wherein:
the donor wafer comprises a plurality of donor wafers; and
the plurality of donor wafers transfers a plurality of arrays of transfer material plates to the acceptor wafer (see rejection of claim 26 above and where Adetutu teaches that the wafer can be formed of active material structures having different surface orientations for different devices wherein the other surface orientation portions on the wafer can be formed by the same bonding technique as that described in Figs. 12-18 [0037-0054] Bahl additionally teaches performing the transfer with multiple donor wafers (Figs. 1-4)).
Re claim 29, Adetutu teaches wherein:
the donor wafer comprises an ion implantation layer (damaged region 1207 formed by hydrogen ions implanted into 1203) overlying the carrier layer, interposed between the carrier layer and the transfer material layer (Fig. 12);
the ion implantation layer remains free of any lateral recess when the transfer material plates are attached to the first dielectric oxide layer (Figs. 12-18); and
the transfer material plates are attached to the first dielectric oxide layer while the ion implantation layer is free of any lateral recess (Figs. 12-18).
Re claim 30, Adetutu teaches wherein the transfer material layer comprises a material selected from single crystalline silicon, single crystalline germanium, a single crystalline silicon- germanium alloy, single crystalline lithium niobate, single crystalline lithium tantalate, single crystalline zinc oxide, single crystalline titanium oxide, single crystalline indium tin oxide, single crystalline gallium oxide, single crystalline tin oxide, single crystalline tungsten trioxide, or single crystalline indium gallium zinc oxide ([0014, 0044-0045]).
Allowable Subject Matter
Claims 10, 25, 28 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20200303242 A1 (Ghyselen) which teaches patterning and transferring portions of lithium niobate onto copper sheets (Example 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896