DETAILED ACTION
This application, 18/470614, attorney docket 2023-0923/24061.4839US01, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Taiwan Semiconductor Manufacturing Company, Ltd., and claims priority from provisional application 63509665 , filed 06/22/2023. Applicant's election with traverse of Group I, claims 1-15 in the reply filed on 7/30/2025 is acknowledged. Claims 16-20 were cancelled by the applicant. Applicant traversed the restriction to identify the typographical error in the restriction which identified both groups as method claims. Because the attendant text describing the difference made it clear that claims 16-20 are device claims, the requirement is still deemed proper and is therefore made FINAL. Claims 1-15 and new claims 21-25 are pending and are considered below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 2 is rejected under 35 U.S.C. 112(a) because the specification, while being enabling for a fin formed with a germanium layer, does not reasonably provide enablement for forming a germanium layer on a fin. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims. The disclosure does not teach how to form a fin then deposit the germanium layer as required by claim 2, which recites. “forming a germanium layer over a silicon fin ….the forming includes at least one of deposition of the germanium layer”
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 recites the limitation "the forming.” “The forming” could be forming the channel region or the gate structure. There is insufficient antecedent basis for this limitation in the claim.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 5 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. “On does not distinguish from “over.” Examiner assumes applicant intended to mean “in direct contact with”. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 4-7 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by McArdle et al. (U.S. 2017/0033181).
As for claim 1,
McArdle teaches in figure 2a-2J the method of fabricating a semiconductor device comprising:
forming a channel region of the semiconductor device, wherein forming the channel region includes:
providing a germanium-comprising layer (110A); and
depositing a crystalline silicon layer (114A) on the germanium-comprising layer;
and forming a gate structure (122a/122b) over a first surface and a second surface, the second surface opposing the first surface.
As for claim 2,
McArdle teaches the method of claim 1, wherein the providing the germanium-comprising layer includes forming a germanium layer over a silicon fin (106, fig. 2B), wherein the forming includes at least one of deposition of the germanium layer or diffusion of germanium to form the germanium layer. (epitaxial deposition [00314]).
As for claim 4,
McArdle teaches the method of claim 1, wherein the providing the germanium-comprising layer includes forming a fin structure having a first portion comprising silicon (106) and the germanium-comprising layer (110A) over the first portion.
As for claim 5,
McArdle teaches the method of claim 4, wherein the germanium-comprising layer includes forming silicon germanium on the first portion comprising silicon.(the layers are in direct contact in figure 2d)
As for claim 6,
McArdle teaches the method of claim 1, wherein the providing the germanium-comprising layer includes: providing a silicon substrate (102/104);
etching a recess in the silicon substrate (fig 2B);
growing the germanium-comprising layer in the recess; and
etching a fin structure including a portion of the silicon substrate and the germanium- comprising layer. (104 is etched in figure 2J [0037])
As for claim 7,
McArdle teaches the method of claim 1, wherein at least one of the first surface and the second surface is the crystalline silicon layer. (both sides include silicon layers in figure 2J).
Claims 8-9, 11-12, 14 and 21-24 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Lin et al. (U.S. 2021/0125859), also assigned to Taiwan Semiconductor, but to another inventive entity, and published more than one year before the effective filing date of this application.
As for claim 8,
Lin teaches in figures 2-18 a method, comprising:
forming a trench (22) in a silicon substrate (20);
forming a germanium comprising layer (24-1, [0018]) on the silicon substrate including in the trench;
depositing a crystalline silicon material 34-1, [0027]) over the germanium comprising layer;
patterning the crystalline silicon material, silicon germanium comprising layer, and the silicon substrate to form a fin structure (figure 15), wherein the fin structure includes a lower portion comprising the silicon substrate (48), a middle portion comprising the germanium comprising layer (24-1), and an upper portion comprising the crystalline silicon material (34-n); and
forming a gate structure extending over the fin structure (56, fig. 18).
As for claim 9,
Lin teaches the method of claim 8, wherein the forming the gate structure includes:
depositing a gate dielectric layer (54) interfacing an upper surface of the upper portion comprising the crystalline silicon material.
As for claim 11,
Lin teaches the method of claim 8, and ,Lin teaches in figure 15,
patterning the crystalline silicon material and a second region of the silicon substrate (left and right of figure) to form another fin structure, wherein the crystalline silicon material is disposed directly on the second region of the silicon substrate (shown in figure 13).
As for claim 12,
Lin teaches the method of claim 11, wherein the forming the gate structure extending over the fin structure includes forming the gate structure over another fin structure.(shown in figure 18a).
As for claim 14,
Lin teaches the method of claim 8, further comprising: forming another recess in the fin structure adjacent the gate structure; and growing an epitaxial source/drain feature in another recess. ([0041]).
As for claim 21,
Lin teaches in figures 2-18 a method for fabricating a semiconductor device, comprising:
providing a silicon substrate (20);
forming a first channel region disposed over the silicon substrate; forming the forming the first channel region includes:
forming a first semiconductor material (24-1),
forming a germanium comprising layer (34-1) on the first semiconductor material, and
forming a crystalline silicon layer (24-n) on the germanium comprising layer;
and providing a gate structure (54/56) on at least two surfaces of the first channel region.
As for claim 22,
Lin teaches the method of fabricating the semiconductor device of claim 21, wherein the forming the first channel region includes providing the first semiconductor material as a silicon nanostructure (layers are nanosheets [0002]).
As for claim 23,
Lin teaches the method of fabricating the semiconductor device of claim 21, wherein forming the first channel region includes forming the first semiconductor material as a fin structure extending from the silicon substrate. (fig 15).
As for claim 24,
Lin teaches the method of fabricating the semiconductor device of claim 21, wherein the forming the germanium comprising layer includes depositing a germanium layer directly on a sidewall of the first semiconductor material. (34-1 deposited on 24-1 sidewall at top of trench in figure 7) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over McArdle in view of Reznicek et al. (U.S. 2013/0334571)
As for claim 3,
McArdle teaches the method of claim 1, but does not teach forming the providing the germanium-comprising layer includes depositing a germanium layer over a silicon germanium nanostructure, wherein the forming includes diffusion of germanium to form the germanium layer.
However, Reznicek teaches forming a germanium layer by depositing a seed layer (nanostructure) and diffusing it into the silicon layer [0005].
It would have been obvious to one skilled in the art at the effective filing date of this application to use the seed layer/diffusion method of Reznicek in the method of McArdle to improve the surface roughness of the and reduce lattice mismatch stress. [0005]. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Rachmady et al. (U.S. 8748940).
As for claim 10,
Lin teaches the method of claim 9, but does not teach that the forming the gate structure includes depositing a gate dielectric layer interfacing a sidewall of the germanium comprising layer.
However, Rachmady teaches that the forming the gate structure includes depositing a gate dielectric layer interfacing a sidewall of the germanium comprising layer. (the silicon layer is used as the sacrificial layer, preserving the germanium containing layer as the channel to contact the gate dielectric. (Rachmady, [co6 ln65+]).
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute the materials of Rachmady for the materials of Lin because using the silicon leaves the SiGe, which has a different channel characteristics, that may be advantageous to devices with different Vts. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Xie (U.S. 2018/0301531).
As for claim 13,
Lin teaches the method of claim 8, but does not teach that the depositing the crystalline silicon material includes introducing a precursor of at least one of silane (SiH4) or disilane (Si2H6).
However, Xie teaches depositing a silicon layer by introducing a precursor of at least one of silane (SiH4) [0036].
It would have been obvious to one skilled in the art at the effective filing date of this application to use silane as a Si sourced gas because Silane precursor deposition is a known technique for CVD of silicon and one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Cheng et al (U.S. 9496341).
As for claim 15,
Lin teaches the method of claim 8, but does not teach the patterning the crystalline silicon material, germanium comprising layer, and the silicon substrate to form the fin structure includes: forming a hard mask layer directly on the crystalline silicon material; patterning the hard mask layer; and using the patterned hard mask layer as a masking element when patterning the crystalline silicon material, germanium comprising layer, and the silicon substrate.
However, Cheng teaches in figure 4 forming fins(pillars) using a hardmask (18).
It would have been obvious to one skilled in the art at the effective filing date of this application to use a hardmask to pattern the stack because a hardmask allows a deeper isotropic etch than a polymer mask. One skilled in the art would have combined these elements with a reasonable expectation of success.
Allowable Subject Matter
Claim 25 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As for claim 25
The following is a statement of reasons for the indication of allowable subject matter: .
Lin teaches the method of fabricating the semiconductor device of claim 21, but the prior art does not teach or make obvious providing a curvilinear upper surface of the crystalline silicon layer as one of the at least two surfaces of the first channel region.
Conclusion
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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