DETAILED ACTION
This application, 18/470614, attorney docket 2023-0923/24061.4839US01, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Taiwan Semiconductor Manufacturing Company, Ltd., and claims priority from provisional application 63509665, filed 06/22/2023. Claims 1-15 and new claims 21-25 are pending and are considered below.
Response to Arguments
Applicant has amended claim 2 and correctly argues that the amendment overcomes the §112a of that claim, which is withdrawn.
The applicant has amended claim 3 to clarify what is being formed. and correctly argues that the amendment overcomes the §112b of that claim, which is withdrawn.
Applicant has amended claim 5 and correctly argues that the amendment overcomes the §112d of that claim because depositing is more specific than forming., which is withdrawn
Applicant has amended claim 21 to include the allowed limitation of claim 25 and correctly argues that the amendment renders claim 21 and its dependents allowable.
Applicant has amended claim to include the limitation that “the first silicon comprising layer provides a bottommost point of the channel region, and the crystalline silicon layer provides a topmost point of the channel region,
and wherein the germanium-comprising layer extends between the first silicon comprising layer and the crystalline silicon layer”
McArdle teaches the germanium layer is one of several that are each separated by layers of silicon germanium, and applicant argues that the amendment distinguishes from McArdle. Examiner disagrees. McArdle teaches in paragraph [0036] and [0021] that the embodiment shown is not limited to 10 layers but may be any number that meets the design requirement and may be an even or odd number of layers, so One skilled would understand that McArdle teaches a channel comprising the bulk silicon and one layer each of SiGe and epitaxial silicon.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over McArdle et al. (U.S. 2017/0033181).
As for claim 1,
McArdle teaches in figure 2a-2J the method of fabricating a semiconductor device comprising:
forming a channel region of the semiconductor device, wherein forming the channel region includes:
providing a first silicon comprising layer (102, Bulk silicon [0025]);
providing a germanium-comprising layer (deposited, [0031] 110A); and
depositing a crystalline silicon layer (epitaxially deposited [0034], 114A) on the germanium-comprising layer;
and forming a gate structure (122a/122b) over the channel region, and teaches that the first silicon comprising layer provides a bottommost point of the channel region and the crystalline silicon layer provides a topmost point of the channel region (the gate extends from the top portion of the bulk silicon fin to the top epitaxial layer in figure 2J , and McArdle makes obvious that the germanium-comprising layer extends between the first silicon comprising layer and the crystalline silicon layer.
As discussed above, McArdle teaches that the stack of alternating semiconductors can be any number without requiring a new method [0035], and a stack of one SiGe layer and one Si epitaxial layer is an obvious variant, which reads on the limitation “he germanium-comprising layer extends between the first silicon comprising layer and the crystalline silicon layer”
it has been held by the courts to omit, eliminate, or remove a known step or element if the function of said step or element is not desired. Ex parte Wu, 10 USPQ 2031 (Bd. Pat. App. & Inter. 1989); See In reLarson, 340 F.2d 965, 144 USPQ 347 (CCPA 1965); See In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (deleting a prior art switch member and thereby eliminating its function was an obvious expedient). Here it would have been obvious to remove the additional semiconductor layers from the stack if one did not want the function of layers because the layer allows higher drive current. Thus, it would have been obvious to remove said limitation.
As for claim 2,
McArdle makes obvious the method of claim 1, wherein the providing the germanium-comprising layer includes forming a germanium layer over the first silicon comprising layer of a silicon fin (106, fig. 2B), wherein the forming includes at least one of deposition of the germanium layer or diffusion of germanium to form the germanium layer. (epitaxial deposition [0034]).
As for claim 4,
McArdle makes obvious the method of claim 1, wherein the providing the germanium-comprising layer includes forming the first silicon comprising layer of a fin structure having a first portion comprising silicon and the germanium-comprising layer interfacing the first portion. (The silicon fin portion is formed in figure 2b by etching the Si fin to the final height and 2E by depositing the SiGe layer and etching the height to form the first portion.)
As for claim 5,
McArdle makes obvious the method of claim 4, wherein the germanium-comprising layer includes depositing silicon germanium on the first portion comprising silicon. ([0034).
As for claim 6,
McArdle teaches the method of claim 1, wherein the providing the germanium-comprising layer includes: providing a silicon substrate (102/104);
etching a recess in the silicon substrate (fig 2B);
growing the germanium-comprising layer in the recess (epitaxy is a crystal growth); and
etching a fin structure including a portion of the silicon substrate to provide the first silicon comprising layer and the germanium- comprising layer. (the SiGe layer 110 is etched in figure 2E to thickness 114T [0035]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over McArdle in view of Reznicek et al. (U.S. 2013/0334571)
As for claim 3,
McArdle makes obvious the method of claim 1 but does not teach providing the germanium-comprising layer includes diffusion from the first silicon comprising layer of a silicon germanium nanostructure to form the germanium layer.
However, Reznicek teaches forming a germanium layer by depositing a seed layer (nanostructure) and diffusing it into the silicon layer [0005] to form an SiGe layer..
It would have been obvious to one skilled in the art at the effective filing date of this application to use the seed layer/diffusion method of Reznicek in the method of McArdle to improve the surface roughness of the and reduce lattice mismatch stress. [0005]. One skilled in the art would have combined these elements with a reasonable expectation of success.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As for claim 7,
McArdle teaches the method of claim 1, but the prior art does not teach or make obvious the stacked channel wherein the gate structure engages a curvilinear upper surface of the crystalline silicon layer.
Claims 8-5 and 21-25 are allowed.
As for claim 8,
The prior art does not teach or make obvious the stacked channel wherein the patterning provides a curvilinear top surface of the crystalline silicon material.
Claims 9-15 depend from claim 8 and include the same novel limitation.
As for claim 21
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or make obvious providing a curvilinear upper surface of the crystalline silicon layer as one of the at least two surfaces of the first channel region, as required by claim 21.
Claims 22-25 depend from claim 21 and include the same novel limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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