DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 27 is objected to because of the following informalities: line 11: “as least” should be corrected to “at least” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-7, 18-19, 24, and 50 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mieczkowski et al. (U.S. Publication No. 2011/0227089 A1; hereinafter Mieczkowski)
With respect to claim 1, Mieczkowski discloses a semiconductor device, comprising: a wide bandgap semiconductor structure [212]; a metal structure on the wide bandgap semiconductor structure; and wherein the metal structure comprises a metal layer [160], the metal layer comprising a metal selected from the group consisting of ruthenium, osmium, rhodium, or iridium (See ¶[0032]; Iridium), wherein the metal structure further comprises at least one of a diffusion barrier layer [180], an adhesion layer [810], or a conductive layer [170] on the metal layer [160] (see Figure 2 and ¶[0034]; diffusion barrier layer, adhesion layer and conductive layers are all present).
With respect to claim 5, Mieczkowski discloses wherein the metal is iridium (see ¶[0032]).
With respect to claim 6, Mieczkowski discloses wherein the metal structure is a Schottky contact with the wide bandgap semiconductor structure (see Figure 2).
With respect to claim 7, Mieczkowski discloses wherein the metal structure is a gate contact on the wide bandgap semiconductor structure (See Figure 2).
With respect to claim 18, Mieczkowski discloses wherein the metal structure does not include nickel (See ¶[0032]; metal is selected independently, therefore nickel can be avoided in favor of iridium).
With respect to claim 19, Mieczkowski discloses wherein the wide bandgap semiconductor structure comprises a Group III-nitride (See ¶[0023]).
With respect to claim 24, Mieczkowski discloses wherein the semiconductor device is a high electron mobility transistor (See Figure 2 and ¶[0022]).
With respect to claim 50, Mieczkowski discloses a method of forming a semiconductor device, comprising: forming a wide bandgap semiconductor structure [212] on a substrate [320]; forming a gate contact [150] on the wide bandgap semiconductor structure; and wherein the gate contact comprises a metal layer [160], the metal layer comprising a metal selected from the group consisting of ruthenium, osmium, rhodium, or iridium (see ¶[0032]; Iridium); and wherein the metal structure further comprises at least one of a diffusion barrier layer [180], an adhesion layer [810], or a conductive layer [170] on the metal layer [160] (see Figure 2 and ¶[0034]; diffusion barrier layer, adhesion layer and conductive layers are all present).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 8-9, 12, 15, 18, and 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagida et al. (U.S. Publication No. 2023/0290888 A1; hereinafter Yanagida) in view of Mieczkowski
With respect to claim 1, Yanagida discloses a semiconductor device, comprising: a wide bandgap semiconductor structure [101]; a metal structure on the wide bandgap semiconductor structure; and wherein the metal structure comprises a metal layer [105b], the metal layer comprising a metal selected from the group consisting of ruthenium, osmium, rhodium, or iridium (See ¶[0070]). Yanagida fails to disclose wherein the metal structure further comprises at least one of a diffusion barrier layer, an adhesion layer, or a conductive layer on the metal layer. In the same field of endeavor, Mieczkowski teaches wherein the metal structure further comprises at least one of a diffusion barrier layer [180], an adhesion layer [810], or a conductive layer [170] on the metal layer [160] (see Figure 3 and ¶[0034]; diffusion barrier layer, adhesion layer and conductive layers are all present). Implementation of the multilayer structure of Mieczkowski of a diffusion barrier layer prevents leakage current increase from the metal layer [160] (see ¶[0025]).
the adhesion layer bonds barrier layers together (see ¶[0034]) and the conductive layer enhances the conductivity of the gate and lowers gate resistance (see ¶[0026]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Yanagida and Mieczkowski discloses wherein the metal is ruthenium (See Yanagida ¶[0070]).
With respect to claim 3, the combination of Yanagida and Mieczkowski discloses wherein the metal is osmium (See Yanagida ¶[0070]).
With respect to claim 4, the combination of Yanagida and Mieczkowski discloses wherein the metal is rhodium (See Yanagida ¶[0070]).
With respect to claim 5, the combination of Yanagida and Mieczkowski discloses wherein the metal is iridium (See Yanagida ¶[0070] and Mieczkowski ¶[0031]; Iridium).
With respect to claim 8, the combination of Yanagida and Mieczkowski discloses wherein a thickness of the metal layer is in a range of about 50 Angstroms to about 200 Angstroms (see Yanagida ¶[0070]).
With respect to claim 9, the combination of Yanagida and Mieczkowski discloses wherein the adhesion layer comprises platinum, wherein a thickness of the adhesion layer is about 50 Angstroms to about 300 Angstroms (See Yanagida ¶[0070] and ¶[0073] and Mieczkowski ¶[0034]; other metals with good adhesion characteristics, Platinum is utilized throughout the diffusion/adhesion layers).
With respect to claim 12, the combination of Yanagida and Mieczkowski wherein the diffusion barrier layer comprises titanium, wherein a thickness of the diffusion barrier layer is about 100 Angstroms to about 300 Angstroms (See Yanagida ¶[0073] and Mieczkowski ¶[0034]).
With respect to claim 15, the combination of Yanagida and Mieczkowski discloses wherein the conductive layer comprises gold, wherein a thickness of the conductive layer is about 1000 Angstroms to about 6000 Angstroms (See Yanagida ¶[0073] and Mieczkowski ¶[0026]).
With respect to claim 18, the combination of Yanagida and Mieczkowski discloses wherein the metal structure does not include nickel (See Yanagida ¶[0070] and Mieczkowski ¶[0031]; Iridium).
With respect to claim 25, the combination of Yanagida and Mieczkowski discloses wherein the semiconductor device is a Schottky diode (see Yanagida ¶[0104]).
With respect to claim 26, the combination of Yanagida and Mieczkowski discloses wherein the semiconductor device is a MOSFET (see Yanagida ¶[0079]).
Claim(s) 21 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mieczkowski in view of Tu et al. (U.S. Publication No. 2023/0352574 A1).
With respect to claim 21, Mieczkowski fails to disclose wherein the wide bandgap semiconductor structure further comprises a barrier layer, a channel layer, and a two-dimensional electron gas (2DEG) at an interface between the channel layer and the barrier layer but does disclose a channel structure with a 2DEG between the source and drain regions (See ¶[0003]). In the same field of endeavor, Tu teaches wherein the wide bandgap semiconductor structure further comprises a barrier layer [120], a channel layer [110], and a two-dimensional electron gas (2DEG) [115] at an interface between the channel layer and the barrier layer (see Figure 1A) Both Tu and Mieczkowski are HEMT structures. Integration of Tu’s specific orientation of the barrier layer, channel and 2DEG allows for more control of the depletion region for specific applications (see Tu ¶[0057]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 23, the combination of Mieczkowski and Tu discloses wherein the wide bandgap semiconductor structure is on a substrate [230], the substrate comprising silicon carbide (see Mieczkowski ¶[0023]).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tu in view of Mieczkowski
With respect to claim 27, Tu discloses a transistor device, comprising: a substrate [101]; a Group III-nitride semiconductor structure on the substrate, the Group III-nitride semiconductor structure comprising a barrier layer [120] and a channel layer [110], the barrier layer having a different bandgap relative to the channel layer (see ¶[0050]); a gate contact [150], source contact [130], and a drain contact [140], wherein the gate contact is between the source contact and the drain contact; and wherein the gate contact comprises a plurality of gate stack layers [150/170], wherein at least one of the gate stack layers is a metal layer comprising a metal selected from the group consisting of ruthenium, osmium, rhodium, or iridium (See ¶[0051]; Iridium). Tu fails to disclose wherein the metal structure further comprises as least one of a titanium layer, a platinum layer, a gold layer, a copper layer, and a silver layer on the metal layer
In the same field of endeavor, Mieczkowski teaches wherein the metal structure further comprises as least one of a titanium layer, a platinum layer, a gold layer, a copper layer, and a silver layer on the metal layer (see Figure 7). Implementation of the multilayer structure of Mieczkowski of multiple metals prevents leakage current increase from the metal layer [160] (see Mieczkowski ¶[0025]), bonds barrier layers together (see Mieczkowski ¶[0034]) and enhances the conductivity of the gate and lowers gate resistance (see Mieczkowski ¶[0026]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Response to Arguments
Applicant's arguments with respect to claims 1-9, 12, 18, 19, 21, 23-27 and 50 have been considered and are persuasive but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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