DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-9 and 16-20, and additionally 21-26, in the reply filed on 3/16/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show signal routes as described in the specification. Note that in FIG. 1, the label “Signal Routes 106” points to an empty space in the drawing. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
The drawings are objected to because:
In FIGS. 1-4 and 11, layers (shaded layers and empty layers in between) are not labeled in the drawings.
In FIGS. 1-4 and 11, the box within the near bottom layer (box under “Defect 112” in FIG. 1, for example) is not labeled in the drawings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 2022/0020665) in view of Dubey (US 2020/0076424).
Regarding claim 1, Li discloses, in FIG. 4 and in related text, a semiconductor device, comprising:
a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back-side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes (coupled to pTSV I/O bumps 450-a and 450-b) and the back-side BEOL stack comprising a plurality of power delivery routes (Vdd, Vss); and
a plurality of auxiliary paths (circled paths, see annotation of FIG. 4 below) formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of switches (transistors P-gate 421 and N-gate 422), the plurality of power delivery routes, the plurality of switches, and the plurality of auxiliary paths forming a power delivery network (PDN) (see Li, [0002], [0044], [0049], [0053]-[0054], [0063]-[0066]).
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Li does not explicitly disclose a plurality of auxiliary power paths; a plurality of programmable switches; a programmable power delivery network.
Dubey teaches a network including a path (46-1, 46-2 in FIG. 1; 46R in FIG. 2) delivering power (Vcc1 in FIG. 2) that is turned on or off (gated) with a programmable switch (38-1, 38-2 in FIG. 1; transistor 38S in FIG. 2) controlled by a processor executing program code instructions (see Dubey, FIGS. 1-2, [0023]-[0024], [0035]-[0036], [0067]). Therefore, Dubey teaches a plurality of auxiliary power paths; a plurality of programmable switches; a programmable power delivery network.
Li and Dubey are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li with the features of Dubey because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Li to include a plurality of auxiliary power paths; a plurality of programmable switches; a programmable power delivery network, as taught by Dubey, to selectively interrupt or not interrupt a flow of current to a power management region (see Dubey, [0067]).
Regarding claim 5, Li in view of Dubey teaches the device of claim 1.
Li discloses wherein: the plurality of power delivery routes (Vdd, Vss) included in the back-side BEOL stack are disposed parallel to one another along a first direction (vertical direction) and in a first common plane; and
the plurality of auxiliary power paths (horizontal portions in the circled paths) formed within the front-side BEOL stack are disposed parallel to one another in a second common plane parallel to the first common plane and in a second direction (horizonal direction) that is orthogonal to the first direction (see annotation of FIG. 4 of Li above).
Regarding claim 6, Li in view of Dubey teaches the device of claim 5.
Dubey teaches wherein each of the plurality of programmable switches (38-1, 38-2), when in a closed position, electrically couples at least one of the plurality of power delivery routes (18) to at least one of the plurality of auxiliary power paths (46-1, 46-2) (see Dubey, FIGS. 1-2, [0023]-[0024], [0035]-[0036]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 2022/0020665) in view of Dubey (US 2020/0076424) and Wikipedia (Wikipedia, von Neumann architecture, archived 3 January 2022).
Regarding claim 16, Li discloses, in FIG. 4 and in related text, a system comprising:
a semiconductor device comprising:
a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back-side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes (coupled to pTSV I/O bumps 450-a and 450-b) and the back-side BEOL stack comprising a plurality of power delivery routes (Vdd, Vss);
a plurality of auxiliary paths (circled paths, see annotation of FIG. 4 below) formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of switches (transistors P-gate 421 and N-gate 422), the plurality of power delivery routes, the plurality of switches, and the plurality of auxiliary paths forming a power delivery network (PDN), a control device (PMCI 440) communicatively coupled to the PDN (see Li, [0002], [0044], [0049], [0053]-[0054], [0063]-[0066]).
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Li does not explicitly disclose:
a plurality of auxiliary power paths; a plurality of programmable switches; a programmable power delivery network;
the control device comprising:
a receiving module, stored in memory, that receives an instruction to adjust the programmable PDN included in a silicon stack;
an adjusting module, stored in memory, that adjusts the programmable PDN in response to receiving the instruction; and
at least one physical processor that executes the receiving module and the adjusting module.
Dubey teaches a network including a path (46-1, 46-2 in FIG. 1; 46R in FIG. 2) delivering power (Vcc1 in FIG. 2) that is turned on or off (gated) with a programmable switch (38-1, 38-2 in FIG. 1; transistor 38S in FIG. 2) controlled by a processor executing program code instructions; the program code instructions receive/detect conditions and control the programmable switch (see Dubey, FIGS. 1-2, [0023]-[0024], [0035]-[0036], [0067]). Therefore, Dubey teaches a plurality of auxiliary power paths; a plurality of programmable switches; a programmable power delivery network; the control device comprising: a receiving module (program code instructions), that receives an instruction to adjust the programmable PDN included in a silicon stack; an adjusting module (program code instructions), that adjusts the programmable PDN in response to receiving the instruction; and at least one physical processor that executes the receiving module and the adjusting module.
Li and Dubey are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li with the features of Dubey because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Li to include a plurality of auxiliary power paths; a plurality of programmable switches; a programmable power delivery network; the control device comprising: a receiving module, that receives an instruction to adjust the programmable PDN included in a silicon stack; an adjusting module, that adjusts the programmable PDN in response to receiving the instruction; and at least one physical processor that executes the receiving module and the adjusting module, as taught by Dubey, to selectively interrupt or not interrupt a flow of current to a power management region (see Dubey, [0067]).
Dubey does not explicitly teach a receiving module, stored in memory; an adjusting module, stored in memory. Dubey does not explicitly teach that the program code instructions for receiving and adjusting are stored in a memory.
Wikipedia teaches a von Neumann computer architecture that includes a processor executing instructions stored in a memory (see Wikipedia, page 1). Therefore, Wikipedia together with Dubey teaches a receiving module, stored in memory; an adjusting module, stored in memory.
Li and Wikipedia are analogous art because they both are directed to processor systems and one of ordinary skill in the art would have had a reasonable expectation of success to further modify Li with the features of Wikipedia because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Li as already modified by Dubey, to include a receiving module, stored in memory; an adjusting module, stored in memory, as taught by Wikipedia, to provide a simple architecture to store instructions (see Wikipedia, page 1).
Regarding claim 17, Li in view of Dubey and Wikipedia teaches the system of claim 16.
Dubey teaches wherein the adjusting module (program code instructions) adjusts the programmable PDN by adjusting an activation state of at least one of the plurality of programmable switches (power gating transistor) (see Dubey, [0067] and discussion on claim 16 above), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 16.
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 2022/0020665) in view of Dubey (US 2020/0076424).
Regarding claim 22, Li discloses, in FIG. 4 and in related text, a semiconductor device, comprising:
a front-side comprising a plurality of signal routes (coupled to pTSV I/O bumps 450-a and 450-b) and a back-side comprising a plurality of power delivery routes (Vdd, Vss); and
a plurality of auxiliary paths (circled paths, see annotation of FIG. 4 below) formed within the front-side and electrically coupled to the plurality of power delivery routes of the back-side via a plurality of switches (transistors P-gate 421 and N-gate 422) (see Li, [0002], [0044], [0049], [0053]-[0054], [0063]-[0066]).
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Li does not explicitly disclose a plurality of auxiliary power paths; a plurality of programmable switches.
Dubey teaches a network including a path (46-1, 46-2 in FIG. 1; 46R in FIG. 2) delivering power (Vcc1 in FIG. 2) that is turned on or off (gated) with a programmable switch (38-1, 38-2 in FIG. 1; transistor 38S in FIG. 2) controlled by a processor executing program code instructions (see Dubey, FIGS. 1-2, [0023]-[0024], [0035]-[0036], [0067]). Therefore, Dubey teaches a plurality of auxiliary power paths; a plurality of programmable switches.
Li and Dubey are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li with the features of Dubey because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Li to include a plurality of auxiliary power paths; a plurality of programmable switches, as taught by Dubey, to selectively interrupt or not interrupt a flow of current to a power management region (see Dubey, [0067]).
Regarding claim 23, Li in view Dubey teaches the device of claim 22.
Li in view of Dubey teaches wherein the plurality of power delivery routes (Vss, Vdd in FIG. 4 of Li), the plurality of programmable switches (P-gate 421 and N-gate 422 in FIG. 4 of Li), and the plurality of auxiliary power paths (circled path in annotation of FIG. 4 of Li above) form a programmable power delivery network (PDN); and wherein the semiconductor device is configured to receive an instruction to adjust the programmable PDN and adjust the programmable PDN in response to receiving the instruction (see Li, FIG. 4, [0065]; Dubey, [0067]; discussion on claim 22 above), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 22 above.
Regarding claim 24, Li in view Dubey teaches the device of claim 22.
Dubey teaches wherein the semiconductor device is configured to adjust the programmable PDN by adjusting an activation state of at least one of the plurality of programmable switches (see Dubey, [0067]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 22 above.
Allowable Subject Matter
Claims 2-4, 7-9, 18-21 and 25-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, Li, discloses wherein: a first auxiliary power path included in the plurality of auxiliary power paths is electrically coupled, via a first switch included in the plurality of programmable switches, to a positive supply voltage terminal; a second auxiliary power path included in the plurality of auxiliary power paths is electrically coupled, via a second switch included in the plurality of programmable switches, to a negative supply voltage terminal. The prior art of records, individually or in combination, do not disclose nor teach “when electrical power is applied to the silicon stack via the plurality of power delivery routes and the first switch and the second switch are both in a closed position, a power supply voltage flows via the first auxiliary power path and the second auxiliary power path between the positive supply voltage terminal and the negative supply voltage terminal” in combination with other limitations as recited in claim 2.
The prior art of records, individually or in combination, do not disclose nor teach “wherein: a first auxiliary power path included in the plurality of auxiliary power paths is electrically coupled, via a first switch included in the plurality of programmable switches, to a first clock signal terminal; a second auxiliary power path included in the plurality of auxiliary power paths is electrically coupled, via a second switch included in the plurality of programmable switches, to a second clock signal terminal; and when electrical power is applied to the silicon stack via the plurality of power delivery routes and the first switch and the second switch are both in a closed position, a clock signal propagates between the first clock signal terminal and the second clock signal terminal via the first auxiliary power path and the second auxiliary power path” in combination with other limitations as recited in claim 4.
The prior art of record, Li, discloses a carrier wafer layer. The prior art of records, individually or in combination, do not disclose nor teach “a thermal oxide bond layer, formed between and bonding the carrier wafer layer and the front-side BEOL stack; an active interposer die (AID) layer; and a hybrid copper bond layer formed between and bonding the back-side BEOL stack and the AID layer” in combination with other limitations as recited in claim 7.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the receiving module: further detects, within the programmable PDN, a change in resistance of greater than a threshold resistance value; and receives the instruction to adjust the programmable PDN by receiving the instruction in response to detecting the change of resistance.” in combination with other limitations as recited in claim 18.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the semiconductor device is configured to adjust the programmable PDN to bypass a defect within the power delivery route” in combination with other limitations as recited in claim 25.
The prior art of records, individually or in combination, do not disclose nor teach “further configured to detect a change in resistance within the programmable PDM and send an instruction to adjust the programmable PDN in response to detecting the change of resistance” in combination with other limitations as recited in claim 26.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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