DETAILED ACTION
This Office Action is in response to Applicant’s application 18/471,233 filed on September 20, 2023 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on September 20, 2023 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS), filed on October 29, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
During examination, a claim must be given its broadest reasonable interpretation consistent with the specification as it would be interpreted by one of ordinary skill in the art. 76 Fed. Reg. 7164 (February 9, 2011). During examination, after applying the broadest reasonable interpretation to the claim, if the metes and bounds of the claimed invention are not clear, the claim is indefinite and should be rejected. Id. at 7165. When a term of degree is used in the claim, the examiner should determine whether the specification provides some standard for measuring that degree. Id. at 7165. If the specification does not provide some standard for measuring that degree, a determination must be made as to whether one of ordinary skill in the art could nevertheless ascertain the scope of the claim (e.g., a standard that is recognized in the art for measuring the meaning of the term of degree). Id. at 7165.
Here Applicant recites “low-melting-temperature’ for which the specification does not provide a standard for measuring ‘low-melting-temperature’. Furthermore, a person of ordinary skill in the art could not ascertain the scope of the claim as ‘low-melting temperature' has no recognized standard in the semiconductor art. Accordingly, Examiner determines that those skilled in the art would not understand what is claimed when the claim is read in light of the specification and claim 2 is indefinite pursuant to requirements and examination guidelines for 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. 2018/0151472 (Chen).
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Regarding claim 1 and referring to annotated Figure 2, Chen discloses a package structure, comprising:
a package substrate, 109 [0023];
an interposer module, 106 [0024], on the package substrate, as shown;
a thermal interface material (TIM) layer, 102 [0029], on the interposer module, as shown; and
a package lid, 101 [0029], on the TIM layer, as shown, comprising:
a package lid foot portion, 101b [0028], attached to the package substrate, as shown;
a package lid plate portion, 101c [0028], connected to the package lid foot portion, as shown; and
a plurality of fins, 101a [0029], extending from the package lid plate portion into the TIM layer over the interposer module, as shown.
Regarding claim 2 which depends upon claim 1, Chen teaches the TIM layer comprises a low-melting-temperature metal, e.g. Indium [0029].
Regarding claim 3 which depends upon claim 2, Chen teaches the low-melting-temperature metal comprises at least one of indium, gallium, silver or tin at [0029].
Regarding claim 4 which depends upon claim 1, Chen teaches the package lid plate portion comprises a bottom surface, as annotated, adjoining the package lid foot portion, as shown, and the plurality of fins extend from the bottom surface, as shown.
Regarding claim 5 which depends upon claim 4, Chen teaches the TIM layer contacts the bottom surface of the package lid plate portion in a gap, as annotated and shown, between the plurality of fins, 101a.
Regarding claim 6 which depends upon claim 1, Chen teaches the TIM layer has a first thickness, as annotated, between a bottom surface of the package lid plate portion and the interposer module and a second thickness, as annotated, less than the first thickness, as shown, between the plurality of fins and the interposer module, as shown.
Regarding claim 7 which depends upon claim 1, Chen teaches a thickness of the plurality of fins is in a range from 25 μm to 100 μm at [0034] i.e., 50 to 100 microns.
Regarding claim 9 which depends upon claim 1, Chen teaches a width of the plurality of fins is in a range from 100 μm to 1000 μm at [0034], i.e., 100 to 1500 microns.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding claim 8 which depends upon claim 1, Chen is silent as to a pitch of the plurality of fins is in a range from 1 mm to 5 mm.
An artisan would recognize that function of the fin to increase the surface area of the TIM/Lid interface thus lowering the temperature drop through the TIM (heat transfer = conductivity of TIM x Area of TIM x Delta T of TIM / thickness of the TIM).
Accordingly, configuration of the device of claim 1 with a pitch of the plurality of fins is in a range from 1 mm to 5 mm is merely a design choice to realize a particular surface area for the fin and to decrease the temperature drop through the TIM for a given heat transfer requirement, see MPEP 2144.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen and U.S. 2021/0249326 (Uppal).
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Regarding claim 10 which depends upon claim 1, Chen teaches various embodiments which include semicircular recess in the die that mates with the fin shape, e.g. at Figure 1G while at Figure 2 Chen teaches the fins have a rectangular shape in cross section. Chen teaches the end portions of the plurality of fins are embedded in the TIM layer.
Chen does not explicitly teach the plurality of fins comprises a square cylindrical
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shape and a square-shaped end portion.
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Uppal is directed to semiconductor packages which have fins embedded in TIM material, see Figure 9.
At Figure 7-9, Uppal teaches various fin configurations including a plurality of fins comprises a square cylindrical shape and a square-shaped end portion, see Figure 7, are useful fin shapes.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein the plurality of fins comprises a square cylindrical shape and a square-shaped end portion, as taught by Uppal, because Uppal teaches this is a suitable configuration for fins that penetrate a TIM layer in a semiconductor package and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 20 and referring to the discussion at claim 1, Chen discloses a package structure, comprising:
a package substrate, 109 [0023];
an interposer module, 106 [0024] / 103 [0039], including a plurality of semiconductor dies, 103 0039], on the package substrate, as shown;
a metallic thermal interface material (TIM) layer, 102 [0029], on the interposer module, as shown; and
a package lid, 101 [0029], on the metallic TIM layer, as shown, comprising:
a package lid foot portion, 101b [0028], attached to the package substrate, as shown;
a package lid plate portion, 101c [0028], over the interposer module, as shown, and connected to the package lid foot portion, as shown; and
a plurality of fins, 101a [0029], extending from the package lid plate portion, as shown, into the metallic TIM layer, 102 as shown, over the plurality of semiconductor dies, 103, of the interposer module, as shown,
wherein the plurality of fins comprises an arc-shaped end portion of the plurality of fins is embedded in the metallic TIM layer, as shown in Figure 1G.
Chen does not explicitly teach the plurality of fins comprises a circular cylindrical shape.
Uppal is directed to semiconductor packages which have fins embedded in TIM material, see Figure 9. At Figure 7-9, Uppal teaches various pin configurations including a plurality of fins comprises a circular cylindrical shape as a useful fin shape.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 20 wherein the plurality of fins comprises a plurality of fins comprises a circular cylindrical shape, as taught by Uppal, because Uppal teaches this is a suitable configuration for fins that penetrate a TIM layer in a semiconductor package and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen and U.S. 2022/0367317 (Hua).
Regarding claim 11 which depends upon claim 1, Chen does not teach the interposer module comprises a backside metal (BSM) layer and the TIM layer is on the BSM layer.
Hua is directed to improvements in package and TIM reliability.
[0002] A thermal interface material is required to transfer the heat generated by the chip to the heat dissipation cover. The thermal conductivity of the thermal interface material determines whether the heat generated by CPU can be effectively dissipated. For high-end CPU, the indium sheet, a welding material based on pure indium, is commonly used for thermal interface material. Pure indium has a thermal conductivity of approximately 86 W/mk, which is the highest among welding materials. In order to weld the indium sheet with thermally conductive interface without any gaps, the design of both the back metal layer of the chip contacting with the indium sheet and the surface metal layer of the heat dissipation cover is crucially important.
[0003] The commonly used chip thermal interface material layer is developed by Intel, which includes an indium layer, and a heat dissipation cover and a back metal layer respectively located on both sides of the indium layer. The back metal layer is bonded to the chip with the side facing away the indium layer. Both of the connections, between the heat dissipation cover and the indium layer and between the back metal layer and the indium layer, adopt welding method and use an Au layer as a wetting layer. The Au layer as a wetting layer and the indium layer are bonded by welding, forming a compound layer between the two metal layers. The compound layer is the AuIn2 compound layer. The defect of this solution is that the AuIn2 compound layer formed at the welding position is unstable when Au is used as the wetting layer. The AuIn2 compound layer, at the interface between heat dissipation cover and indium layer, often suffers fracture during the process of reliability test of the units obtained by packaging with same, causing the chips to insufficient heat dissipation and failure eventually.
[0004] Therefore, it still has great importance to improve the interface metal layer of both heat dissipation cover and indium layer in the chip thermal interface material layer, thus improving the reliability of the units obtained by packaging with same.
At [0005], Hua teaches
[0005] An object of the present disclosure is to provide a thermal interface material layer and use thereof. The thermal interface material layer includes an indium layer and a heat dissipation cover located on one side of the indium layer, wherein the heat dissipation cover includes a nickel layer on its surface and the nickel layer is bonded to the indium layer. In the thermal interface material layer provided by the present disclosure, the nickel layer on the surface of the heat dissipation cover is bonded to the indium layer, which forms a Ni—In compound layer with high structural stability, thereby solving the problem of fracture readily appearing in AuIn.sub.2 compound layer which is formed by welding Au as a wetting layer adopted in the conventional thermal interface material to indium layer, and improving the reliability of components assembled by same.
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Referring to annotated Figures 1-3 and 5, Hua teaches teach die, 3 [0050] which is part of Chen’s interposer module, 105-103 [0024-29], comprises a backside metal (BSM) layer, Ni-V 10 [0053], and the TIM layer, Indium 7 [0052], is on the BSM layer.
Hua teaches at [0027];
[0027] The back metal layer generally refers to the metal layer on the back side of the semiconductor, and the back metal generally includes NiV alloy layer and Au layer, while the back metal layer of the present disclosure may adopt a two-layer structure of NiV alloy layer and Au layer (NiV alloy layer+Au layer), or NiV alloy layer only. When NiV alloy layer+Au layer is used, the AuIn.sub.2 compound layer will be formed by welding Au layer and indium layer, and a Ni—In compound layer will be formed between AuIn.sub.2 compound layer and NiV alloy layer; however, if only NiV alloy layer is used, just Ni—In compound layer will be formed. Before metal layer and the indium layer are welded, the Au layer used for the back metal layer has a thickness of 0 μm to 2 μm.
Hua teaches at [0061];
[0061] According to the reliability test hereinabove, it is found that the Ni—In compound layer has better structural stability and is not easy to fracture, which is formed by welding the indium layer with the Ni layer on the surface of the heat dissipation cover of the thermal interface material layer described in Examples 1-2 of the present disclosure, while the AuIn.sub.2 compound layer, which is formed by welding the indium layer with the Au layer employed as a wetting layer of the heat dissipation cover of the thermal interface material layer in Comparative Example 1, is structurally unstable and easy to fracture, thereby causing relatively poor reliability to the central processing unit obtained by packaging with same.
Hua teaches at [0034-35];
[0034] When the Au layer is not used as the wetting layer in the back metal layer, the nickel-vanadium alloy layer of the back metal layer has a thickness of 4 μm to 10 μm, such as 5 μm, 6 μm, 7 μm, 8 μm or 9 μm. The nickel-vanadium alloy layer of the back metal layer is subjected to surface chemical treatment, giving its surface a lower surface tension compared with that of the molten indium layer, creating a state of more easily being wettable; then the indium layer and the nickel-vanadium alloy layer are bonded by welding, and a Ni—In compound layer at the junction of the back metal layer and the indium layer, thereby achieving the object of improving the reliability of the thermal interface material layer.
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[0035] When the Au layer is used as the wetting layer, the Au layer has a thickness of 0.2 μm to 2 μm. The Au layer and the indium layer are bonded by welding, and an AuIn.sub.2 compound layer is formed between the back metal layer and the indium layer. Meanwhile, due to the thin thickness of the Au wetting layer, a Ni—In compound layer will be formed between the AuIn.sub.2 compound layer and the nickel-vanadium alloy layer during the welding process.
Hua teaches that the use of the Ni-V back layer that is subject to a surface chemical treatment enables the omission of Au as a wetting agent for the Indium TIM and consequently the welding process to form the TIM does not form a AuIn2 material which is unstable and results in fracture(s) of the TIM.
An artisan would find it desirable to implement a high reliability TIM material in the assembly process to improve the reliability of the reliability of the semiconductor device.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein the interposer module comprises a backside metal (BSM) layer and the TIM layer is on the BSM layer to implement a TIM material to improve package reliability.
Regarding claim 12 which depends upon claim 11, Hua teaches the package lid further comprises a plating layer, 8 electroplated Ni [0052], on a bottom surface of the package lid plate portion and the plating layer contacts an upper surface of the TIM layer and when implemented on Chen’s device results in the package lid further comprising a plating layer on the plurality of fins and on a bottom surface of the package lid plate portion and the plating layer contacts an upper surface of the TIM layer
Regarding claim 13 which depends upon claim 12, Hua teaches a first intermetallic compound (IMC) layer, 11 Ni-In [0053], between the TIM layer and the BSM layer; and a second IMC layer, 11 Ni-In [0053], between the package lid plate portion and the TIM layer.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Hua and Deppisch, Carl, et al. “The material optimization and reliability characterization of an indium-solder thermal interface material for CPU packaging.” JOM, vol. 58, no. 6, June 2006, pp. 67–74, https://doi.org/10.1007/s11837-006-0186-6. (Deppisch).
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Regarding claim 14 which depends upon claim 13, Hua teaches the first IMC layer and the second IMC layer have a thickness greater than zero microns. Hua teaches inter alia the IMC may be Ni-In or InAu2.
Deppisch is directed to indium TIM characterization. At Figure 15, Deppisch teaches various intermetallic thicknesses pre and post assembly, i.e. reflow. Deppisch reports a thickness of the Ni-In IMC is 0.5-0.9 microns. Further that the AuIn2 IMC ranges from 2.5 to 2 microns and the In-Ni-Au IMC range from 0.1 to 0.5 microns.
Examiner understands that Deppisch teaches that IMC thicknesses for a solder TIM may range from 0.1 to 2.5 microns.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 13 wherein the first IMC layer and the second IMC layer have a thickness in a range from 0.5 μm to 2.0 μm because Deppisch teaches that Hua’s IMC have these properties.
Allowable Subject Matter
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 15, the prior art fails to disclose the method of claim 15 comprising forming a package lid comprising a package lid foot portion a package lid plate portion connected to the package lid foot portion, and a plurality of fins extending from the package lid foot portion.
Claim 16-19 depend directly or indirectly on claim 15 and are allowable on that basis.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893