DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 08 Apr 2026 for application number 18/471,316. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims.
Claims 1-2, 4, 7-17, 21-24, and 26-27 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 1-2, 4, 7-9, 21-24, and 26-27 allowed.
The following is an examiner’s statement of reasons for allowance:
The Examiner has carefully considered independent claims 1 and 24. The prior art of record, alone or in combination, does not teach or fairly suggest the following limitations in claims 1 and 24:
Claim 1:
“forming an interconnect structure over the semiconductor substrate and electrically connected to the first transistors,
wherein the step of forming the interconnect structure comprising forming stacked interlayer dielectric layers, interconnect wirings, and second transistors embedded in the stacked interlayer dielectric layers; and
forming memory devices embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors,
wherein a layer of the memory devices and a layer of the second transistors are vertically stacked, wherein the interconnect wirings comprise through vias, and through vias are respectively disposed next to at least two opposite sides of each of the memory devices and penetrate through two vertical adjacent stacked interlayer dielectric layers to respectively electric connect to a corresponding one of the second transistors,
wherein a plurality of wiring portions is formed and connected between the through vias and the second transistors,
wherein the interconnect wirings further comprise a first vias and a second vias respectively connected to an upper surface and a lower surface of each of the memory devices, and the first vias and the second vias are electronically and horizontally connected with the through vias through the plurality of wiring portions”
Claim 24:
“forming stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers; and
forming a memory cell array embedded in the stacked interlayer dielectric layers,
wherein the step of forming the memory cell array comprises forming a driving circuit and memory devices,
wherein the step of forming the driving circuit comprises forming thin film transistors embedded in the stacked interlayer dielectric layers, and the thin film transistors comprise bottom gate thin film transistors having respective gate insulating patterns,
wherein the memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the thin film transistors through the interconnect wirings,
wherein the driving circuit is located at a first level height, and the memory devices are located at a second level height above the first level height, wherein the interconnect wirings comprise a plurality of first through vias and a plurality of second through vias, at least two of the plurality of first through vias are respectively disposed next to at least two opposite sides of each of the memory devices, located at the second level height, and respectively extend toward the first level height to electrically connect to a corresponding one of the thin film transistors respectively, and the plurality of second through vias, located above the second level height, respectively extend toward the second level height to connect to a corresponding one of the plurality of first through vias,
wherein both the plurality of first through vias and the plurality of second through vias are disposed entirely above upper surfaces of the thin film transistors”
These limitations, in specific combinations as recited in independent claims 1 and 24, define the patentability of the claims.
The dependent claims are allowed based on the same rationale.
Response to Arguments
In response to Applicant’s arguments regarding the 103 rejection of claim 1, the arguments are moot, as claim 1 is allowed.
In response to Applicant’s arguments regarding the 103 rejection of claim 10, Applicant contends that the prior does not teach, “wherein a plurality of wiring portions is formed and connected between the first through vias and the second through vias”; Examiner respectfully disagrees. Kato teaches wherein a plurality of wiring portions [Kato, e.g. wiring 1730 and 1731; Fig. 29A-B, para 0412] is formed and connected between the first through vias [Kato, e.g. conductors 1712 and 1713; Fig. 29A-B, para 0413] and the second through vias [Kato, e.g. conductors 1710 and 1771; Fig. 29A-B, para 0411]. It would have been obvious to one of ordinary skill in the art to combine the teachings of Kato and Muller to produce wirings connecting vias, to yield predictable results using known methods. In response to applicant's argument that the Examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Dependent claims 11-17 are rejected for these reasons, and for reasons as expressed in the Rejection below.
In response to Applicant’s arguments regarding the 103 rejection of claim 24, the arguments are moot, as claim 24 is allowed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato (US 2016/0336055 A1) in view of Muller et al. [hereinafter as Muller] (US 10,438,645 B2).
In reference to claim 10, Kato teaches A fabrication method of a semiconductor chip, comprising:
providing a semiconductor substrate comprising a logic circuit [Kato Figs. 28A-B, 1700];
forming an interconnect structure [Kato Figs. 28A-B, such as 1730, 1712, 1702, 1703, 1714, 1717 and/or TrB, and TrC] on the semiconductor substrate and electrically connected to the logic circuit [Kato Figs. 28A-B, 1717],
wherein the step of forming the interconnect structure comprising forming stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers [Kato Figs. 28A-B, all the dielectric layers between 1710 and 1737]; and
forming a memory cell array embedded in the stacked interlayer dielectric layers [Kato Fig. 1, LYR2];
wherein a plurality of wiring portions [Kato, e.g. wiring 1730 and 1731; Fig. 29A-B, para 0412] is formed and connected between the first through vias [Kato, e.g. conductors 1712 and 1713; Fig. 29A-B, para 0413] and the second through vias [Kato, e.g. conductors 1710 and 1771; Fig. 29A-B, para 0411].
However, Kato does not explicitly teach:
wherein the step of forming the memory cell array comprises forming driving transistors and memory devices, and the memory devices are electrically connected to the driving transistors through the interconnect wirings,
wherein the driving transistors are located at a first level height, and the memory devices are located at a second level height above the first level height,
wherein the interconnect wirings comprise a plurality of first through vias and a plurality of second through vias, at least two of the plurality of first through vias are respectively disposed next to at least two opposite sides of each of the memory devices, located at the second level height, and respectively extend toward the first level height to electrically connect to a corresponding one of the driving transistors respectively, and the plurality of second through vias, located above the second level height, respectively extend toward the second level height to connect to a corresponding one of the plurality of first through vias.
Muller teaches:
wherein the step of forming the memory cell array comprises forming driving transistors [Muller Fig. 6A, 122] and memory devices [Muller Fig. 6A, 104], and the memory devices are electrically connected to the driving transistors through the interconnect wirings [Muller Fig. 6A, 104 connected to 122 via 262d/s],
wherein the driving transistors are located at a first level height, and the memory devices are located at a second level height above the first level height [Muller Fig. 6A],
wherein the interconnect wirings comprise a plurality of first through vias [Muller Fig. 6A, portion of 262d/s in layer 260a] and a plurality of second through vias [Muller Fig. 6A, portion of 262d/s in layer 260c], at least two of the plurality of first through vias are respectively disposed next to at least two opposite sides of each of the memory devices [Muller Fig. 6A, 262d/s are on opposite sides of 122], located at the second level height [Muller Fig. 6A, 262d/s], and respectively extend toward the first level height to electrically connect to a corresponding one of the driving transistors respectively [Muller Fig. 6A, 262d/s in each layers 260a/c connect 122 to 104], and the plurality of second through vias, located above the second level height, respectively extend toward the second level height to connect to a corresponding one of the plurality of first through vias [Muller Fig. 6A, portion of 262d/s in layers 260a/c forming a connected 262d/s pair of thru vias].
Kato and Muller disclose memory storage devices and systems. Muller disclose a memory system using FeFET memory cell that can be integrated in the front end processing thus providing manufacturing flexibility. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to apply the FeFET integration process of Muller to the memory storage devices taught by Kato for the purpose of providing manufacturing flexibility [see e.g., Muller col. 4, ll. 53-66 through col. 5, ll. 1-10].
In reference to claim 11, Kato and Muller teach the invention of claim 10.
Kato and Muller teach The fabrication method as claimed in claim 10, the step of forming the stacked interlayer dielectric layers comprises forming damascene openings therein with different aspect ratios [e.g. Muller discloses well known dual-damascene process that would include forming openings as needed].
In reference to claim 12, Kato and Muller teach the invention of claim 10.
Kato and Muller teach The fabrication method as claimed in claim 10, wherein the step of forming the memory cell array further comprises forming word lines and bit lines,
wherein the memory devices are electrically connected to the word lines, and sources of the driving transistors are electrically connected to the bit lines [both Kato and Muller disclose memory arrays which are known to have word lines and bit lines].
In reference to claim 13, Kato and Muller teach the invention of claim 12.
Kato and Muller teach The fabrication method as claimed in claim 12, wherein the driving transistors, located at the first level height, are formed in a first interlayer dielectric layer among the stacked interlayer dielectric layers, and the memory devices of the memory cell array, located at the second level height, are embedded in a second interlayer dielectric layer among the stacked interlayer dielectric layers [Muller Fig. 6A: 102 transistors in first level and 104 memory cell in second level].
In reference to claim 14, Kato and Muller teach the invention of claim 13.
Kato and Muller teach The fabrication method as claimed in claim 13 further comprising:
forming a dielectric layer covering the second interlayer dielectric layer; and
forming a buffer layer covering the dielectric layer, wherein the interconnect structure and the memory cell array are disposed on the buffer layer [Muller Fig. 6A: 260c].
In reference to claim 15, Kato and Muller teach the invention of claim 14.
Kato and Muller teach The fabrication method as claimed in claim 14, wherein the step of forming driving transistors comprises forming thin film transistors on the buffer layer [Kato Figs. 28A-B, TrC].
In reference to claim 16, Kato and Muller teach the invention of claim 10.
Kato and Muller teach The fabrication method as claimed in claim 10, wherein the driving transistors comprise thin film transistors having respective gate insulating patterns [Kato Figs. 28A-B, TrC].
In reference to claim 17, Kato and Muller teach the invention of claim 13.
Kato and Muller teach The fabrication method as claimed in claim 13, wherein
each of the memory devices comprises a first electrode, a second electrode and a storage layer between the first electrode and second electrode,
the second interlayer dielectric comprises a first dielectric sub-layer and a second dielectric sub-layer covering the first dielectric sub-layer,
the interconnect wirings comprise first vias and second vias, the first vias [Kato Figs. 28A-B: 1718 and/or 1736] are embedded in the first dielectric sub-layer [Kato Figs. 28A-B: L9 and/or L10] and electrically connected to the first electrode [Kato Figs. 28A-B: 1751] of the memory devices, the memory devices and the second vias [Kato Figs. 28A-B: 1719 and/or 1737] are embedded in the second dielectric sub-layer [Kato Figs. 28A-B: L11 and/or L12], and the second vias are electrically connected to the second electrode [Kato Figs. 28A-B: 1752] of the memory devices.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW CHUNG whose telephone number is (571)272-5237. The examiner can normally be reached M-F 9-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW CHUNG/
Examiner, Art Unit 2898
Prosecution Insights