DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 30 Oct 2025 for application number 18/471,316. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims.
Claims 1-2, 4, 7-17, 21-24, and 26-27 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The double patenting rejections of claims 1-17 and 21-23 have been removed in light of amendments.
Regarding claim 1, Applicant contends that the prior does not teach, “wherein a plurality of wiring portions is formed and connected between the through vias and the second transistors”; Examiner respectfully disagrees. Kato teaches wherein a plurality of wiring portions [Kato, e.g. wiring 1730 and 1731; Fig. 29A-B, para 0412] is formed and connected between the through vias [Kato, e.g. conductors 1712 and 1713; Fig. 29A-B, para 0413] and the second transistors [Kato, transistors TrA; Fig. 29A-B, para 0411].
Regarding claim 10, Applicant contends that the prior does not teach, “wherein a plurality of wiring portions is formed and connected between the first through vias and the second through vias”; Examiner respectfully disagrees. Kato teaches wherein a plurality of wiring portions [Kato, e.g. wiring 1730 and 1731; Fig. 29A-B, para 0412] is formed and connected between the first through vias [Kato, e.g. conductors 1712 and 1713; Fig. 29A-B, para 0413] and the second through vias [Kato, e.g. conductors 1710 and 1771; Fig. 29A-B, para 0411].
Regarding claim 24, Applicant contends that the prior does not teach, “…wherein the interconnect wirings…first through vias”; Examiner respectfully disagrees. Muller teaches:
wherein the step of forming the memory cell array comprises forming a driving circuit [Muller Fig. 6A, 122] and memory devices [Muller Fig. 6A, 104],
wherein the memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the thin film transistors through the interconnect wirings [Muller Fig. 6A, 104 connected to 122 via 262d/s],
wherein the interconnect wirings comprise a plurality of first through vias [Muller Fig. 6A, portion of 262d/s in layer 260a] and a plurality of second through vias [Muller Fig. 6A, portion of 262d/s in layer 260c], at least two of the plurality of first through vias are respectively disposed next to at least two opposite sides of each of the memory devices [Muller Fig. 6A, 262d/s are on opposite sides of 122], located at the second level height [Muller Fig. 6A, 262d/s], and respectively extend toward the first level height to electrically connect to a corresponding one of the thin film transistors respectively [Muller Fig. 6A, 262d/s in each layers 260a/c connect 122 to 104], and the plurality of second through vias, located above the second level height, respectively extend toward the second level height to connect to a corresponding one of the plurality of first through vias [Muller Fig. 6A, portion of 262d/s in layers 260a/c forming a connected 262d/s pair of thru vias].
Regarding new claim 27, see the Rejection of claim 27 below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4, 7-17, 21-24, and 26-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato (US 2016/0336055 A1) in view of Muller et al. [hereinafter as Muller] (US 10,438,645 B2).
In reference to claim 1, Kato teaches A fabrication method of a semiconductor chip, comprising:
providing a semiconductor substrate [Kato Figs. 28A-B, 1700];
forming first transistors over the semiconductor substrate [Kato Figs. 28A-B, TrC];
forming an interconnect structure [Kato Figs. 28A-B, such as 1730, 1712, 1702, 1703, 1714, 1717 and/or TrB, and TrC] over the semiconductor substrate and electrically connected to the first transistors [Kato Figs. 28A-B, such as 1730, 1712, 1702, 1703, 1714, 1717 and/or TrB, and TrC],
wherein the step of forming the interconnect structure comprising forming stacked interlayer dielectric layers [Kato Figs. 28A-B, all the dielectric layers between 1710 and 1737], interconnect wirings [Kato Figs. 28A-B 1730, 1734], and second transistors embedded in the stacked interlayer dielectric layers;
wherein a plurality of wiring portions [Kato, e.g. wiring 1730 and 1731; Fig. 29A-B, para 0412] is formed and connected between the through vias [Kato, e.g. conductors 1712 and 1713; Fig. 29A-B, para 0413] and the second transistors [Kato, transistors TrA; Fig. 29A-B, para 0411].
Kato does not explicitly teach:
forming memory devices embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors,
wherein a layer of the memory devices and a layer of the second transistors are vertically stacked, wherein the interconnect wirings comprise through vias, and through vias are respectively disposed next to at least two opposite sides of each of the memory devices and penetrate through two vertical adjacent stacked interlayer dielectric layers to respectively electric connect to a corresponding one of the second transistors.
Muller teaches:
forming memory devices embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors,
wherein a layer of the memory devices [Muller, Fig. 6A, the layer containing memory structure 104] and a layer of the second transistors [Muller, Fig. 6A, 102] are vertically stacked [Muller Fig. 6A], wherein the interconnect wirings comprise through vias [Muller Fig. 6A, 262d/s], and through vias are respectively disposed next to at least two opposite sides of each of the memory devices and penetrate through two vertical adjacent stacked interlayer dielectric layers to respectively electric connect to a corresponding one of the second transistors [Muller Fig. 6A, 262d/s connecting to S/D of transistor 102].
Kato and Muller disclose memory storage devices and systems. Muller disclose a memory system using FeFET memory cell that can be integrated in the front end processing thus providing manufacturing flexibility. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to apply the FeFET integration process of Muller to the memory storage devices taught by Kato for the purpose of providing manufacturing flexibility [see e.g., Muller col. 4, ll. 53-66 through col. 5, ll. 1-10].
In reference to claim 2, Kato and Muller teach the invention of claim 1.
Regarding the limitations: The fabrication method as claimed in claim 1, wherein the step of forming memory devices comprises
forming a first conductive material layer, a ferroelectric layer, and a second conducive material layer sequentially over the stacked interlayer dielectric layer; and patterning the first conductive material layer, the ferroelectric layer, and the second conducive material, in addition to what have been discussed above, it is further noted that: it is well known in the art that the capacitor dielectric layer can be commonly and desirably formed of a ferroelectric material, so as to form a capacitor with the desired high-k dielectric property therein; and it has been held that:
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
In reference to claim 4, Kato and Muller teach the invention of claim 1.
Kato and Muller teach The fabrication method as claimed in claim 1, wherein the second transistors are embedded in a first interlayer dielectric layer among the stacked interlayer dielectric layers, the memory devices are embedded in a second interlayer dielectric layer among the stacked interlayer dielectric layers, and the second interlayer dielectric layer covers the first interlayer dielectric layer [Muller, Fig. 6A, 102 and 104 respectively].
In reference to claim 7, Kato and Muller teach the invention of claim 1.
Kato and Muller teach The fabrication method as claimed in claim 1, wherein the memory devices are formed over the stacked interlayer dielectric layers through manufacturing process of back end of line (BEOL) [Muller, col. “Alternatively, the memory structure 104 may be formed…in the BEoL processing.”].
In reference to claim 8, Kato and Muller teach the invention of claim 4.
Kato and Muller teach The fabrication method as claimed in claim 4, wherein the second interlayer dielectric comprises a first dielectric sub-layer and a second dielectric sub-layer covering the first dielectric sub-layer [Muller, Fig. 6A, 260b, 260c].
In reference to claim 9, Kato and Muller teach the invention of claim 8.
Kato and Muller teach The fabrication method as claimed in claim 8, wherein the step of forming the interconnect wirings comprises forming first vias and second vias, wherein the first vias are embedded in the first dielectric sub-layer and electrically connected to first electrodes of the memory devices, the memory devices and the second vias are embedded in the second dielectric sub-layer, and the second vias are electrically connected to second electrodes of the memory devices [Muller, Fig. 6A, 262b, 262c].
In reference to claim 10, Kato teaches A fabrication method of a semiconductor chip, comprising:
providing a semiconductor substrate comprising a logic circuit [Kato Figs. 28A-B, 1700];
forming an interconnect structure [Kato Figs. 28A-B, such as 1730, 1712, 1702, 1703, 1714, 1717 and/or TrB, and TrC] on the semiconductor substrate and electrically connected to the logic circuit [Kato Figs. 28A-B, 1717],
wherein the step of forming the interconnect structure comprising forming stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers [Kato Figs. 28A-B, all the dielectric layers between 1710 and 1737]; and
forming a memory cell array embedded in the stacked interlayer dielectric layers [Kato Fig. 1, LYR2];
wherein a plurality of wiring portions [Kato, e.g. wiring 1730 and 1731; Fig. 29A-B, para 0412] is formed and connected between the first through vias [Kato, e.g. conductors 1712 and 1713; Fig. 29A-B, para 0413] and the second through vias [Kato, e.g. conductors 1710 and 1771; Fig. 29A-B, para 0411].
However, Kato does not explicitly teach:
wherein the step of forming the memory cell array comprises forming driving transistors and memory devices, and the memory devices are electrically connected to the driving transistors through the interconnect wirings,
wherein the driving transistors are located at a first level height, and the memory devices are located at a second level height above the first level height,
wherein the interconnect wirings comprise a plurality of first through vias and a plurality of second through vias, at least two of the plurality of first through vias are respectively disposed next to at least two opposite sides of each of the memory devices, located at the second level height, and respectively extend toward the first level height to electrically connect to a corresponding one of the driving transistors respectively, and the plurality of second through vias, located above the second level height, respectively extend toward the second level height to connect to a corresponding one of the plurality of first through vias.
Muller teaches:
wherein the step of forming the memory cell array comprises forming driving transistors [Muller Fig. 6A, 122] and memory devices [Muller Fig. 6A, 104], and the memory devices are electrically connected to the driving transistors through the interconnect wirings [Muller Fig. 6A, 104 connected to 122 via 262d/s],
wherein the driving transistors are located at a first level height, and the memory devices are located at a second level height above the first level height [Muller Fig. 6A],
wherein the interconnect wirings comprise a plurality of first through vias [Muller Fig. 6A, portion of 262d/s in layer 260a] and a plurality of second through vias [Muller Fig. 6A, portion of 262d/s in layer 260c], at least two of the plurality of first through vias are respectively disposed next to at least two opposite sides of each of the memory devices [Muller Fig. 6A, 262d/s are on opposite sides of 122], located at the second level height [Muller Fig. 6A, 262d/s], and respectively extend toward the first level height to electrically connect to a corresponding one of the driving transistors respectively [Muller Fig. 6A, 262d/s in each layers 260a/c connect 122 to 104], and the plurality of second through vias, located above the second level height, respectively extend toward the second level height to connect to a corresponding one of the plurality of first through vias [Muller Fig. 6A, portion of 262d/s in layers 260a/c forming a connected 262d/s pair of thru vias].
Kato and Muller disclose memory storage devices and systems. Muller disclose a memory system using FeFET memory cell that can be integrated in the front end processing thus providing manufacturing flexibility. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to apply the FeFET integration process of Muller to the memory storage devices taught by Kato for the purpose of providing manufacturing flexibility [see e.g., Muller col. 4, ll. 53-66 through col. 5, ll. 1-10].
wherein a plurality of wiring portions is formed and connected between the first through vias and the second through vias.
In reference to claim 11, Kato and Muller teach the invention of claim 10.
Kato and Muller teach The fabrication method as claimed in claim 10, the step of forming the stacked interlayer dielectric layers comprises forming damascene openings therein with different aspect ratios [e.g. Muller discloses well known dual-damascene process that would include forming openings as needed].
In reference to claim 12, Kato and Muller teach the invention of claim 10.
Kato and Muller teach The fabrication method as claimed in claim 10, wherein the step of forming the memory cell array further comprises forming word lines and bit lines,
wherein the memory devices are electrically connected to the word lines, and sources of the driving transistors are electrically connected to the bit lines [both Kato and Muller disclose memory arrays which are known to have word lines and bit lines].
In reference to claim 13, Kato and Muller teach the invention of claim 12.
Kato and Muller teach The fabrication method as claimed in claim 12, wherein the driving transistors, located at the first level height, are formed in a first interlayer dielectric layer among the stacked interlayer dielectric layers, and the memory devices of the memory cell array, located at the second level height, are embedded in a second interlayer dielectric layer among the stacked interlayer dielectric layers [Muller Fig. 6A: 102 transistors in first level and 104 memory cell in second level].
In reference to claim 14, Kato and Muller teach the invention of claim 13.
Kato and Muller teach The fabrication method as claimed in claim 13 further comprising:
forming a dielectric layer covering the second interlayer dielectric layer; and
forming a buffer layer covering the dielectric layer, wherein the interconnect structure and the memory cell array are disposed on the buffer layer [Muller Fig. 6A: 260c].
In reference to claim 15, Kato and Muller teach the invention of claim 14.
Kato and Muller teach The fabrication method as claimed in claim 14, wherein the step of forming driving transistors comprises forming thin film transistors on the buffer layer [Kato Figs. 28A-B, TrC].
In reference to claim 16, Kato and Muller teach the invention of claim 10.
Kato and Muller teach The fabrication method as claimed in claim 10, wherein the driving transistors comprise thin film transistors having respective gate insulating patterns [Kato Figs. 28A-B, TrC].
In reference to claim 17, Kato and Muller teach the invention of claim 13.
Kato and Muller teach The fabrication method as claimed in claim 13, wherein
each of the memory devices comprises a first electrode, a second electrode and a storage layer between the first electrode and second electrode,
the second interlayer dielectric comprises a first dielectric sub-layer and a second dielectric sub-layer covering the first dielectric sub-layer,
the interconnect wirings comprise first vias and second vias, the first vias [Kato Figs. 28A-B: 1718 and/or 1736] are embedded in the first dielectric sub-layer [Kato Figs. 28A-B: L9 and/or L10] and electrically connected to the first electrode [Kato Figs. 28A-B: 1751] of the memory devices, the memory devices and the second vias [Kato Figs. 28A-B: 1719 and/or 1737] are embedded in the second dielectric sub-layer [Kato Figs. 28A-B: L11 and/or L12], and the second vias are electrically connected to the second electrode [Kato Figs. 28A-B: 1752] of the memory devices.
In reference to claim 21, Kato and Muller teach the invention of claim 4.
Kato and Muller teach The fabrication method as claimed in claim 4, further comprising forming a dielectric layer covering the second interlayer dielectric layer [Muller, Fig. 6A, 260c].
In reference to claim 22, Kato and Muller teach the invention of claim 21.
Kato and Muller teach The fabrication method as claimed in claim 21, further comprising forming a buffer layer covering the dielectric layer, wherein the interconnect structure and the second transistors are formed on the buffer layer [Muller, Fig. 6A, 240].
In reference to claim 23, Kato and Muller teach the invention of claim 22.
Kato and Muller teach The fabrication method as claimed in claim 22, wherein the step of forming the second transistors comprises forming thin film transistors on the buffer layer [Muller, Fig. 6A, 122].
In reference to claim 24, Kato teaches A fabrication method of a semiconductor chip, comprising:
providing a semiconductor substrate comprising fin-type field-effect transistors [e.g. Kato Figs. 28A-B, TrC in 1700];
forming an interconnect structure on the semiconductor substrate and electrically connected to the fin-type field-effect transistors [Kato Figs. 28A-B, such as 1730, 1712, 1702, 1703, 1714, 1717 and/or TrB, and TrC],
wherein the step of forming the interconnect structure comprises forming stacked interlayer dielectric layers [Kato Figs. 28A-B, all the dielectric layers between 1710 and 1737] and interconnect wirings embedded in the stacked interlayer dielectric layers [Kato Figs. 28A-B 1730, 1734]; and
forming a memory cell array embedded in the stacked interlayer dielectric layers [Kato Fig. 1, LYR2],
wherein the step of forming the driving circuit comprises forming thin film transistors embedded in the stacked interlayer dielectric layers, and the thin film transistors comprise bottom gate thin film transistors having respective gate insulating patterns [Kato Figs. 28A-B, TrC],
wherein the driving circuit is located at a first level height [Kato Figs. 28A-B: L1], and the memory devices are located at a second level height above the first level height [Kato Figs. 28A-B: MCC1].
However, Kato does not explicitly teach:
wherein the step of forming the memory cell array comprises forming a driving circuit [Muller Fig. 6A, 122] and memory devices [Muller Fig. 6A, 104],
wherein the memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the thin film transistors through the interconnect wirings [Muller Fig. 6A, 104 connected to 122 via 262d/s],
wherein the interconnect wirings comprise a plurality of first through vias and a plurality of second through vias, at least two of the plurality of first through vias are respectively disposed next to at least two opposite sides of each of the memory devices, located at the second level height, and respectively extend toward the first level height to electrically connect to a corresponding one of the thin film transistors respectively, and the plurality of second through vias, located above the second level height, respectively extend toward the second level height to connect to a corresponding one of the plurality of first through vias.
Muller teaches:
wherein the step of forming the memory cell array comprises forming a driving circuit [Muller Fig. 6A, 122] and memory devices [Muller Fig. 6A, 104],
wherein the memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the thin film transistors through the interconnect wirings [Muller Fig. 6A, 104 connected to 122 via 262d/s],
wherein the interconnect wirings comprise a plurality of first through vias [Muller Fig. 6A, portion of 262d/s in layer 260a] and a plurality of second through vias [Muller Fig. 6A, portion of 262d/s in layer 260c], at least two of the plurality of first through vias are respectively disposed next to at least two opposite sides of each of the memory devices [Muller Fig. 6A, 262d/s are on opposite sides of 122], located at the second level height [Muller Fig. 6A, 262d/s], and respectively extend toward the first level height to electrically connect to a corresponding one of the thin film transistors respectively [Muller Fig. 6A, 262d/s in each layers 260a/c connect 122 to 104], and the plurality of second through vias, located above the second level height, respectively extend toward the second level height to connect to a corresponding one of the plurality of first through vias [Muller Fig. 6A, portion of 262d/s in layers 260a/c forming a connected 262d/s pair of thru vias].
Kato and Muller disclose memory storage devices and systems. Muller disclose a memory system using FeFET memory cell that can be integrated in the front end processing thus providing manufacturing flexibility. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to apply the FeFET integration process of Muller to the memory storage devices taught by Kato for the purpose of providing manufacturing flexibility [see e.g., Muller col. 4, ll. 53-66 through col. 5, ll. 1-10].
In reference to claim 26, Kato and Muller teach the invention of claim 24.
Kato and Muller teach The fabrication method as claimed in claim 24, wherein the step of forming the driving circuit further comprises forming word lines, bit lines, and driving transistors having oxide semiconductor channel layers,
wherein the memory devices are electrically connected to the word lines, and sources of the driving transistors are electrically connected to the bit lines [both Kato and Muller disclose memory arrays which are known to have word lines and bit lines].
In reference to claim 27, Kato and Muller teach the invention of claim 1.
Kato and Muller teach The fabrication method as claimed in claim 1, wherein the interconnect wirings further comprise upper via portions [memory contact structure 262c of Muller; Fig. 6A, col. 14, line 65] and lower via portions [gate contact structure 262b of Muller; Fig. 6A, col. 15, line 10], and each of the upper via portion [262c of Muller] and each of the lower via portions [262b of Muller] respectively connected to an upper side and a lower side of each of the memory devices [memory structure 104 of Muller; Fig. 6A, col. 8, line 34],
wherein each of the lower via portions [262b of Muller] is connected between the lower side of each of the memory devices [104 of Muller] and the wiring portions [Kato, e.g. wiring 1730 and 1731].
It would have been obvious to one of ordinary skill in the art to combine the wiring portions of Kato and the via portions of Muller, as Kato clearly teaches vias and wiring portions connected together to electrically connect semiconductor components. One would have motivated to make this combination to provide efficient signaling and power routing.
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Nagai et al. (US-20190237471-A1) discloses wirings and vias connected to transistors [Fig. 5].
Tsukamoto (US-2020/0381034-A1) discloses wirings and vias connected to transistors [Fig. 5].
Ujita et al. (US-20160329890-A1) discloses wirings and vias connected to transistors [Fig. 4].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898