Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 5:
Claim 5 recites the phrase “…electrically connecting the multiple first dies to the primary RDL and/or the secondary RDL”, emphasis added, in line 3 of the claim. There is insufficient antecedent basis for “the secondary RDL” in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0242100 A1 Hou et al (herein “Hou”).
Regarding Claim 1, Hou discloses:
A semiconductor package (#10, see generally Figs. 1A showing semiconductor devices 200 and 300 and 2 showing completed semiconductor package including lower redistribution structure and circuit substrate 800. See also annotated Fig. 2 below), comprising:
a first integrated circuit (IC) structure (Fig. 1A, #200 and #300), comprising:
a first body (see annotated Fig. 2 below) having a first primary surface (see annotated Fig. 2 below) and a first secondary surface (see annotated Fig. 2 below), with the first primary surface being substantially perpendicular to the first secondary surface (see annotated Fig. 2 below); and
an interconnect structure (#600, [0028]), comprising:
a primary redistribution layer (RDL) (#620, [0028]-[0030]) over the first primary surface, with the primary RDL (#620) having a second secondary (see annotated Fig. 2 below) surface that is aligned with the first secondary surface of the first body, wherein the first secondary surface and the second secondary surface jointly form a secondary plane (see annotated Fig. 2 below),
wherein the primary RDL (#620) further comprises a first conductive element (also referenced as #620, individual conductive elements not explicitly labelled, see annotated Fig. 2 below, first conductive elements described in relation to redistribution conductive layer #620 in [0027]-[0030]. For example, [0028]: “…The redistribution conductive layers 620 may include a plurality of routing traces and redistribution vias.”) exposed through the second secondary surface of the primary RDL.
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Hou Fig. 2 – Annotated by Examiner
Regarding Claim 2, Hou discloses: The semiconductor package of claim 1,
Hou further discloses:
wherein the first conductive element (#620) comprises a conductive pad (see annotated Fig. 2 below) on a surface of the primary RDL (#600) substantially parallel to the first primary surface, a conductive via connecting adjacent layers of the primary RDL, a stacked via traversing the primary RDL, or a combination thereof ([0027]-[0030]).
Regarding Claim 3, Hou discloses: The semiconductor package of claim 2,
Hou further discloses:
wherein the first body further comprises at least a through-silicon via, a through-molding via, or an insulating element exposed through the first secondary surface (insulating element #400 exposed through first secondary surface).
Regarding Claim 4, Hou discloses: The semiconductor package of claim 1,
Hou further discloses:
wherein the first body comprises multiple first dies (#200, #300, Fig. 1A) placed in a same package layer, vertically stacked second dies (#300, specifically vertically stacked dies #310, Fig. 1A), the vertically stacked second dies placed side-by-side with other third dies (#200) in the same package layer, or a combination thereof, and wherein the first, second and third dies are of the same or different sizes (Fig. 1A).
Regarding Claim 5, Hou discloses: The semiconductor package of claim 4,
Hou further discloses:
wherein the first body comprises a plurality of conductive vias, pillars or plugs of same or different lengths, electrically connecting the multiple first dies to the primary RDL and/or the secondary RDL (Figs. 1D-1L, #520, [0028]: “…The through vias 520 may establish electrical connection between the semiconductor dies 200, 300 and the redistribution conductive layers 620 of the redistribution structure 600.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over in view of US 2021/0242100 A1 Hou et al in view of US 2020/0411481 A1 Yang et al (herein “Yang”).
Regarding Claim 6, Hou discloses: The semiconductor package of claim 1,
Hou does not explicitly disclose:
wherein the interconnect structure further comprises a secondary RDL over the secondary plane, wherein the secondary RDL is electrically connected to the first conductive element of the primary RDL, to conductive vias, pillars or plugs in the first body, or to a combination thereof.
However, in analogous art, Yang teaches:
See Fig. 23 and paragraphs [0041]-[0048].
wherein the interconnect structure further comprises a secondary RDL (#134/234) over the secondary plane (#122/222), wherein the secondary RDL is electrically connected to the first conductive element ([0042]: “…The RDL 134 electrically redistributes the edge pads 112 to the fan-out pattern of contact pads 140 on the second surface 142.”) of the primary RDL, to conductive vias, pillars or plugs in the first body, or to a combination thereof ([0047]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Yang to the device disclosed by Hou and include a secondary RDL layer on the sidewall of the die stacks. Doing so would form an external electrical redistribution connection for edge pads 112 like shown in Yang for the purposes of providing power or signal to individual dies in the die stack for 2.5 and 3D packaging.
Regarding Claim 8, Hou in view of Yang discloses: The semiconductor package of claim 6,
Hou in view of Yang does not explicitly disclose the particular arrangement of claim 8, specifically:
wherein the secondary RDL covers the secondary plane, with the secondary RDL comprising a first surface coincident with the secondary plane, and a second surface opposite to the first surface, wherein the first surface of the secondary RDL comprises a first flip-chip bonding layer corresponding to a second flip-chip bonding layer on the secondary plane.
However, the particular placement of a claim element is an obvious matter of design choice absent a showing that the particular arrangement would have modified the operation of the device, see MPEP 2144.04(VI)(C). In this case, nothing on the record indicates that the claimed arrangement would have a different mode of operation than the referenced semiconductor package structure. Rather, the arrangement is a design consideration to meet application specific requirements that may be made by the person of ordinary skill. Therefore, the claimed arrangement is a mere rearrangement of parts with respect to the prior art.
Regarding Claim 10, Hou in view of Yang discloses: The semiconductor package of claim 6,
Hou in view of Yang further discloses:
further comprising: a second IC structure (#300, [0015]: “multiple stacked dies”) stacked over the first primary surface (see annotated Fig. 2 above) of the first IC structure; and
a third IC structure (#300, [0015]) stacked over a second primary surface (see annotated Fig. 2 above) of the second IC structure (#300, [0015]),
Hou in view of Yang does not explicitly disclose the particular arrangement of claim 10, specifically:
wherein the secondary RDL extends over the secondary plane of the first IC structure, a secondary plane of the second IC structure, and a secondary plane of the third IC structure, and
wherein a conductive trace or wire in the secondary RDL electrically connects the first IC structure, the second IC structure and the third IC structure while bypassing a second body of the second IC structure.
However, the particular placement of a claim element is an obvious matter of design choice absent a showing that the particular arrangement would have modified the operation of the device, see MPEP 2144.04(VI)(C). In this case, nothing on the record indicates that the claimed arrangement would have a different mode of operation than the referenced semiconductor package structure. Rather, the arrangement is a design consideration to meet application specific requirements that may be made by the person of ordinary skill. Therefore, the claimed arrangement is a mere rearrangement of parts with respect to the prior art.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over in view of US 2021/0242100 A1 Hou et al in view of US 2018/0040587 A1 Tao et al (herein “Tao”).
Regarding Claim 11, Hou discloses: A semiconductor package assembly comprising: a first semiconductor package of claim 1 (#10, see annotated Fig. 2 and rejection of claim 1 above); and
a first carrier (#800) supporting the first semiconductor package (#10), with the first carrier (#800) comprising a second interconnect surface (#825) bonded to the first interconnect surface (#600, bonded through connective pads, see annotated Fig. 2 above, and connective terminals #700).
Hou does not explicitly disclose:
a secondary RDL over the secondary plane, with the secondary RDL electrically connected to the primary RDL,
wherein the secondary RDL comprises a first interconnect surface opposite to the first secondary surface of the first body; and
However, in analogous art, Tao teaches:
See Fig. 20 and paragraphs [0046]-[0053].
a secondary RDL (#902, also includes RDL signal pads #904) over the secondary plane (side surface), with the secondary RDL electrically connected to the primary RDL (#1200, [0052]),
wherein the secondary RDL (#902) comprises a first interconnect surface (outside surface of #902 with respect to stacked dies #106) opposite to the first secondary surface (side surface of stacked dies #106) of the first body (#2000); and
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Tao to the device disclosed by Hou and include a secondary RDL layer on the sidewall of the die stacks. Doing so would form an external electrical redistribution connection for edge signal pads 904 like shown in Tao for the purposes of providing power or signal to individual dies in the die stack for 2.5 and 3D packaging.
Regarding Claim 12, Hou in view of Tao discloses: The semiconductor package assembly of claim 11,
Hao further discloses:
wherein the first interconnect surface of the first IC structure comprises a first bond pad array (array of space where conductive bond pads, see annotated Fig. 2 above, are formed over first interconnect layer #600) for flip-chip assembly corresponding to a second bond pad array (array of space where conductive bond pads, see annotated Fig. 2 above, are formed over second interconnect layer #825) on the second interconnect surface (#825) of the first carrier (#800).
Regarding Claim 13, Hou in view of Tao discloses: The semiconductor package assembly of claim 12,
Hou in view of Tao does not explicitly disclose:
further comprising: a second semiconductor package of claim 1, wherein the primary RDL comprises a third interconnect surface opposite to the first primary surface of the first body, wherein the first carrier supports the second semiconductor package, with the second interconnect surface bonded to the third interconnect surface.
However, nothing on the record indicates that the duplicating the first semiconductor package structure produces a new or unexpected result, rather producing the expected result of having multiple semiconductor packages which would therefore comprise multiple die stacks, RDL layers, and corresponding bonding surfaces. Thus, a second semiconductor package structure is a mere duplication of parts. See MPEP 2144.04 VI.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider duplicating the semiconductor package structure to fit the needs/constraints of the device in order for the device to perform its intended function of routing electrical signals, controlling electrical signals… etc.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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