DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-6, 11, 13-17, 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Das et al US 2017/0162550.
Pertaining to claim 1, Das teaches a semiconductor device assembly comprising:
a first substrate 110 including:
a first dielectric layer (material in 110 surrounding conductive elements); and
a first patterned metal layer 114 disposed on a surface of the first dielectric layer;
a pre-molded semiconductor device module 160 (note “pre-molded” is broad and is being interpreted as an integrated circuit structure) having a first side disposed on and electrically coupled (element 302) with the first patterned metal layer 114; and
a second substrate 130 including:
a second dielectric layer(material in 130 surrounding conductive elements);
a second patterned metal layer 132 disposed on a first surface of the second dielectric layer 130, the second patterned metal layer being disposed on and electrically coupled with a second side of the pre-molded semiconductor device module 160 opposite the first side; and
a conductive via (See Figure 3 Marked up below) defined through the second dielectric layer, the conductive via electrically coupling a signal terminal (see [0051] where Das teaches that the electrically conductive elements can comprise signal, ground and/or power) of the pre-molded semiconductor device module with a third patterned metal layer disposed on a second surface of the second dielectric layer opposite the first surface. See Figure 3 marked up below.
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Pertaining to claim 3, Das teaches the semiconductor device assembly of claim 1, further comprising a plurality of electrically conductive spacers 301/306 being respectively:
coupled with the first patterned metal layer; and
coupled with the second patterned metal layer. See Figure 3 marked up above
Pertaining to claim 4, Das teaches the semiconductor device assembly of claim 1, wherein the conductive via is a first conductive via of a plurality of conductive vias defined through the second dielectric layer, the plurality of conductive vias electrically coupling respective signal terminals of the pre-molded semiconductor device module 170 with respective portions of the third patterned metal layer 134. See Figure 4 marked up below, note that this is an alternative embodiment illustrating that the semiconductor device can be connected in the manner as claimed, all other elements from claim 1 are also present in this embodiment.
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Pertaining to claim 5, Das teaches the semiconductor device assembly of claim 1, wherein the pre-molded semiconductor device module is a first pre-molded semiconductor device module 160, the semiconductor device assembly 300 further comprising:
a second pre-molded semiconductor device module 170 having:
a first side disposed on and electrically coupled with the first patterned metal layer; and
a second side opposite the first side disposed on and electrically coupled with the second patterned metal layer. See Figure 3 note that element 170 has the same connections as element 160 as rejected in Claim 1 above and shown above in marked up Figure 3.
Pertaining to claim 6, Das teaches the semiconductor device assembly of claim 5, wherein the conductive via is a first conductive via (the via is conductive), the second substrate further including a second conductive via electrically coupling a signal terminal of the second pre-molded semiconductor device module with the third patterned metal layer See rejection notes of claim 5 above, noting that the second pre-molded semiconductor device has all the same connections and features as the first as laid out in the rejection of claim 1 above. See Figure 3.
Pertaining to claim 11, Das teaches a semiconductor device assembly comprising:
a first substrate including:
a first dielectric layer (material in 110 surrounding conductive elements); and
a first patterned metal layer 114 See Figure 3 below including:
a first portion disposed on a surface of the first dielectric layer; and
a second portion that extends off the surface of the first dielectric layer;
See Figure 4 marked up below illustrating how element 114 has “first and second portions” (also present and applicable to Figure 3)
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a pre-molded semiconductor device module (note “pre-molded” is broad and is being interpreted as an integrated circuit structure) having a first side disposed on and electrically coupled with the first portion of the first patterned metal layer, the second portion of the first patterned metal layer being electrically coupled with a signal terminal of the pre-molded semiconductor device module via the first portion of the first patterned metal layer; See Figure 3 marked up below (see [0051] where Das teaches that the electrically conductive elements can comprise signal, ground and/or power) and
a second substrate including:
a second dielectric layer (material in 130 surrounding conductive elements); and
a second patterned metal layer 132 disposed on a surface of the second dielectric layer, the second patterned metal layer being disposed on and electrically coupled with a second side of the pre-molded semiconductor device module opposite the first side. See Figure 3 marked up below
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Pertaining to claim 13, Das teaches the semiconductor device assembly of claim 11, further comprising an electrically conductive spacer 304/305 see Figure 4 that is coupled with the pre-molded semiconductor device module 170 and the second patterned metal layer 132 (this is an alternative embodiment taught by Das shown in Figure 4, however, Figure 4 contains all the elements found in Claim 11.
Pertaining to claim 14, Das teaches the semiconductor device assembly of claim 11, further comprising a plurality of electrically conductive spacers 301/306 being respectively:
coupled with the first portion of the first patterned metal layer; and
coupled with the second patterned metal layer See Figure 3 marked up above.
Pertaining to claim 15, Das teaches the semiconductor device assembly of claim 11, wherein the second portion of the first patterned metal layer includes a plurality of extensions 302/303 that are electrically coupled with respective signal terminals of the pre-molded semiconductor device module Note “extensions” is broad and elements 302 and 303 can be considered electrically conductive extensions (ie the extend from element 114) see Figure 3.
Pertaining to claim 16, Das teaches the semiconductor device assembly of claim 11, wherein the pre-molded semiconductor device module is a first pre-molded semiconductor device module 160, the semiconductor device assembly 300 further comprising:
a second pre-molded semiconductor device module 170 having:
a first side disposed on and electrically coupled with the first patterned metal layer; and
a second side opposite the first side disposed on and electrically coupled with the second patterned metal layer. See Figure 3 note that element 170 has the same connections as element 160 as rejected in Claim 1 above and shown above in marked up Figure 3.
Pertaining to claim 17, Das teaches the semiconductor device assembly of claim 16, wherein the second portion of the first patterned metal layer includes:
a first plurality of extensions 302/303 that are electrically coupled with respective signal terminals of the first pre-molded semiconductor device module 160; and
a second plurality of extensions 304/305 that are electrically coupled with respective signal terminals of the second pre-molded semiconductor device module 170 see Figure 3.
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Pertaining to claim 21, Das teaches a method for producing a semiconductor device assembly, the method comprising:
coupling at least one pre-molded semiconductor device module 160/170 with a first patterned metal layer 114 disposed on a surface of a first dielectric layer of a first substrate 110;
coupling an output terminal and at least one power supply terminal with a second patterned metal layer 132 disposed on a first surface of a second dielectric layer of a second substrate 130,
the second substrate having a plurality of conductive vias see Figure 3 disposed through the second dielectric layer, the plurality of conductive vias electrically coupling respective signal terminals (see [0051] where Das teaches that the electrically conductive elements can comprise signal, ground and/or power) of the at least one pre-molded semiconductor device module with respective portions of a patterned metal layer disposed on a second surface of the second dielectric layer opposite the first surface See Figure 3 marked up below; and
coupling the second patterned metal layer 132 with:
the at least one pre-molded semiconductor device module 160; and
the first patterned metal layer 113 via a plurality of conductive spacers 301/305 see Figure 3 marked up below.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das et al as applied to claims 1 and 11 above, and further in view of Liu et al US 2004/0245228.
Pertaining to claims 2 and 12, Das teaches the semiconductor device assembly of claim 1, including power terminals and signal terminals terminals (see [0051] where Das teaches that the electrically conductive elements can comprise signal, ground and/or power) , but is silent with respect to welding them to the patterned metal layer. Liu teaches that laser welding is an alternative to heating and solder (taught by Das). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to use welding instead of soldering for the purpose of creating a very strong bond while eliminating the need for globally heating the device which could cause device element failures. [0005]
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das as applied to claims 6 and 16 above.
Pertaining to claim 7, Das teaches the semiconductor device assembly of claim 6, but as illustrated in Figure 4, Das teaches that only one pair of semiconductor device modules have a plurality of conductive vias. However, duplicating this connection to where both of the semiconductor device modules includes a plurality of vias would have been obvious to one of ordinary skill in the art at the time the invention was filed. The ordinary artisan would have found it obvious to include more than one connection to a semiconductor module depending on the design needs and function of the overall device. Das teaches this arrangement for one module (See Figure 4), duplicating that for both would have been a matter of design choice. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc. See Figure 4 marked up below.
See also In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a “web” which lies in the joint, and a plurality of “ribs” projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
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Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das as applied to claims 1 and 11 above, and further in view of Gerber et al US 2007/0234850.
Pertaining to claims 10 and 20, Das teaches the semiconductor device assembly of claims 1 and 11, but is silent wherein an area of the surface of the first dielectric layer of the first substrate is greater than an area of the first surface of the second dielectric layer of the second substrate (the examiner interprets this to mean that the first substrate is larger than the second substrate). However, this is a well known configuration that one of ordinary skill in the art at the time the invention was filed would have been familiar with in this art. Gerber teaches a first substrate 405 and a second substrate 401 that is not as larger (ie less area) than the first substrate 405. It would have been obvious to one of ordinary skill in the art to select the appropriate sizes of substrates under the course of routine experimentation and/or design needs/choice and it is not inventive to simply select different sizes for each substrate. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Allowable Subject Matter
Claims 8, 9, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The primary reason for the allowance of the claims is the inclusion of the limitation(s):
For claims 8 and 18, the prior art does not teach nor suggest a device further comprising a molding compound that: encapsulates the first pre-molded semiconductor device module, the second pre-molded semiconductor device module, and a plurality of electrically conductive spacers respectively coupled with the first patterned metal layer and the second patterned metal layer, and partially encapsulates the first substrate, the second substrate, an output signal terminal that is welded to the first patterned metal layer, and a plurality of power supply terminals that are respectively welded to the first patterned metal layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817