DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 6-9, 13-16, 19-22 and 25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-9, 13-16, 19-22 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takaike US 2010/0149768 and further in view of Kim et al US 6,232,563.
Pertaining to claims 1 and 7, Takaike teaches a semiconductor device, comprising:
an interconnect substrate 201;
a plurality of first conductive pads 205 formed over a first surface of the interconnect substrate 201;
a first insulating layer 212 formed over the first conductive pads 205; and
a first electrical component 211 disposed over the first surface of the interconnect substrate 201, wherein the first electrical component 211 includes an interconnect structure (solder ball) making electrical connection to the first conductive pads 205 through the first insulating layer 212 while leaving a portion of the first insulating layer 212 over a side surface of the interconnect structure (solder ball) see Figure 4 marked up below.
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Takaike fails to teach a thickness of the first insulating layer being less than a height of the interconnect structure of the first electrical component. Kim teaches an electrical component including an interconnect structure (See Figure 6A below) making electrical connection to conductive pads 16’ see figure 5D below through the first insulating layer 18’ while leaving a portion of the first insulating layer 18’ over a side surface of the interconnect structure see Figure 6a below and a thickness of the first insulating layer is less than a height of the interconnect structure of the first electrical component see Figure 6a below.
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It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the insulating layer taught by Kim with the interconnect and pad structure of Takaike, the ordinary artisan would have been motivated to do so for the purpose of preventing electrical shorts through the side surface Abstract of Kim.
Pertaining to claims 2 and 8, Takaike in view of Kim teaches the semiconductor device of claim 1 and 7, wherein the first conductive pads include a fine pitch Conductive pads 205 have a pitch, and at this scale they would be considered fine. In fact, “fine pitch” is vague since it has no basis of comparison and one could argue any pitch could be fine compared to a pitch that is larger, whatever those dimensions may be.
Pertaining to claims 3 and 9, Takaike in view of Kim teaches the semiconductor device of claim 1 and 7, wherein the first insulating layer 212 is formed over a side surface and a top surface of the first conductive pads 205 see Figure 4 pads 205 are surrounded on sides and top surface by insulating layer 212.
Pertaining to claims 6 and 13, Takaike in view of Kim teaches the semiconductor device of claim 1 and 7, further including:
a plurality of second conductive pads 208 formed over a second surface of the interconnect substrate 201;
a second insulating layer 215 formed over the second conductive pads 208 see Figure 5; and
a second electrical component 214 disposed over the second surface of the interconnect substrate and making electrical connection (through solder balls) to the second conductive pads 208 through the second insulating layer 215 see Figure 5 marked up below.
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Pertaining to claims 14 and 20, Takaike teaches a method of making a semiconductor device, comprising:
providing an interconnect substrate 201;
forming a plurality of first conductive pads 205 over a first surface of the interconnect substrate 201;
forming a first insulating layer 212 over the first conductive pads 205; and
disposing a first electrical component 211 over the first surface of the interconnect substrate 201, wherein the first electrical component 211 includes an interconnect structure (solder ball) making electrical connection to the first conductive pads 205 through the first insulating layer 212 while leaving a portion of the first insulating layer 212 over a side surface of the interconnect structure (solder ball) see Figure 4 marked up above.
Takaike fails to teach a thickness of the first insulating layer being less than a height of the interconnect structure of the first electrical component. Kim teaches an electrical component including an interconnect structure (See Figure 6A below) making electrical connection to conductive pads 16’ see figure 5D below through the first insulating layer 18’ while leaving a portion of the first insulating layer 18’ over a side surface of the interconnect structure see Figure 6a below and a thickness of the first insulating layer is less than a height of the interconnect structure of the first electrical component see Figure 6a below.
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It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the insulating layer taught by Kim with the interconnect and pad structure of Takaike, the ordinary artisan would have been motivated to do so for the purpose of preventing electrical shorts through the side surface Abstract of Kim.
Pertaining to claims 15 and 21, Takaike in view of Kim teaches the method of claims 14 and 20, wherein the first conductive pads include a fine pitch. Conductive pads 205 have a pitch, and at this scale they would be considered fine. In fact, “fine pitch” is vague since it has no basis of comparison and one could argue any pitch could be fine compared to a pitch that is larger, whatever those dimensions may be.
Pertaining to claims 16 and 22, Takaike in view of Kim teaches the method of claims 14 and 20, further including forming the first insulating layer over a side surface and a top surface of the first conductive pads. See Figure 4 pads 205 are surrounded on sides and top surface by insulating layer 212
Pertaining to claims 19 and 25, Takaike in view of Kim teaches the method of claims 14 and 20, further including:
forming a plurality of second conductive pads 208 formed over a second surface of the interconnect substrate 201;
forming a second insulating layer 215 formed over the second conductive pads 208 see Figure 5; and
disposing a second electrical component 214 disposed over the second surface of the interconnect substrate and making electrical connection (through solder balls) to the second conductive pads 208 through the second insulating layer 215 see Figure 5 marked up above
Claim(s) 4, 5, 10-12, 17, 18, 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takaike/Kim as applied to claims 1, 7, 14 and 20 above, and further in view of Ooi et al US 2009/0215619.
Pertaining to claims 4 and 10 and 17 and 23, Takaike/Kim teaches the semiconductor device (and method) of claims 1, 6, 14 and 20 above, including an interconnect substrate that is a core substrate 201, but is silent, wherein the core substrate includes:
a first conductive layer formed over a first surface of the core substrate; and
a first insulating layer formed over the first conductive layer.
Ooi teaches:
a core substrate including a core layer 13
a first conductive layer 11 formed over a first surface of the core substrate 10; and
a first insulating layer 20 formed over the first conductive layer.
It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Takaike and Ooi to enable the core substrate formation step of Takaike to be performed according to the teachings of Ooi because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed the core substrate formation step of Takaike and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Pertaining to claims 5 and 11 and 18 and 24, Takaike/Kim in view of Ooi teaches the semiconductor device (method) of claims 4, 10, 17 and 23, wherein the interconnect substrate includes:
a second conductive layer 12 (Ooi) formed over a second surface of the core substrate 13 opposite the first surface of the core substrate; and
a second insulating layer 21 formed over the second conductive layer 12 see Figure 4 of Ooi.
Pertaining to claim 12, Takaike/Kim in view of Ooi teaches the semiconductor device of claim 11, further including a bump formed over the second conductive layer. Takaike teaches that bumps are formed over the conductive layers above the core substrate layer 201, see Takaike Figure 5 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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