DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-9, 13-16, 19-22 and 25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takaike US 2010/0149768.
Pertaining to claims 1 and 7, Takaike teaches a semiconductor device, comprising:
an interconnect substrate 201;
a plurality of first conductive pads 205 formed over a first surface of the interconnect substrate 201;
a first insulating layer 212 formed over the first conductive pads 205; and
a first electrical component 211 disposed over the first surface of the interconnect substrate 201, wherein the first electrical component 211 includes an interconnect structure (solder ball) making electrical connection to the first conductive pads 205 through the first insulating layer 212 while leaving a portion of the first insulating layer 212 over a side surface of the interconnect structure (solder ball) see Figure 4 marked up below.
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Pertaining to claims 2 and 8, Takaike teaches the semiconductor device of claim 1 and 7, wherein the first conductive pads include a fine pitch Conductive pads 205 have a pitch, and at this scale they would be considered fine. In fact, “fine pitch” is vague since it has no basis of comparison and one could argue any pitch could be fine compared to a pitch that is larger, whatever those dimensions may be.
Pertaining to claims 3 and 9, Takaike teaches the semiconductor device of claim 1 and 7, wherein the first insulating layer 212 is formed over a side surface and a top surface of the first conductive pads 205 see Figure 4 pads 205 are surrounded on sides and top surface by insulating layer 212.
Pertaining to claims 6 and 13, Takaike teaches the semiconductor device of claim 1 and 7, further including:
a plurality of second conductive pads 208 formed over a second surface of the interconnect substrate 201;
a second insulating layer 215 formed over the second conductive pads 208 see Figure 5; and
a second electrical component 214 disposed over the second surface of the interconnect substrate and making electrical connection (through solder balls) to the second conductive pads 208 through the second insulating layer 215 see Figure 5 marked up below.
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Pertaining to claims 14 and 20, Takaike teaches a method of making a semiconductor device, comprising:
providing an interconnect substrate 201;
forming a plurality of first conductive pads 205 over a first surface of the interconnect substrate 201;
forming a first insulating layer 212 over the first conductive pads 205; and
disposing a first electrical component 211 over the first surface of the interconnect substrate 201, wherein the first electrical component 211 includes an interconnect structure (solder ball) making electrical connection to the first conductive pads 205 through the first insulating layer 212 while leaving a portion of the first insulating layer 212 over a side surface of the interconnect structure (solder ball) see Figure 4 marked up above.
Pertaining to claims 15 and 21, Takaike teaches the method of claims 14 and 20, wherein the first conductive pads include a fine pitch. Conductive pads 205 have a pitch, and at this scale they would be considered fine. In fact, “fine pitch” is vague since it has no basis of comparison and one could argue any pitch could be fine compared to a pitch that is larger, whatever those dimensions may be.
Pertaining to claims 16 and 22, Takaike teaches the method of claims 14 and 20, further including forming the first insulating layer over a side surface and a top surface of the first conductive pads. See Figure 4 pads 205 are surrounded on sides and top surface by insulating layer 212
Pertaining to claims 19 and 25, Takaike teaches the method of claims 14 and 20, further including:
forming a plurality of second conductive pads 208 formed over a second surface of the interconnect substrate 201;
forming a second insulating layer 215 formed over the second conductive pads 208 see Figure 5; and
disposing a second electrical component 214 disposed over the second surface of the interconnect substrate and making electrical connection (through solder balls) to the second conductive pads 208 through the second insulating layer 215 see Figure 5 marked up above
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, 10-12, 17, 18, 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takaike as applied to claims 1, 7, 14 and 20 above, and further in view of Ooi et al US 2009/0215619.
Pertaining to claims 4 and 10 and 17 and 23, Takaike teaches the semiconductor device (and method) of claims 1, 6, 14 and 20 above, including an interconnect substrate that is a core substrate 201, but is silent, wherein the core substrate includes:
a first conductive layer formed over a first surface of the core substrate; and
a first insulating layer formed over the first conductive layer.
Ooi teaches:
a core substrate including a core layer 13
a first conductive layer 11 formed over a first surface of the core substrate 10; and
a first insulating layer 20 formed over the first conductive layer.
It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Takaike and Ooi to enable the core substrate formation step of Takaike to be performed according to the teachings of Ooi because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed the core substrate formation step of Takaike and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Pertaining to claims 5 and 11 and 18 and 24, Takaike in view of Ooi teaches the he semiconductor device (method) of claims 4, 10, 17 and 23, wherein the interconnect substrate includes:
a second conductive layer 12 (Ooi) formed over a second surface of the core substrate 13 opposite the first surface of the core substrate; and
a second insulating layer 21 formed over the second conductive layer 12 see Figure 4 of Ooi.
Pertaining to claim 12, Takaike in view of Ooi teaches the semiconductor device of claim 11, further including a bump formed over the second conductive layer. Takaike teaches that bumps are formed over the conductive layers above the core substrate layer 201, see Takaike Figure 5 above.
Conclusion
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817