DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 12/16/25 is acknowledged. The traversal is on the ground(s) that because the method is used to manufacture the device that they should be examined together. This is not found persuasive because different classification for the two claimed inventions is proof of serious burden in and of itself. As stated in MPEP 808.02, a serious burden is present when there is A) Separate classification thereof: this shows that each invention has attained recognition in the art as a separate subject for inventive effort, and also a separate field of search. The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haneda et al US 2012/0256264.
Pertaining to claim 1, Haneda teaches a transistor structure, comprising:
a first transistor device, formed on a first active region 11A of a semiconductor substrate 11, and comprising:
a first gate structure 13G1, disposed on the first active region 11A;
first gate spacers 13SW1, formed along opposite sidewalls of the first gate structure 13G1;
first source/drain structures See Figure 5C marked up below, formed in recesses of the first active region 11A at opposite sides of the first gate structure 13G1;
first buried isolation structures 11IF, separately extending along bottom sides of the first source/drain structures; and
a first strained etching stop layer 17A see [0214], covering the first source/drain structures, the first gate spacers and the first gate structure, and formed with tensile or compressive stressors See Figure 5C marked up below.
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Pertaining to claim 2, Haneda teaches the transistor structure according to claim 1, wherein the first source/drain structures are in lateral contact with straight sidewalls of the recesses that are substantially aligned with the sidewalls of the first gate structure. See Figure 5C marked up below
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Pertaining to claim 3, Haneda teaches the transistor structure according to claim 1, including first source/drain structures. Haneda teaches source/drain structure, their method of production in this case (ie grown from curved or depressed sidewalls) is not patentably relevant to the claimed invention as it is a product-by-process limitation. Product-By-Process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps.
“Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted) (Claim was directed to a novolac color developer. The process of making the developer was allowed. The difference between the inventive process and the prior art was the addition of metal oxide and carboxylic acid as separate ingredients instead of adding the more expensive pre-reacted metal carboxylate. The product-by-process claim was rejected because the end product, in both the prior art and the allowed process, ends up containing metal carboxylate. The fact that the metal carboxylate is not directly added, but is instead produced in-situ does not change the end product.).
Pertaining to claim 4, Haneda teaches the transistor structure according to claim 1, wherein the first active region 11A is a fin structure defined at a top surface of the semiconductor substrate 11, and the first gate structure 13G1 crosses the first active region 11A, such that the first active region is in contact with the first gate structure by a top surface and opposite sidewalls See Figure 5C.
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Pertaining to claim 6, Haneda teaches the transistor structure according to claim 1, wherein each of the first source/drain structures is grown from a single crystalline plane of the first active region. [0190]
Pertaining to claim 7, Haneda teaches the transistor structure according to claim 1, wherein the first transistor device is an N-type MOSFET (Haneda teaches that 11A is P-type and 11B is N-type, [0127][0128] but it doesn’t matter which transistor is which, Haneda teaches a MOSFET with a P-type and N-type transistor), the first strained etching stop layer is formed with tensile stressors (see [0214] the configuration increases uniaxial tensile stress), and the transistor structure further comprises:
a second transistor device as a P-type MOSFET, formed on a second active region 11B (or 11A it doesn’t matter) of the semiconductor substrate, and comprising:
a second gate structure 13G2;
second gate spacers See Figure 5C spaces adjacent 13G2, formed along opposite sidewalls of the second gate structure;
second source/drain structures, formed in recesses of the second active region at opposite sides of the second gate structure See Figure 5C marked up below;
second buried isolation structures 11IF, formed in the second active region, and separately extending along bottom sides of the second source/drain structures; and
a second strained etching stop layer 17B, covering the second source/drain structures, the second gate spacers and the second gate structure, and formed with compressive stressors. See Figure 5C.
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Pertaining to claim 8, Haneda teaches the transistor structure according to claim 7, wherein the first and second strained etching stop layers are both formed of silicon nitride [0214].
Pertaining to claim 9, Haneda teaches the transistor structure according to claim 7, further comprising:
a trench isolation structure 11I1/11I2/11I3, formed into the semiconductor substrate, and laterally surrounding each of the first and second active regions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haneda and further in view of Xu et al US 2016/0035891.
Pertaining to claim 11, Haneda teaches the transistor structure, comprising:
a transistor device, formed on an active region 11A of a semiconductor substrate, and comprising:
a gate structure 13G1;
gate spacers, formed along opposite sidewalls of the gate structure See Figure 5C marked up below;
source/drain structures See Figure 5C marked up below, filled in recesses of the active region at opposite sides of the gate structure See Figure 5C marked up below, and respectively comprising a first semiconductor region and a second semiconductor region See Figure 5C marked up below, wherein the first semiconductor region is in lateral contact with a sidewall of one recess and the second semiconductor region laterally extends from the first semiconductor region; and
buried isolation structures 11IF, formed along bottom sides of the recesses, and are laterally separated from each other. See Figure 5C marked up below
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Haneda fails to teach that the semiconductor region is formed with dislocation stressors.
Xu teaches that dislocation stress applied to source and drain elements in a CMOS structure increases the mobility of the conduction channel [0053]. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Xu into the device of Haneda by applying dislocation stress to the source/drain elements. The ordinary artisan would have been motivated to modify Haneda in the manner set forth above for at least the purpose of increasing channel mobility.
Pertaining to claim 12, Haneda in view of Xu teaches the transistor structure according to claim 11, wherein the dislocation stressors result in tensile stress or compressive stress in a channel portion of the active region between the source/drain structures. Xu teaches that tensile stress is provided in the channel [0059]
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haneda and further in view of Fujiwara US2003/0102499.
Pertaining to claim 5, Haneda teaches the transistor structure according to claim 1, wherein the first buried isolation structures, but is silent wherein they respectively comprise a first localized isolation layer and a second localized isolation layer, the first localized isolation layer lies under the second localized isolation layer, and further extends to be in lateral contact with an edge of the second localized isolation layer and in contact with the overlying one of the first source/drain structures from below.
Fujiwara teaches buried isolation structure that comprises a first localized isolation layer 21 and a second localized isolation layer 22 see Figure 18, the first localized isolation layer 21 lies under the second localized isolation layer 22, and further extends to be in lateral contact with an edge of the second localized isolation layer and in contact with the overlying one of the first source/drain structures from below See Figure 18 marked up below
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It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Haneda and Fujiwara to enable the buried isolation structure formation step of Haneda to be performed according to the teachings of Fujiwara because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed buried isolation structure formation step of Haneda and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haneda and further in view of Tang et al US 2009/0224328.
Pertaining to claim 10, Haneda teaches the transistor structure according to claim 9, but does not teach wherein a top surface of the trench isolation structure is higher than topmost surfaces of the first and second active regions. Tang teaches a CMOS device with trench isolation structures having a top surface higher than the topmost surface of the active regions See Figure 13 (marked up below) elements 330.
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It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Haneda and Tang to enable the trench isolation formation step of Haneda to be performed according to the teachings of Tang because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed trench isolation formation step of Haneda and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haneda and further in view of Kubo US 5,463,241.
Pertaining to claim 13, Haneda teaches the transistor structure according to claim 11, but fails to teach wherein a doping concentration in the first semiconductor region is lower than a doping concentration in the second semiconductor region. Kubo teaches a CMOS transistor with first and second semiconductor regions, the first region having a lower doping concentration than the second region See Figure 3 marked up below.
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It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Kubo into the device of Haneda by including the two regions with different doping profiles as claimed (first region lower than second region). The ordinary artisan would have been motivated to modify Haneda in the manner set forth above for at least the purpose of greatly reducing junction capacitance See Kubo Col 5 lines 11-26.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817