Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed 05/18/2026 (“Amend.”), in which: claims 16 and 18-23 are amended; and the rejection of the claims are traversed. Claims 16-35 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 16-27 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16, 18, 19, 21-23, 25, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coolbaugh, US 20110115005, in view of Lee et al, US 6080615.
Regarding claim 16, Coolbaugh teaches : A method of forming an integrated chip structure, comprising: forming an isolation structure within a trench formed by sidewalls of a substrate(Fig. 7, #104); forming a first conductive layer over the high-voltage dielectric layer(#112); patterning the first conductive layer to form a first capacitor conductor over the high-voltage dielectric layer(#112 is a capacitor plate); forming a capacitor dielectric along sidewalls and an upper surface of the first capacitor conductor(#120 along the sidewalls of #112 [0017]); forming a second conductive layer along a sidewall and an upper surface of the capacitor dielectric(#140 shown to be along a sidewall and upper surface of #120 [0020]); patterning the second conductive layer to form a second capacitor conductor along the sidewall and the upper surface of the capacitor dielectric(#140 patterned to be a second capacitor plate along the sidewall and upper surface of #120 [0022]).
Coolbaugh does not disclose : forming a high-voltage dielectric layer over the isolation structure and the substrate; and patterning the high-voltage dielectric layer to etch completely through and remove peripheral parts of the high-voltage dielectric layer that are laterally outside of the first capacitor conductor and the second capacitor conductor, wherein patterning the high- voltage dielectric layer forms a lower dielectric between the isolation structure and lower surfaces of the first capacitor conductor and the second capacitor conductor.
However, in the same field of endeavor, Lee teaches : forming a high-voltage dielectric layer over the isolation structure and the substrate(Fig. 4c, #23 on #22 and #21); and patterning the high-voltage dielectric layer to etch completely through and remove peripheral parts of the high-voltage dielectric layer that are laterally outside of the first capacitor conductor and the second capacitor conductor, wherein patterning the high- voltage dielectric layer forms a lower dielectric between the isolation structure and lower surfaces of the first capacitor conductor and the second capacitor conductor(Fig. 4d, #24 etched completely through to form #23 between #22, #26b and #26a).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Lee to Coolbaugh to include a dielectric layer that is completely etched through between an isolation and a first and second capacitor plate to simplify a manufacturing process (Lee, Col. 4 line 45-50).
Regarding claim 18, Coolbaugh as modified by Lee discloses : The method of claim 16.
Lee teaches : wherein the isolation structure laterally extends for non-zero distances past opposing outermost sidewalls of the high-voltage dielectric layer(Fig. 4e, #22 shown to extend past opposing sidewalls of #23).
Regarding claim 19, Coolbaugh as modified by Lee discloses : The method of claim 16,
Lee teaches : wherein the lower dielectric is disposed vertically above topmost surfaces of both the isolation structure and the substrate(Fig. 4e, #23 disposed above #21 and #22).
Regarding claim 21, Coolbaugh discloses : A method of forming an integrated chip structure, comprising: depositing a first conductive layer over the first dielectric(Fig. 7, #104 may include a dielectric [0015] with #112 over #104); patterning the first conductive layer to form a first conductor over the first dielectric(#112 may be patterned to be a first capacitor plate [0016]); forming a second dielectric along a sidewall and an upper surface of the first conductor(#120 along a sidewall and upper surface of #112 [0017]); depositing a second conductive layer along a sidewall and an upper surface of the second dielectric(#140 along a side wall and upper surface of #120 [0020]); and patterning the second conductive layer to form a second conductor along the sidewall and the upper surface of the second dielectric(#140 etched to be formed along a sidewall and upper surface of #120 [0022])
Coolbaugh does not disclose : forming a first dielectric over a substrate; and forming a first sidewall spacer along a first side of the second conductor and a second sidewall spacer along a second side of the second conductor, the second sidewall spacer being over the second dielectric and having an outermost sidewall laterally between opposing outermost edges of both the first conductor and the second dielectric.
However, in the same field of endeavor, Lee teaches : forming a first dielectric over a substrate(Fig. 4c, #23 over #21); and forming a first sidewall spacer along a first side of the second conductor and a second sidewall spacer along a second side of the second conductor(Fig. 4e, #30 on along a sidewall of #26a).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Lee to Coolbaugh to include sidewall spacers on the sidewalls of a first and second capacitor conductor.
Coolbaugh as modified by Lee teaches : the second sidewall spacer being over the second dielectric and having an outermost sidewall laterally between opposing outermost edges of both the first conductor and the second dielectric(With the teachings of Lee, sidewalls spacers may include in both a first capacitor plate and a second capacitor plate. Fig. 7, of Coolbaugh, the sidewall spacers of Lee may be included in #140 which would place a second sidewall between an outermost edge of #114 and #120).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Lee to Coolbaugh to include sidewall spacers on the sidewalls of a first and second capacitor conductor.
Regarding claim 22, Coolbaugh as modified by Lee discloses : The method of claim 21.
Coolbaugh teaches : further comprising: forming an inter-level dielectric material over and along sidewalls of the second conductor(Fig. 7, #151 over #140, #151 may be a dielectric [0027]); and performing a planarization process on the second conductor and the inter-level dielectric material(#151 deposited and planarized), wherein the planarization process causes the second conductor to have a curved upper surface continuously extending from directly over the first conductor to laterally outside of the first conductor; and forming a metal onto the curved upper surface(#149 may be formed in#140 similar to the process of #132 [0027] where a recess is shown in #114 shown by #128. #149 is above #114 and laterally outside of #114).
Regarding claim 23, Coolbaugh as modified by Lee discloses : The method of claim 21.
Lee teaches : further comprising: patterning the first dielectric using the second conductor and the first sidewall spacer as a mask(Fig. 4c, #28 is the same size as #26b and is used as a mask to pattern #23).
Regarding claim 25, Coolbaugh as modified by Lee discloses : : The method of claim 21.
Coolbaugh teaches : further comprising: etching the substrate to form a trench; forming an isolation dielectric within the trench(Etch to form #104 [0015])); and forming the first dielectric over the isolation dielectric(#104 may include any appropriate dielectric [0015]).
Regarding claim 26, Coolbaugh as modified by Lee discloses : The method of claim 25.
Coolbaugh teaches : wherein the isolation dielectric laterally extends past opposing outermost edges of the first dielectric after patterning the second conductive layer The method of claim 25, wherein the isolation dielectric laterally extends past opposing outermost edges of the first dielectric after patterning the second conductive layer(Fig. 7, after patterning of #140 [0025-0027] , #104 shown to extend past opposing edges of #120).
Claim(s) 17 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coolbaugh, US 20110115005, in view of Lee et al, US 6080615 in further view of Lee, US 20080006866, hereafter ‘866.
Regarding claim 17, Coolbaugh as modified by Lee discloses : The method of claim 16,.
Coolbaugh as modified by Lee does not disclose : further comprising: selectively patterning the substrate to form a high-voltage gate dielectric recess within the substrate; forming a first high-voltage gate dielectric within the high-voltage gate dielectric recess; and patterning the high-voltage dielectric layer to form a second high-voltage gate dielectric over the first high-voltage gate dielectric and within the high-voltage gate dielectric recess.
However, in the same field of endeavor, ‘866 teaches : further comprising: selectively patterning the substrate to form a high-voltage gate dielectric recess within the substrate(Fig. 2a, #125); forming a first high-voltage gate dielectric within the high-voltage gate dielectric recess(Fig. 2e, #135 formed in #125[0032]); and patterning the high-voltage dielectric layer to form a second high-voltage gate dielectric over the first high-voltage gate dielectric and within the high-voltage gate dielectric recess(Fig. 2i, #180 may function as gate insulting layer #185 and #182 may be a capacitor dielectric layer with #182 and #185 formed from #180 [0033-0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of ‘866 to Coolbaugh and Lee to form a gate dielectric and an isolation dielectric from the same layer so as to simplify a fabrication process ([‘866, 0053]).
Regarding claim 27, Coolbaugh as modified by Lee discloses : The method of claim 25.
Coolbaugh as modified by Lee does not disclose : further comprising: etching an upper surface of the substrate to form a recess that is laterally separated from the isolation dielectric by the substrate; forming a gate dielectric along sidewalls of the substrate forming the recess, wherein the first dielectric continuously extends from over the isolation dielectric to within the recess and over the gate dielectric; and wherein patterning the second conductive layer forms a gate structure over a part of the first dielectric that is within the recess.
However, in the same field of endeavor, Lee teaches : further comprising: etching an upper surface of the substrate to form a recess that is laterally separated from the isolation dielectric by the substrate(Fig. 2a, #125 in region #105 with capacitor in region #101); forming a gate dielectric along sidewalls of the substrate forming the recess(Fig. 2e, #135 formed in #125[0032]), wherein the first dielectric continuously extends from over the isolation dielectric to within the recess and over the gate dielectric(Fig. 2i, #180 may function as gate insulting layer #185 and #182 may be a capacitor dielectric layer with #182 and #185 formed from #180 [0033-0034]); and wherein patterning the second conductive layer forms a gate structure over a part of the first dielectric that is within the recess(Fig. 2h, #190 in both regions #101 and #105 with #195 formed over #105 and #191 formed over #101).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of ‘866 to Coolbaugh and Lee to form a gate dielectric and an isolation dielectric from the same layer and a conductive layer to form a gate structure and capacitor conductor so as to simplify a fabrication process ([Lee, 0053]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coolbaugh, US 20110115005, in view of Lee et al, US 6080615 in further view of Nakao, US 20110169135.
Regarding claim 20, Coolbaugh as modified by Lee discloses : The method of claim 16.
Coolbaugh as modified by Lee does not disclose : wherein the second capacitor conductor comprises a recess formed by a curved upper surface straddling an outermost sidewall of the first capacitor conductor, a metal inset being disposed within the recess.
However, in the same field of endeavor, Nakao teaches : wherein the second capacitor conductor comprises a recess formed by a curved upper surface straddling an outermost sidewall of the first capacitor conductor, a metal inset being disposed within the recess(Fig. 3g, curved recess in #21 with #48 disposed in recess).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Nakao to Coolbaugh and Lee to modified a capacitor plate to include a recess and a contact metal.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coolbaugh, US 20110115005, in view of Lee et al, US 6080615 in further view of Wong et al, US 20230046455.
Regarding claim 24, Coolbaugh as modified by Lee discloses : The method of claim 21.
Coolbaugh teaches : wherein the second conductor comprises a first upper surface over the first conductor and a second upper surface laterally outside of the first conductor(Fig. 7, #140 of region #127 laterally outside #112 and another upper surface #140 directly over #112).
Coolbaugh as modified by Lee does not disclose : the first upper surface being vertically above the second upper surface.
However, in the same field of endeavor, Wong teaches : the first upper surface being vertically above the second upper surface(Fig. 1b, #118 shown to be a second conductive layer of a capacitor with an upper surface with two different heights #118a and #118b with #118a overlapping #114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Wong to Coolbaugh and Lee to form a conductive layer with different heights to prevent electrical shorts (Wong [0034]).
Allowable Subject Matter
Claim 28, 29, and 30-35 allowed.
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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