Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group I, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 01/06/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16, 21, 22, 25, and 26 is/are rejected under 35 U.S.C. 103 as being anticipated by Coolbaugh et al, US 20110115005, hereafter ‘Coolbaugh’ in view of Ikegami, US 20060255439, hereafter ‘Ikegami’.
Regarding claim 16, Coolbaugh discloses : A method of forming an integrated chip structure, comprising: forming an isolation structure within a trench formed by sidewalls of a substrate(Fig.7, #104) ; forming a first conductive layer over the high-voltage dielectric layer(#112); patterning the first conductive layer to form a first capacitor conductor over the high-voltage dielectric layer(#112 is a capacitor plate); forming a capacitor dielectric along sidewalls and an upper surface of the first capacitor conductor(#120 along the sidewalls of #112 [0017]); forming a second conductive layer along a sidewall and an upper surface of the capacitor dielectric(#140 shown to be along a sidewall and upper surface of #120 [0020]); patterning the second conductive layer to form a second capacitor conductor along the sidewall and the upper surface of the capacitor dielectric(#140 patterned to be a second capacitor plate along the sidewall and upper surface of #120 [0022]).
Coolbaugh does not explicitly discloses : forming a high-voltage dielectric layer over the isolation structure and the substrate; and patterning the high-voltage dielectric layer to form a lower dielectric between the isolation structure and lower surfaces of the first capacitor conductor and the second capacitor conductor.
However, in the same field of endeavor, Ikegami teaches : forming a high-voltage dielectric layer over the isolation structure and the substrate(Fig. 1L, #12 insulating layer pf an element isolation region [0007]) and patterning the high-voltage dielectric layer to form a lower dielectric between the isolation structure and lower surfaces of the first capacitor conductor and the second capacitor conductor(#12 shown to be in contact with #20 and #12).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Ikegami to Coolbaugh to include a dielectric layer between an isolation structure and the lower surfaces of the first and second capacitor conductor since the teachings of Coolbaugh is open to the idea of including a dielectric in a trench isolation (Coolbaugh [0015]).
Regarding claim 21, Coolbaugh discloses : A method of forming an integrated chip structure, comprising: depositing a first conductive layer over the first dielectric(Fig. 7, #104 may include a dielectric [0015] with #112 over #104); patterning the first conductive layer to form a first conductor over the first dielectric(#112 may be patterned to be a first capacitor plate [0016]); forming a second dielectric along a sidewall and an upper surface of the first conductor(#120 along a sidewall and upper surface of #112 [0017]); depositing a second conductive layer along a sidewall and an upper surface of the second dielectric(#140 along a side wall and upper surface of #120 [0020]); and patterning the second conductive layer to form a second conductor along the sidewall and the upper surface of the second dielectric(#140 etched to be formed along a sidewall and upper surface of #120 [0022]).
Coolbaugh does not explicitly disclose : forming a first dielectric over a substrate.
However, in the same field of endeavor Ikegami teaches : forming a first dielectric over a substrate(#12 formed on substrate [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Ikegami to Coolbaugh to include a dielectric layer over the substrate since the teachings of Coolbaugh is open to the idea of including a dielectric in a trench isolation (Coolbaugh [0015]).
Regarding claim 22, Coolbaugh as modified by Ikegami discloses : The method of claim 21.
Coolbaugh teaches : further comprising: forming an inter-level dielectric material over and along sidewalls of the second conductor(Fig. 4, #130 over #140); and performing a planarization process on the second conductor and the inter-level dielectric material(#130 and #140 planarized [0019-0022]).
Regarding claim 25, Coolbaugh as modified by Ikegami discloses : The method of claim 21.
Coolbaugh teaches : further comprising: etching the substrate to form a trench; forming an isolation dielectric within the trench(Etch to form #104 [0015])); and forming the first dielectric over the isolation dielectric(#104 may include any appropriate dielectric [0015]).
Regarding claim 26, Coolbaugh as modified by Ikegami discloses : The method of claim 25.
Coolbaugh teaches : wherein the isolation dielectric laterally extends past opposing outermost edges of the first dielectric after patterning the second conductive layer The method of claim 25, wherein the isolation dielectric laterally extends past opposing outermost edges of the first dielectric after patterning the second conductive layer(Fig. 7, after patterning of #140 [0025-0027] , #104 shown to extend past opposing edges of #120).
Claims 17 and 27 is/are rejected under 35 U.S.C. 103 as being anticipated by Coolbaugh et al, US 20110115005, hereafter ‘Coolbaugh’ in view of Ikegami, US 20060255439, hereafter ‘Ikegami’, and in further view of Lee, US 20080006866, hereafter ‘Lee’.
Regarding claim 17, Coolbaugh as modified by Ikegami discloses : The method of claim 16,.
Coolbaugh as modified by Ikagami does not disclose : further comprising: selectively patterning the substrate to form a high-voltage gate dielectric recess within the substrate; forming a first high-voltage gate dielectric within the high-voltage gate dielectric recess; and patterning the high-voltage dielectric layer to form a second high-voltage gate dielectric over the first high-voltage gate dielectric and within the high-voltage gate dielectric recess.
However, in the same field of endeavor, Lee teaches : further comprising: selectively patterning the substrate to form a high-voltage gate dielectric recess within the substrate(Fig. 2a, #125); forming a first high-voltage gate dielectric within the high-voltage gate dielectric recess(Fig. 2e, #135 formed in #125[0032]); and patterning the high-voltage dielectric layer to form a second high-voltage gate dielectric over the first high-voltage gate dielectric and within the high-voltage gate dielectric recess(Fig. 2i, #180 may function as gate insulting layer #185 and #182 may be a capacitor dielectric layer with #182 and #185 formed from #180 [0033-0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Lee to Coolbaugh and Ikagami to form a gate dielectric and an isolation dielectric from the same layer so as to simplify a fabrication process ([Lee, 0053]).
Regarding claim 27, Coolbaugh as modified by Ikegami discloses : The method of claim 25.
Coolbaugh as modified by Ikegami does not disclose : further comprising: etching an upper surface of the substrate to form a recess that is laterally separated from the isolation dielectric by the substrate; forming a gate dielectric along sidewalls of the substrate forming the recess, wherein the first dielectric continuously extends from over the isolation dielectric to within the recess and over the gate dielectric; and wherein patterning the second conductive layer forms a gate structure over a part of the first dielectric that is within the recess.
However, in the same field of endeavor, Lee teaches : further comprising: etching an upper surface of the substrate to form a recess that is laterally separated from the isolation dielectric by the substrate(Fig. 2a, #125 in region #105 with capacitor in region #101); forming a gate dielectric along sidewalls of the substrate forming the recess(Fig. 2e, #135 formed in #125[0032]), wherein the first dielectric continuously extends from over the isolation dielectric to within the recess and over the gate dielectric(Fig. 2i, #180 may function as gate insulting layer #185 and #182 may be a capacitor dielectric layer with #182 and #185 formed from #180 [0033-0034]); and wherein patterning the second conductive layer forms a gate structure over a part of the first dielectric that is within the recess(Fig. 2h, #190 in both regions #101 and #105 with #195 formed over #105 and #191 formed over #101).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Lee to Coolbaugh and Ikagami to form a gate dielectric and an isolation dielectric from the same layer and a conductive layer to form a gate structure and capacitor conductor so as to simplify a fabrication process ([Lee, 0053]).
Claims 18 and 19 is/are rejected under 35 U.S.C. 103 as being anticipated by Coolbaugh et al, US 20110115005, hereafter ‘Coolbaugh’ in view of Ikegami, US 20060255439, hereafter ‘Ikegami’, in further view of Lee, US 20080006866, hereafter ‘Lee’, and Cheng, US 20180254218, hereafter ‘Cheng’.
Regarding claim 18, Coolbaugh as modified by Ikegami and Lee discloses : The method of claim 17.
Coolbaugh as modified by Ikegami and Lee does not disclose : further comprising: patterning the substrate to form one or more fins of semiconductor material; and forming a logic gate dielectric along sidewalls and an upper surface of the one or more fins of semiconductor material, wherein the logic gate dielectric is formed concurrent to forming the capacitor dielectric on the first capacitor conductor.
However, in the same field of endeavor, Cheng teaches : further comprising: patterning the substrate to form one or more fins of semiconductor material(Fig. 10, #113 and #114); and forming a logic gate dielectric along sidewalls and an upper surface of the one or more fins of semiconductor material(#142 along the sidewalls and upper surfaces of #113 and #114), wherein the logic gate dielectric is formed concurrent to forming the capacitor dielectric on the first capacitor conductor(#142 is also a dielectric of a MIM capacitor [0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Cheng to Coolbaugh, Ikegami, and Lee to use a dielectric layer to form both a dielectric of semiconductor fins and a dielectric of a capacitor to minimize processing time and reduce fabrication cost (Cheng,[0002]).
Regarding claim 19, Coolbaugh as modified by Ikegami, Lee, and Cheng teaches : The method of claim 18.
Lee teaches : further comprising: patterning the second conductive layer to form a high-voltage sacrificial(Fig. 1, #190 forms #191 and #195) gate structure over the second high-voltage gate dielectric and to further form a logic sacrificial gate structure over the logic gate dielectric(Fig. 11, #144 forms #144a and #144b[0041]).
Claim 20 is/are rejected under 35 U.S.C. 103 as being anticipated by Coolbaugh et al, US 20110115005, hereafter ‘Coolbaugh’ in view of Ikegami, US 20060255439, hereafter ‘Ikegami’, in further view of Lee, US 20080006866, hereafter ‘Lee’, Cheng, US 20180254218, hereafter ‘Cheng’ and Ando et al, US 20180226417, hereafter ‘Ando’.
Regarding claim 20, Coolbaugh as modified by Ikegami, Lee, and Cheng discloses : The method of claim 19.
Coolbaugh as modified by Ikegami, Lee, and Cheng does not disclose : further comprising: removing the high-voltage sacrificial gate structure to form a high-voltage gate cavity; removing the logic sacrificial gate structure to form a logic gate cavity; forming a high-voltage gate structure within the high-voltage gate cavity; and forming a logic gate structure within the logic gate cavity.
However, in the same field of endeavor, Ando teaches : further comprising: removing the high-voltage sacrificial gate structure to form a high-voltage gate cavity; removing the logic sacrificial gate structure to form a logic gate cavity; forming a high-voltage gate structure within the high-voltage gate cavity; and forming a logic gate structure within the logic gate cavity(#30A, and #30b serve as a placeholder for a functional gate stack which is removed to form a functional gate stack [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Ando to Coolbaugh, Ikegami, Lee and Cheng to include sacrificial gates to be removed and replaced with functional gate stacks to control output current (Ando [0057]).
Claim 23 is/are rejected under 35 U.S.C. 103 as being anticipated by Coolbaugh et al, US 20110115005, hereafter ‘Coolbaugh’ in view of Ikegami, US 20060255439, hereafter ‘Ikegami’, in further view of Totani et al, US 20230127904, hereafter ‘Totani’.
Regarding claim 23, Coolbaugh as modified by Ikegami discloses : The method of claim 22.
Coolbaugh as modified by Ikegami does not disclose : wherein the second conductor comprises a curved upper surface continuously extending from directly over the first conductor to laterally outside of the first conductor.
However, in the same field of endeavor, Totani teaches : wherein the second conductor comprises a curved upper surface continuously extending from directly over the first conductor to laterally outside of the first conductor(Fig. 32a, dishing occurs during chemical mechanical planarization (CMP) process of conductive material).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Totani to Coolbaugh and Ikegami to have a dishing effect on a conductor because of CMP process to define a recess in a conductor (Totani [0277]).
Claim 24 is/are rejected under 35 U.S.C. 103 as being anticipated by Coolbaugh et al, US 20110115005, hereafter ‘Coolbaugh’ in view of Ikegami, US 20060255439, hereafter ‘Ikegami’ in further view of Wong et al, US 20230046455, hereafter ‘Wong’.
Regarding claim 24, Coolbaugh as modified by Ikegami discloses : The method of claim 21.
Coolbaugh teaches : wherein the second conductor comprises a first upper surface over the first conductor and a second upper surface laterally outside of the first conductor(Fig. 7, #140 of region #127 laterally outside #112 and another upper surface #140 directly over #112).
Coolbaugh as modified by Ikegami does not disclose : the first upper surface being vertically above the second upper surface.
However, in the same field of endeavor, Wong teaches : the first upper surface being vertically above the second upper surface(Fig. 1b, #118 shown to be a second conductive layer of a capacitor with an upper surface with two different heights #118a and #118b with #118a overlapping #114).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Wong to Coolbaugh and Ikegami to form a conductive layer with different heights to prevent electrical shorts (Wong [0034]).
Allowable Subject Matter
Claim 28, 29, and 30-35 allowed.
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : US 20220068915 - Capacitor and transistor concurrent formation.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897