Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-12) in the reply filed on 02/12/2026 is acknowledged. Applicant added new claims 21-28.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pat # 8,912,651 to Yu et al. (Yu).
Regarding independent claim 1, Yu discloses a semiconductor structure (Fig. 19), comprising:
a metallic member (18) disposed between a substrate (22) and a board (10 such as interposer);
a first solder (28) disposed between the substrate (22) and the metallic member (18); and
a second solder (12, Under the broadest reasonable interpretation consistent with the specification, the claimed “solder” is interpreted as a conductive material used to electrically and/or mechanically couple components. The prior art’s copper pad, which provides a conductive interface for electrical connection, reasonably reads on the claimed “solder,” as the claim does not explicitly limit the solder to a particular composition or melting functionality) disposed between the board (10) and the metallic member (18).
Regarding independent claim 10, Yu discloses a semiconductor structure (Fig. 19), comprising:
a conductive bump (the conductive bump in the middle of Fig. 19) disposed between a substrate (10) and a board (22);
an isolation member (30) disposed over the board (22) and surrounding the conductive bump (the conductive bump in the middle of Fig. 19) and the substrate (10);
a metallic member (18) disposed between the isolation member (30) and the conductive bump (the conductive bump in the middle of Fig. 19); and
a solder (28) disposed between the substrate (10) and the board (22) and configured to attach the metallic member (18) to the substrate (10) and the board (22).
Regarding independent claim 24, Yu discloses a package structure (Fig. 19) comprising:
a substrate (22);
a printed circuit board (10) attached to the substrate (22); and
a corner reinforcement structure (the combinations of 12,18,20 is considered to be a corner reinforcement structure) between the substrate (22) and the printed circuit board (10), wherein the corner reinforcement structure includes:
a first solder layer (28),
a second solder layer (12, Under the broadest reasonable interpretation consistent with the specification, the claimed “solder” is interpreted as a conductive material used to electrically and/or mechanically couple components. The prior art’s copper pad, which provides a conductive interface for electrical connection, reasonably reads on the claimed “solder,” as the claim does not explicitly limit the solder to a particular composition or melting functionality), and
a metal layer (18) disposed between the first solder layer (28) and the second solder layer (12), wherein the first solder layer (28) is between the substrate (22) and the metal layer (18) and the second solder layer (12) is between the printed circuit board (10) and the metal layer (18).
Claims 1-2, 4-10, 12, 21-26 and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2009/0146314 to Akaike et al. (Akaike).
Regarding independent claim 1, Akaike discloses a semiconductor structure (Fig. 7), comprising:
a metallic member (the combination of 92-1 or 91-1 or 151-1) disposed between a substrate (21) and a board (11);
a first solder (97) disposed between the substrate (21) and the metallic member (92-1 or 91-1 or 151-1); and
a second solder (14) disposed between the board (11) and the metallic member (92-1 or 91-1 or 151-1).
Regarding claim 2, Akaike discloses a third solder (23) extending between the first solder (97) and the second solder (14), wherein the third solder (23) surrounds the metallic member (partially surrounds 92-1 or 91-1 or 151-1).
Regarding claim 4, Akaike discloses an isolation member (27) disposed over the board (11) and surrounding the metallic member (92-1 or 91-1 or 151-1), the first solder (97), the second solder (14), the third solder (23), and the substrate (21), wherein the third solder (23) is disposed between the isolation member (27) and the metallic member (92-1 or 91-1 or 151-1).
Regarding claim 5, Akaike discloses wherein the substrate (21) includes a central portion and a peripheral portion, and the metallic member (92-1 or 91-1 or 151-1) is disposed at the peripheral portion (see Examiner’s Mark-up below).
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Regarding claim 6, Akaike discloses an isolation member (27) disposed over the board (11) and surrounding the metallic member (92-1 or 91-1 or 151-1), the first solder (97), the second solder (14), and the substrate (21).
Regarding claim 7, Akaike discloses wherein the isolation member (27) is in contact with the metallic member (92-1 or 91-1 or 151-1), the first solder (97), and the second solder (14).
Regarding claim 8, Akaike discloses a die (24 and ¶0079) disposed over the substrate (21), wherein the substrate (21) is disposed between the die (24) and the first solder (97).
Regarding claim 9, Akaike discloses a conductive pad (78) disposed between the substrate (21) and the first solder (97).
Regarding independent claim 10, Akaike discloses a semiconductor structure (Fig. 7), comprising:
a conductive bump (95) disposed between a substrate (11) and a board (21);
an isolation member (27) disposed over the board (21) and surrounding the conductive bump (95) and the substrate (11);
a metallic member (the combination of 92-1, 151-1, 91-1 is considered to be a metallic member) disposed between the isolation member (27) and the conductive bump (95); and
a solder (23) disposed between the substrate (11) and the board (21) and configured to attach the metallic member (92-1, 151-1, 91-1) to the substrate (11) and the board (21).
Regarding claim 12, Akaike discloses wherein the solder (23) surrounds the metallic member (92-1, 151-1, 91-1).
Regarding claim 21, Akaike discloses a first metal pad (16) disposed on the substrate (11), wherein the solder (23) is disposed between the first metal pad (16) and the metallic member (92-1, 151-1, 91-1); and
a second metal pad (17) disposed on the board (21), wherein the solder (23) is disposed between the second metal pad (17) and the metallic member (92-1, 151-1, 91-1).
Regarding claim 22, Akaike discloses wherein the metallic member (92-1, 151-1, 91-1) is disposed at a corner of the substrate (11) (see Examiner’s Mark-up below).
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Regarding claim 23, Akaike discloses wherein the metallic member (92-1, 151-1, 91-1) includes more than one metallic member segment (such as 151 or 91-1).
Regarding independent claim 24, Akaike discloses a package structure (Fig. 7) comprising:
a substrate (11);
a printed circuit board (21) attached to the substrate (11); and
a corner reinforcement structure (the combinations of 16,14, 141, 17,23 is considered to be a corner reinforcement structure) between the substrate (11) and the printed circuit board (21), wherein the corner reinforcement structure includes:
a first solder layer (14),
a second solder layer (23), and
a metal layer (combined 16 and 17 and 141) disposed between the first solder layer (14) and the second solder layer (23), wherein the first solder layer (14) is between the substrate (11) and the metal layer (combined 16 and 17 and 141) and the second solder layer (23) is between the printed circuit board (21) and the metal layer (combined 16 and 17 and 141).
Regarding claim 25, Akaike discloses wherein the metal layer (combined 16 and 17 and 141) is disposed at a corner of the substrate (11), and in a top view, the metal layer is rectangular-shaped (see Fig. 7: either parts of 16 or 17 or 141 is rectangular-shaped) (see Examiner’s Mark-up below).
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Regarding claim 26, Akaike discloses wherein the metal layer (combined 16 and 141) is disposed at a corner of the substrate, and in a top view, the metal layer is L-shaped (combined 16 and 17 and 141 is L-shaped) (see also Examiner’s Mark-up above from claim 25).
Regarding claim 28, Akaike discloses wherein the metal layer (combined 16, 141 and 17) is disposed at a corner of the substrate (see also Examiner’s Mark-up above from claim 25), and in a top view, the metal layer is C-shaped (combined 16, 141 and 17 is C-shaped).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2009/0146314 to Akaike et al. (Akaike) in view of US Pub # 2007/0000976 to Arana et al. (Arana).
Regarding claim 3, Akaike teaches all of the limitations of claim 2 from which this claim depends.
Akaike fails to explicitly discloses wherein the third solder is integral with the first solder and the second solder.
Arana teaches (Fig. 2a) wherein the third solder (a first side 26 of the solder preform 20) is integral with the first solder (a second side 26 of the solder preform 20) and the second solder (a third side 26 of the solder preform 20).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor structure of Akaike with the solder preform as taught by Arana so as to couple the seal ring portion to the bonding pad interconnect portion (¶0020).
Claims 11 and 27 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2009/0146314 to Akaike et al. (Akaike).
Regarding claim 11, Akaike discloses wherein a total height of the metallic member (the combination of 92-1, 151-1, 91-1) and the solder (23). Akaike further teaches a distance the substrate (11) and the board (21).
However, Akaike does not explicitly disclose that the total height of the metallic member and solder is “substantially the same as” the distance between the substrate and the board.
Nevertheless, the relative dimensions between the height of the metallic member and solder and the distance between the substrate and the board constitute a result-effective variable, as such dimensions directly affect the connection reliability, mechanical stability, and electrical performance.
It would have been obvious to one of ordinary skill in the art at the time of the invention to adjust the height of the metallic member and solder to be substantially equal to the distance between the substrate and the board in order to ensure proper contact, alignment, and structural integrity, since optimizing dimensional relationships between mating components is a routine design consideration.
The claimed relationship therefore represents no more than an obvious optimization of known parameters, absent a showing of criticality or unexpected results.
Regarding claim 27, Akaike discloses wherein the metal layer (combined 16, 141 and 17) is disposed at a corner of the substrate (see also Examiner’s Mark-up above from claim 25).
Akaike does not teach in a top view, the metal layer is triangular-shaped. However, the shape of the metal layer is a result-effective variable that affects (e.g., current distribution, stress concentration, or layout efficiency). Akaike teaches multiple alternative shapes, thereby suggesting that geometry may be selected based on design needs. It would have been obvious to optimize the shape, including selecting a triangular configuration, through routine experimentation to achieve desired performance characteristics.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 8,574,959 to Pendse; US Pat # 9,418,913 to Shim et al.; US Pat # 9,865556 to Pendse.
Pendse discloses a semiconductor structure (Fig. 17d) comprising, a bump 238 formed over contact pad 232 of semiconductor die 224, a semiconductor die 224 is positioned so that composite bump 238 is aligned with an interconnect site on conductive trace 256, a composite bump 238 can be aligned with a conductive pad or other interconnect site formed on substrate 254, the composite bump 238 is wider than conductive trace 256 and a non-fusible or non-collapsible portion 240 and fusible or collapsible portion 242 are formed on a PCB 254.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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