DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 16-20 in the reply filed on 1/12/2026 is acknowledged.
Furthermore, with the amendment of 1/12/2026, the applicant cancelled non-elected device claims 1-15 and added new method claims 20-35. Therefore, claims 16-35 are examiner with this action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. (20220254781).
Regarding Claim 16, in Figs, 3A, 3B, 5A-10D and in paragraphs 0015, 0016, 0017, 0040, 0045, 0090, 0091, 0094, 0096, 0099, 0105, 0114, 0124, 0140, 0144, 0164 and 0166, Song et al. discloses a method for forming a semiconductor device, comprising: forming a channel portion CH1/SP1/SP2/SP3 on a substrate 100 (Fig. 3A) the channel portion being spaced apart from the substrate; forming a gate dielectric GI (Fig. 3A) which includes an upper dielectric region (portion of GI that is on top of fin FST1) that covers the channel portion; forming a work-function
Regarding Claim 17, in paragraph 0048 and 0049, the gate dielectric GI further includes a lower dielectric region (bottom left and bottom right of fin FST1) that covers the substrate 100, the work-function layer MP1 is further formed over the lower dielectric region, and the first inner gate structure IGEa/IGE1/IGE2/IGE3 is formed between the lower dielectric region and the upper dielectric region (portion of the GI on top of fin FST1, see Fig. 3A)
Regarding Claim 18, an outer gate OGE structure which includes an outer work-function portion MP2 that covers the lower dielectric region, the first inner gate structure IGEa/IGE1/IGE2/IGE3 and the upper dielectric region, and a cap portion FMP that covers the outer work-function portion in a way that the cap portion is separated from the first inner gate structure by the outer work-function portion MP2, the outer work-function portion MP2 including a second work-function material different from the conductive material (i.e. metal carbide material as molybdenum/tantalum, see paragraphs 0087, 0091 and 0095)
Regarding Claim 19, the cap portion FMP includes silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbon nitride, silicon oxycarbon nitride, titanium nitride, tantalum nitride, or combinations thereof (see paragraph 0098).
Regarding Claim 20, the channel portion CH1/SP1/SP2/SP3 includes two channel parts CH1/SP1/SP2/SP3 spaced apart from each other, the upper dielectric region (portion of GI on top of fin FST) includes two upper dielectric parts surrounding the two channel parts, respectively, the work-function layer and the conductive layer are patterned into the first inner gate structure IGEaIGE1/IGE2/IGE3 which is located between the lower dielectric region and a lower one of the two upper dielectric parts, and a second inner gate structure which is located between the two upper dielectric parts, each of the first inner gate structure and the second inner gate structure including a conductive portion IGEa/IGE1/IGE2/IGE3 including the conductive material and two inner work-function portions MP1 which include the first work-function material which are respectively disposed at two opposite sides of the conductive portion, the outer work-function portion further covers the second inner gate structure IGEa/IGE1/IGE2/IGE3, and the cap portion FMP is further separated from the second inner gate structure by the outer work- function portion MP2.
Regarding Claim 21, in Figs 3A, 3B. 5A-10D and in paragraphs 0015, 0016, 0017, 0040, 0045, 0090, 0091, 0094, 0096, 0099, 0105, 0114, 0124, 0140, 0144, 0164 and 0166, Song et al. discloses a method for manufacturing a semiconductor device, comprising: forming two channel parts CH1/SP1/SP2/SP3 over a substrate 100, the two channel parts (SP1/SP2/SP3) being spaced apart from each other; depositing two gate dielectric parts GI respectively around the two channel parts; depositing a first work-function layer MP1 on the two gate dielectric parts, the first work- function layer including a first work-function material (metal nitride see paragraph 0091); depositing a conductive layer IGEa/IGE1/IGE2/IGE3 on the first work-function layer such that a space between the two channel parts is filled by the first work-function layer MP1 and the conductive layer IGEa/IGE1/IGE2/IGE3, the conductive layer including a conductive material that is different from the first work-function material (for example Tantalum/Molybdenum see paragraph 0087, 0091, 0095); and etching back the first work-function layer and the conductive layer so as to form an inner gate structure between the two channel parts (see Figs 16-18), the inner gate structure including a conductive portion IGEa/IGE1/IGE2/IGE3 including the conductive material (see paragraph 0087) , and two inner work-function portions MP1 which are respectively disposed at two opposite sides of the conductive portion and which include the first work-function material MP1 (see Figs 16-18, specifically the bottom left and bottom right portion of fin FST1).
Regarding Claim 22, the conductive material IGEa/IGE1/IGE2/IGE3 (see paragraph 0087, molybdenum/tantalum) has a sheet resistance less than a sheet resistance of the first work-function material MP1 (metal nitride, see paragraph 0091).
Regarding Claim 23, two gate dielectric parts GI are partially exposed from the inner gate structure IGEa/IGE1/IGE2/IGE3 (specifically see the sidewalls of IGEa/IGE1/IGE2/IGE3 in Fig. 3A).
Regarding Claim 24, depositing a second work-function layer MP2 on the two gate dielectric parts GI and the inner gate structure IGEa/IGE1/IGE2/IGE3, the second work-function layer including a second work-function material (metal carbide see paragraph 0095) that is different from the conductive material (tantalum/molybdenum see paragraph 0087); and depositing a cap layer FMP on the second work-function layer MP2, the second work-function layer and the cap layer together constituting an outer gate structure OGE (see Fig. 3A)
Regarding Claim 25, the first work-function material MP1 is the same as the second work-function material MP2 (see paragraph 0091).
Regarding Claim 26, cap layer FMP includes silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbon nitride, silicon oxycarbon nitride, titanium nitride, tantalum nitride, or combinations thereof, see paragraph 0098)
Regarding Claim 27, outer gate structure OGE has a thickness that is less than half of a thickness of the inner gate structure IGEa/IGE1/IGE2/IGE3 (see paragraphs 0093, 0157, 0163, 0164).
Regarding Claim 28, a ratio of a volume of the conductive portion IGEa/IGE1/IGE2/IGE3 to a total volume of the two inner work-function portions MP1 ranges from 5:100 to 100:100 (see paragraph 0093, 0157, 0163 and 0164)
Regarding Claim 29, the two inner work-function portions MP1 are respectively disposed proximate to and distal from the substrate (please see the bottom left and bottom right portions of fin FST in Fig. 3A).
Regarding Claim 30, depositing two source/drain portions SD1/SD2 on the substrate such that each of the two channel parts extends between the two source/drain portions (see paragraphs 0028, 0029, 0064, 0067, 0069, 0132 and 0141).
Regarding Claim 31, the two source/drain portions SD1/SD2 are spaced apart from each other in a first direction, the two channel parts CH1/CH1 are spaced apart from each other in a second direction which is different from the first direction and which is normal to an upper surface of the substrate 100, each of the two channel parts has two first side surfaces opposite to each other in a third direction different from the first direction and the second direction, and has a first length between the two first side surfaces, the first inner gate structure IGEa/IGEb has two second side surfaces opposite to each other in the third direction, and has a second length between the two second side surfaces thereof, and a difference between the first length and the second length ranges from 0 nm to 5 nm (see Fig.2D and paragraph 0077)
Regarding Claim 32, in Figs, 3A, 3B, 5A-10D and in paragraphs 0015, 0016, 0017, 0040, 0045, 0090, 0091, 0094, 0096, 0099, 0105, 0114, 0124, 0140, 0144, 0164 and 0166, Song et al. discloses a method for manufacturing a semiconductor device, comprising: forming a first channel portion CH1/CH2 over and spaced apart from a first region of a substrate 100; forming a second channel portion CH1/CH2 over and spaced apart from a second region of the substrate 100, the first region and the second region being spaced apart from each other (see Fig. 2D); depositing a first gate dielectric GI on the first channel portion and the first region of the substrate; depositing a second gate dielectric GI on the second channel portion and the second region of the substrate; depositing a first work-function layer MP1 on the first gate dielectric, the second gate dielectric, the first region of the substrate, and the second region of the substrate, the first work-function layer including a first work-function material (see paragraph 0091); depositing a conductive layer on the first work-function layer IGEa/IGE1/IGE2/IGE3, the conductive layer including a conductive material that is different from the first work-function material (see paragraph 0087, 0091 and 0095); removing a portion of the first work-function layer and a portion of the conductive layer which are disposed on the second region of the substrate so as to expose the second gate dielectric GI; and etching back another portion of first work-function layer and another portion of the conductive layer which remain on the first region of the substrate so as to form an inner gate structure IGEa/IG1/IG2/IG3 which is disposed between the first channel portion CH1 and the first region of the substrate, the inner gate structure including two inner work-function portions MP1/MP2 and a conductive portion is sandwiched between the two inner work-function portions, the two inner work-function portions MP1/MP2 including the first work-function material MP1, the conductive portion IGEa/IGE1/IGE2/IGE3 including the conductive material (see Fig 3A, paragraphs 0091-0093, 0098, 0099 and 0160).
Regarding Claim 33, depositing a second work-function layer MP2 on the first gate dielectric GI, the second gate dielectric and the inner gate structure, the second work-function layer including a second work- function material that is different from the conductive material (see paragraphs 0087 and 0095); depositing a cap layer FMP on the second work-function layer; and removing a portion of the second work-function layer and a portion of the cap layer which are disposed on the second region of the substrate so as to expose the second gate dielectric GI, wherein another portion of the second work-function layer MP2 and another portion of the cap layer FMP which remain on the first region of the substrate together constitute an outer gate structure OGE which is disposed on the first gate dielectric GI and the inner gate structure IGEa/IGE1/IGE2/IGE3 (see Fig. 3A).
Regarding Claim 34, depositing a third work-function layer on the outer gate structure and the second gate dielectric, the third work-function layer including a third work-function material that is different from the first work-function material and the second work-function material (see paragraph 0106)
Regarding Claim 35, the outer gate structure OGE has a thickness less than a thickness of the inner gate structure IGEa/IGE1/IGE2/IGE3 (see paragraphs 0093, 0157, 0163, 0164)
Cited Art that is NOT Relied Upon
Examiner is including Matagne 20260013203 (Fig. 2, paragraph 0011, 0042, 0056, 0074 and 0075) as pertinent prior art that is NOT relied upon on this rejection but that does disclose GAA device with workfunction mismatch/difference between the inner and outer gate electrodes
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 3/5/2026