DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 07/21/2026, with respect to the rejection of claims 1-4, 12-14 and 21-22 under 35 U.S.C. 112(b) have been fully considered and are persuasive. The rejection of claims 1-4, 12-14 and 21-22 has been withdrawn.
Applicant's arguments filed 07/21/2026 with respect to the rejection of claims 1-4, 12-14 and 21-22 under 35 U.S.C. 102 have been fully considered but they are not persuasive. The broadest reasonable interpretation of the claimed “conductor structures” and “conductive line” does read upon the prior art contacts and shunt, as these are conductive metallization components. Also, while the contacts taught by Inukai are symmetrical, they have a length and a width and therefore “extend” in both directions, even if one dimension is shorter than the other. The same argument can be made for the term “metallization layer” as this is a very broad term as well and the components disclosed in Fig.19 of Inukai occupy three separate horizontal layers at different vertical heights. While it is clearly true that Figure 19 of Inukai is different from the invention as shown in the drawings and written description, the claimed language is broad enough for a proper rejection to be made.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 12-13 and 21-23 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Inukai (US-20240098983-A1).
Regarding claim 1, Inukai teaches a memory device (Fig.19; ¶0135), comprising:
a substrate (Fig.8 SUB; ¶0056);
a plurality of metallization layers (Fig.8; ¶0069 depicts metallization layers) disposed over the substrate (SUB);
a plurality of memory cells (Fig.2 MC; ¶0052), each of the plurality of memory cells (MC) including a transistor (Fig.2 CT; ¶0058) and a capacitor (Fig.2 CC; ¶0058); and
a bit line (Fig.19 BL4; ¶0137) coupled to a corresponding set of the plurality of memory cells (MC);
wherein the bit line (BL4) comprises at least a first conductor structure (Fig.19 43; ¶0137) and a second conductor structure (Fig.19 53; ¶0137) that extend along a first lateral direction (Fig.19 Y direction) and are disposed in a first one (bottom layer) of the plurality of metallization layers (Fig.8; ¶0069);
wherein the first conductor structure (43) and the second conductor structure (53) are physically spaced from each other, but are electrically coupled to each other through conductor structures (Fig.19 CP3 and SH2; ¶0137) disposed in one or more other ones of the plurality of metallization layers (lowest vertical layer in Fig.19), the conductor structures (43 and 53) comprising:
a third conductor structure (Fig.19 CP3 top; ¶0137) disposed in a second one of the plurality of metallization layers (middle horizontal layer of Fig.19) and extending along a second lateral direction (Fig.19 X direction) perpendicular to the first lateral direction (Y direction);
a fourth conductive line (Fig.19 SH2; ¶0137) disposed in a third one of the plurality of metallization layers (top horizontal layer of Fig.19) and extending along the first lateral direction (Y direction); and
a fifth conductor structure (Fig.19 CP3 bottom; ¶0137) disposed in the second one of the plurality of metallization layers (middle horizontal layer of Fig.19) and extending along the second lateral direction (X direction).
Regarding claim 2, Inukai teaches the memory device of claim 1, wherein the transistor (CT) and the capacitor (CC) of each of the plurality of memory cells (MC) are formed across multiple ones of the plurality of metallization layers (see Fig.2, the vertical displacement indicated different metallization layers).
Regarding claim 3, Inukai teaches the memory device of claim 1, wherein the first conductor structure (43) and a projection of the second conductor structure (53) are physically spaced from each other along a second lateral direction (Fig.19 X direction) perpendicular to the first lateral direction (Y direction).
Regarding claim 12, Inukai teaches a memory device (Fig.19; ¶0135), comprising:
a plurality of memory cells (Fig.2 MC; ¶0052) disposed across one or more of a plurality of metallization layers (Fig.8; ¶0069 depicts metallization layers) formed over a substrate (Fig.8 SUB; ¶0056); and
a bit line (Fig.19 BL4; ¶0137) operatively coupled to a corresponding set of the plurality of memory cells (MC);
wherein the bit line (BL4) consists of at least a first conductor structure (Fig.19 43; ¶0137) and a second conductor structure (Fig.19 53; ¶0137) that are disposed in a first one of the plurality of metallization layers (lower vertical layer of Fig.19), the first conductor structure (43) and the second conductor structure (53) both extending along a first lateral direction (Fig.19 Y direction);
wherein the first conductor structure (43) and the second conductor structure (53) are physically spaced from each other, but are electrically coupled to each other through one or more other conductor structures (Fig.19 CP3 and SH2; ¶0137), the one or more other conductor structures (CP3 and SH2) comprising:
a third conductor structure (Fig.19 CP3 top; ¶0137) disposed in a second one of the plurality of metallization layers (middle horizontal layer of Fig.19) and extending along a second lateral direction (Fig.19 X direction) perpendicular to the first lateral direction (Y direction);
a fourth conductive line (Fig.19 SH2; ¶0137) disposed in a third one of the plurality of metallization layers (top horizontal layer of Fig.19) and extending along the first lateral direction (Y direction); and
a fifth conductor structure (Fig.19 CP3 bottom; ¶0137) disposed in the second one of the plurality of metallization layers (middle horizontal layer of Fig.19) and extending along the second lateral direction (X direction).
Regarding claim 13, Inukai teaches the memory device of claim 12, wherein the first conductor structure (43) and the second conductor structure (53) both extend along a first lateral direction (Fig.19 Y direction), and wherein the first conductor structure (43) and a projection of the second conductor structure (53) are physically spaced from each other along a second lateral direction (Fig.19 X direction) perpendicular to the first lateral direction (Y direction).
Regarding claim 21, Inukai teaches a memory device (Fig.19; ¶0135), comprising:
a plurality of memory cells (Fig.2 MC; ¶0052) disposed across one or more of a plurality of metallization layers (Fig.8; ¶0069 depicts metallization layers); and
a bit line (Fig.19 BL4; ¶0137) coupled to a corresponding set of the plurality of memory cells (MC), the bit line (BL4) comprising a first portion (Fig.19 43; ¶0137) and a second portion (Fig.19 53; ¶0137) physically spaced from each other along a second lateral direction (Fig.19 X-direction), and extending along a first lateral direction (Fig.19 Y-direction);
wherein the first portion (43) of the bit line (BL4) is electrically coupled to a first conductor structure (Fig.19 CP3 top; ¶0137) and the second portion (53) of the bit line (BL4) is electrically coupled to a second conductor structure (Fig.19 CP3 bottom; ¶0137), the first conductor structure (CP3 top) and the second conductor (CP3 bottom) structure extend along the second lateral direction (X-direction) and are disposed in a first one of the plurality of metallization layers (middle horizontal layer of Fig.19);
wherein the first conductor structure (CP3 top) and the second conductor structure (CP3 bottom) are electrically coupled to each other through a third conductor structure (Fig.19 SH2; ¶0137) disposed in a second one of the plurality of metallization layers (top horizontal layer of Fig.19) to electrically couple the first portion (43) and the second portion (53) of the bit line (BL4), the third conductor structure (SH2) extending along the first lateral direction (Y-direction);
wherein the first portion (43) and the second portion (53) of the bit line (BL4) are disposed in a third one of the plurality of metallization layers (bottom horizontal layer of Fig.19) different from the first one (middle horizontal layer of Fig.19) and the second one (top horizontal layer of Fig.19) of the plurality of metallization layers.
Regarding claim 22, Inukai teaches the memory device of claim 21, wherein each of the plurality of memory cells (MC) comprises a transistor (Fig.2 CT; ¶0058) and a capacitor (Fig.2 CC; ¶0058) formed across multiple ones of the plurality of metallization layers (see Fig.2, the vertical displacement indicated different metallization layers).
Regarding claim 23, Inukai teaches the memory device of claim 1, further comprising a second bit line (Fig.19 BL3; ¶0137) coupled to a second corresponding set of the plurality of memory cells, the second bit line (BL3) comprising at least a sixth conductor structure (Fig.19 42; ¶0137) and a seventh conductor structure (Fig.19 52; ¶0137) that extend along the first lateral direction (direction Y) and are disposed in the first one of the plurality of metallization layers (bottom metallization layer of Fig.19), wherein a portion of the bit line (BL4) and a portion of the second bit line (BL3) overlap each other when viewed from a direction perpendicular to the first one of the plurality of metallization layers (both bit lines cross over from the top view of Fig.19).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inukai.
Regarding claim 24, Inukai teaches the memory device of claim 21.
Inukai does not explicitly teach wherein the first conductor structure is electrically coupled to the third conductor structure through a first via structure, and the second conductor structure is electrically coupled to the third conductor structure through a second via structure.
This is because the first and second conductor structures (CP3) of Inukai are themselves via structures, making the invention as claimed in claim 24 an obvious variant of the embodiment disclosed in Figure 19 of Inukai. Accordingly, claim 24 is not patentable over the prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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