DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-12, 14-16, & 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Laws (US 20040222494).
Regarding claim 1, Laws discloses that an integrated circuit (IC) structure, comprising:
a semiconductor substrate (para. 0031);
a bottom electrode 36 routing over the semiconductor substrate (para. 0031 & Fig. 5);
a capacitor structure over the bottom electrode routing , the capacitor structure comprising:
a bottom metal layer 29;
a middle metal layer 16 above the bottom metal layer; and
a top metal layer 15 above the middle metal layer, wherein when viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction, wherein the top metal layer structurally spans across the first direction from a first one of the opposite square wave-shaped edges to a second one of the opposite square wave-shaped edges to form a single metal structure (Fig. 3a, 4ab, 5 & 6);
a top electrode routing (a via 25 connected an element 27) over the capacitor structure;
a first metal via extending from the bottom electrode routing to the top electrode routing, the first metal via contacting the top and bottom metal layers and spaced apart from the middle metal layer (Fig. 5); and
a second metal via extending from the bottom electrode routing to the top electrode routing, the second metal via contacting the middle metal layer and spaced apart from the bottom and top metal layers (Fig. 5).
Reclaim 3, Laws discloses that the middle metal layer 16 has opposite straight edges, a first one of the straight edges of the top metal layer is laterally set [[beck]]back from a first one of the straight edges of the middle metal layer, and a second one of the straight edges of the top metal layer is laterally set back from a second one of the straight edges of the middle metal layer (Fig. 3a, 4ab, 5 & 6).
Reclaim 4, Laws discloses that the middle metal layer has opposite straight edges, a first distance between the straight edges of the middle metal layer is greater than a second distance between the straight edges of the top metal layer (Fig. 3a, 4ab, 5 & 6).
Reclaim 5, Laws discloses that the bottom metal layer 29 of the capacitor structure has opposite straight edges and opposite square wave-shaped edges extending between the straight edges of the bottom metal layer (Fig. 3a, 4ab, 5 & 6).
Reclaim 6, Laws discloses that the middle metal layer 16 of the capacitor structure has opposite straight edges and opposite square wave-shaped edges extending between the opposite straight edges of the middle metal layer (Fig. 3a, 4ab, 5 & 6).
Reclaim 7, Laws discloses that the square wave-shaped edges of the middle metal layer overlap with the square wave-shaped edges of the top metal layer (Fig. 3a, 4ab, 5 & 6).
Reclaim 8, Laws discloses that the first metal via has a square top- view pattern, a rectangular top-view pattern, a circle top-view pattern, or an elliptical top-view pattern (Fig. 3a, 4ab, 5 & 6).
Reclaim 9, Laws discloses that a first metal layer above the top metal layer, the first metal layer being electrically connected to the middle metal layer, and electrically isolated from the bottom and top metal layers (Fig. 3a, 4ab, 5 & 6).
Reclaim 10, Laws discloses that a second metal layer above the first metal layer, the second metal layer being electrically connected to the bottom and top metal layers, and electrically isolated from the middle and first metal layers (Fig. 3a, 4ab, 5 & 6).
Regarding claim 11, Laws discloses that an integrated circuit (IC) structure, comprising:
a semiconductor substrate (para. 0031);
a first electrode routing 36 or 29 over the semiconductor substrate;
a second electrode routing over the first electrode routing 29; and
a capacitor structure connected between the first and second electrode routings, the capacitor structure comprising:
a first metal plate 16 serving to receive a first voltage potential and having opposite linear edges extending along a first direction; and
a second metal plate 15 over the first metal plate, the second metal plate 15 serving to receive a second voltage potential different than the first voltage potential, the second metal plate having opposite linear edges extending along the first direction, a first distance between the opposite linear edges of the first metal plate being different than a second distance between the opposite linear edges of the second metal plate, wherein the opposite linear edges of the second metal plate are laterally set back from the opposite linear edges of the first metal plate without intersecting the opposite linear edges of the first metal plate (Fig. 3a, 4ab, 5 & 6).
Reclaim 12, Laws discloses that the first distance between the linear edges of the first metal plate is greater than the second distance between the linear edges of the second metal plate (Fig. 3a, 4ab, 5 & 6).
Reclaim 14, Laws discloses that the capacitor structure further comprises a third metal plate 27 over the second metal plate 15, and the third metal plate serves to receive the first voltage potential (Fig. 4ab & 5).
Reclaim 15, Laws discloses that the first metal plate has a first non-linear edge connecting the linear edges of the first metal plate, the first non-linear edge has a plurality of notches arranged along a second direction perpendicular to the first direction (Fig. 6).
Reclaim 16, Laws discloses that the second metal plate has a non- linear edge connecting the linear edges of the second metal plate, the non-linear edge has a plurality of notches arranged along a second direction perpendicular to the first direction (Fig. 5 & 6).
Reclaim 21 Laws discloses that the first metal plate is a single metal structure, the first metal plate has a second non-linear edge connecting the linear edges of the first metal plate, the second non-linear edge has a plurality of notches arranged along a second direction perpendicular to the first direction (Fig. 4ab, 5, & 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 & 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Laws (US 20040222494).
Reclaim 2, Law discloses that a distance between the first metal via and one of the straight edges of the top metal layer is in a range in the plan view.
Laws fails to specify that a distance between the first metal via and one of the straight edges of the top metal layer is in a range from about 0.1 to 1 times a maximum dimension of the first metal via in the plan view.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain distance between the first metal via and one of the straight edges of the top metal layer, because it would have been to obtain a certain distance between the first metal via and one of the straight edges of the top metal layer to achieve enhance optimizing or adjusting capacitance between metal layers.
Regarding claim 17, Laws discloses that an integrated circuit (IC) structure, comprising:
a substrate (para. 0031);
a first electrode 29 routing over the substrate;
a lower metal plate 16 over the first electrode routing 29, the lower metal plate having a first through hole therein (Fig. 4ab or 6), wherein the first through hole is a closed-perimeter opening laterally enclosed by the lower metal plate;
a middle metal plate 15 over the lower metal plate 16, the middle metal plate 15 having a second through hole therein and opposite straight edges, wherein the second through hole is a closed- perimeter opening laterally enclosed by the middle metal plate 15, and wherein from a cross- sectional view, the middle metal plate has a larger width than the lower metal plate, and the second through hole non-overlaps the first through hole (Fig. 4ab & 6);
a first via 22 extending through the lower metal plate and the middle metal plate 15, wherein the first via is in contact with the lower metal plate, and the first via is further in the second through hole of the middle metal plate and spaced apart from the middle metal plate ; and a second via extending through the lower metal plate and the middle metal plate, wherein the second via is in contact with the middle metal plate, and the second via is further in the first through hole of the lower metal plate and spaced apart from the lower metal plate in a plan view, the second via has a distance to one of the straight edges of the middle metal plate
Laws fails to specify that in a plan view, the second via has a distance to one of the straight edges of the middle metal plate in a range from about 0.1 to 1 times a maximum dimension of the second via.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain distance of via to a plate, because it would have been to obtain a certain distance of via to a plate to achieve optimizing or controlling capacitance by distance.
Reclaim 18, Laws discloses that the lower metal plate has a square wave-shaped edge from the plan view (Fig. 4ab, 5, & 6).
Reclaim 19, Laws discloses that the middle metal plate has a square wave-shaped edge extending between the opposite straight edges from the plan view (Fig. 4ab, 5, & 6)
Reclaim 20, Laws discloses that an upper metal plate over the middle metal plate, wherein from the cross-sectional view, the upper metal plate has a smaller width than the middle metal plate (Fig. 4ab, 5, & 6).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/SU C KIM/ Primary Examiner, Art Unit 2899
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