Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7, 10, 21, and 25-30 are rejected under 35 U.S.C. 103 as being unpatentable over Young (US 20210035870 A1) in view of Xie (US 20240421156 A1).
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Regarding claim 1, Xie discloses a method, comprising: forming first semiconductive sheets (Fig. 3A, left portion of 124) over a substrate (102) and arranged in a vertical direction (Shown arranged in Z direction), second semiconductive sheets (left portion of 126) over the substrate and arranged in the vertical direction (Shown), third semiconductive sheets (See attached figure; right portion of 124) over the substrate and arranged in the vertical direction (Shown), and fourth semiconductive sheets (right portion of 126) over the substrate and arranged in the vertical direction (Shown); forming a first source/drain region (See attached figure) between the first semiconductive sheets and the second semiconductive sheets (Shown matching Applicant's figures 17A-B), and a second source/drain region (See attached
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figure) between the third semiconductive sheets and the fourth semiconductive sheets (Shown matching Applicant's figures 17A-B); forming a first gate (See attached
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figure; 134) around each of the first semiconductive sheets (Fig. 4A shows gate structures substantially matching Applicant's figures 17A-B), a second gate around each of the second semiconductive sheets, a third gate around each of the third semiconductive sheets, and a fourth gate around each of the fourth semiconductive sheets (See attached figure), wherein the first and second gates has a first gate pitch therebetween, the third and fourth gates has a second gate pitch therebetween, and the second gate pitch is greater than the first gate pitch (Fig. 4A shows pitch between first gate and second gate being larger than pitch between third gate and fourth gate); and forming first spacers (Spacers 130 corresponding to the region containing the first and second semiconductive sheets) interleaving with the first semiconductive sheets (Fig. 4A shows spacer placement matching Applicant’s figures 17A-B) and between the first gate and the first source/drain region (Fig. 4A shows spacers substantially matching Applicant's figures 17A-B), and second spacers (spacers 130 corresponding to the region containing the third and fourth semiconductive sheets) interleaving with the third semiconductive sheets and between the third gate and the second source/drain region (Fig. 4A shows spacers substantially matching Applicant's figures 17A-B), wherein the first spacers each has a first lateral dimension in a lengthwise direction (Width of first spacer in X direction) of one of the first semiconductive sheets, the second spacers each has a second lateral dimension om a lengthwise direction (Width of second spacer in X direction). However, Xie does not disclose the second lateral dimension being greater than the first lateral dimension.
On the other hand, Young discloses the second lateral dimension is greater than the first lateral dimension (Fig. 16, first lateral dimension 340B of first spacers 206B and second lateral dimension 340A of second spacers 206A; para. 52 "the inner spacer [206A] has a lateral width 340A that may be equal to or greater than the lateral width 340B of inner spacer 206B"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Xie according to the teachings of Xie such that the lateral dimension of the second spacers would be greater than the lateral dimension of the first spacers in order to tune the capacitance of the different regions of the device (Young, para. 49 “The materials and the lateral widths of the inner spacers may be tuned to achieve overall balanced capacitance of the nano-sheet-based CMOS”).
Regarding claim 3, Young discloses wherein a ratio of the second lateral dimension of the second spacers to the first lateral dimension of the first spacers is greater than about 1.05 (Para. 52 "a ratio of the lateral width 340A to the lateral width 340B may be about 14 to 1.1").
Regarding claim 4, Xie discloses wherein the first, second, third, and fourth gates each comprises a gate dielectric layer (Para. 35 "The gate includes a gate dielectric over the channel") and a gate electrode layer over the gate dielectric layer (Para. 35 "The gate includes… a gate conductor over the gate dielectric"), and the gate dielectric layer of the first gate, the gate dielectric layer of the second gate, the gate dielectric layer of the third gate, the gate dielectric layer of the fourth gate have a same thickness as each other (Fig. 4A shows all gate structures being substantially identical).
Regarding claim 5, Xie discloses wherein the gate electrode layer of the first gate and the gate electrode layer of the second gate have a first distance therebetween (Fig. 5a; distance between first and second gates, each comprising a gate electrode), the gate electrode layer of the third gate and the gate electrode layer of the fourth gate have a second distance therebetween (Fig. 5A; distance between third and fourth gates, each comprising a gate electrode), and the second distance is greater than the first distance (Fig. 5A shows the distance between third and fourth gates being greater than the distance between first and second gates, therefore the distance between third and fourth gate electrodes is greater than the distance between first and second gate electrodes).
Regarding claim 7, Xie discloses wherein the gate electrode layer of the first gate has a first gate length (Fig. 20, X direction length of 248A), the gate electrode layer of the third gate has a second gate length (Z direction length of 248B), and the second gate length is longer than the first gate length (Shown in Fig. 20).
Regarding claim 10, Xie discloses wherein the first and second semiconductive sheets, the first and second gates, and the first source/drain region are of a core device (Fig. 5A shows the first and second semiconductive sheets, gates and source/drain regions being part of the core device), and the third and fourth semiconductive sheets, the third and fourth gates, and the second source/drain region are of a device for a capacitor or being of an e-fuse or an analog circuit (Fig. 5A shows the third and fourth semiconductive sheets, gates and source/drain regions comprising GAA transistors, and therefore being part of an analog circuit).
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Regarding claim 21, Xie discloses a method, comprising: forming first semiconductive sheets (Fig. 3A, left portion of 124) over a substrate (102) and arranged in a vertical direction (Shown arranged in Z direction), second semiconductive sheets (left portion of 126) over the substrate and arranged in the vertical direction (Shown), third semiconductive sheets (See attached figure; right portion of 124) over the substrate and arranged in the vertical direction (Shown), and fourth semiconductive sheets (right portion of 126) over the substrate and arranged in the vertical direction (Shown); forming a first source/drain region (See attached figure) between the first semiconductive sheets and the second semiconductive sheets (Shown matching Applicant's figures 17A-B), and a second source/drain region (See attached figure) between the third semiconductive sheets and the fourth semiconductive sheets (Shown matching Applicant's figures 17A-B); forming a first gate (See attached figure; 134) around each of the first semiconductive sheets (Fig. 4A shows gate structures substantially matching Applicant's figures 17A-B), a second gate around each of the second semiconductive sheets, a third gate around each of the third semiconductive sheets, and a fourth gate around each of the fourth semiconductive sheets (See attached figure), wherein each of the first, second, third, and fourth gates comprises a gate dielectric layer (Para. 35 "The gate includes a gate dielectric over the channel") and a gate electrode layer over the gate dielectric layer (Para. 35 "The gate includes… a gate conductor over the gate dielectric"), the gate electrode layer of the first gate and the gate electrode layer of the second gate have a first distance therebetween (Fig. 5A; distance between first and second gates, each comprising a gate electrode), the gate electrode layer of the third gate and the gate electrode layer of the fourth gate have a second distance therebetween (Fig. 5A; distance between third and fourth gates, each comprising a gate electrode), the second distance is greater than the first distance (Fig. 5A shows the distance between third and fourth gates being greater than the distance between first and second gates, therefore the distance between third and fourth gate electrodes is greater than the distance between first and second gate electrodes), and forming first spacers (Spacers 130 corresponding to the region containing the first and second semiconductive sheets) interleaving with the first semiconductive sheets (Fig. 4A shows spacer placement matching Applicant's figures 17A-B) and between the first gate and the first source/drain region (Fig. 4A shows spacers substantially matching Applicant's figures 17A-B), and second spacers (spacers 130 corresponding to the region containing the third and fourth semiconductive sheets) interleaving with the third semiconductive sheets and between the third gate and the second source/drain region (Fig. 4A shows spacers substantially matching Applicant's figures 17A-B). However, Xie does not disclose the gate electrode layer of the first gate having a first gate length, and the gate electrode layer of the third gate having a second gate length greater than the first gate length.
On the other hand, Young discloses the gate electrode layer of the first gate has a first gate length (Fig. 20, X direction length of 248A), and the gate electrode layer of the third gate has a second gate length (Z direction length of 248B) greater than the first gate length (Shown in Fig. 20). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Xie according to the teachings of Young such that the gate electrode layer of the first gate would have a first gate length, and the gate electrode layer of the second gate would have a second gate length greater than the first gate length in order to improve integration density by reducing the gate width.
Regarding claim 25, Xie discloses further comprising: forming a first dielectric layer (Fig. 2A, left portion of 122 corresponding to the region containing the first and second semiconductive sheets; para. 55 "122 may be formed of a dielectric material") and a second dielectric layer (Right portion of 122 corresponding to the region containing the third and fourth semiconductive sheets) over the substrate (Shown) before forming the first source/drain region and the second source/drain region (Figs. 2A-4A show dielectric layers being formed in fig. 2A while source/drain regions are formed in fig. 4A), wherein the first source/drain region is formed over the first dielectric layer, the second source/drain region is formed over the second dielectric layer, and the second dielectric layer has a greater lateral dimension than the first dielectric layer (Shown).
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Regarding claim 26, Xie discloses a method, comprising: forming first semiconductive sheets (Fig. 3A, left portion of 124) over a substrate (102) and arranged in a vertical direction (Shown arranged in Z direction), second semiconductive sheets (left portion of 126) over the substrate and arranged in the vertical direction (Shown), third semiconductive sheets (See attached figure; right portion of 124) over the substrate and arranged in the vertical direction (Shown), and fourth semiconductive sheets (right portion of 126) over the substrate and arranged in the vertical direction (Shown); forming a first source/drain
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region (See attached figure) between the first semiconductive sheets and the second semiconductive sheets (Shown matching Applicant's figures 17A-B), and a second source/drain region (See attached figure) between the third semiconductive sheets and the fourth semiconductive sheets (Shown matching Applicant's figures 17A-B), wherein the first source/drain region has a first lateral dimension in a lengthwise direction (Length of first source/drain region in X direction) of one of the first semiconductive sheets, the second source/drain region has a second lateral dimension (Length of second source/drain region in Y direction) in a lengthwise direction of one of the third semiconductive sheets, and the second lateral dimension is greater than the first lateral dimension (Shown); forming a
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first gate (See attached figure; 134) around each of the first semiconductive sheets (Fig. 4A shows gate structures substantially matching Applicant's figures 17A-B), a second gate around each of the second semiconductive sheets, a third gate around each of the third semiconductive sheets, and a fourth gate around each of the fourth semiconductive sheets (See attached figure), and forming first spacers (Spacers 130 corresponding to the region containing the first and second semiconductive sheets) interleaving with the first semiconductive sheets (Fig. 4A shows spacer placement matching Applicant's figures 17A-B) and between the first gate and the first source/drain region (Fig. 4A shows spacers substantially matching Applicant's figures 17A-B), and second spacers (spacers 130 corresponding to the region containing the third and fourth semiconductive sheets) interleaving with the third semiconductive sheets and between the third gate and the second source/drain region (Fig. 4A shows spacers substantially matching Applicant's figures 17A-B).
Regarding claim 27, Xie discloses wherein the first gate and the second gate have a first gate pitch therebetween, the third gate and the fourth gate have a second gate pitch therebetween, and the second gate pitch is greater than the first gate pitch (Fig. 4A shows pitch between first gate and second gate being larger than pitch between third gate and fourth gate).
Regarding claim 28, Xie discloses wherein the first semiconductive sheets and the second semiconductive sheets are in a first circuit region (Corresponds to region containing first and second semiconductive sheets), the third semiconductive sheets and the fourth semiconductive sheets are in a second circuit region (Corresponds to region containing third and fourth semiconductive sheets), and the second circuit region has a greater width than the first circuit region (Shown).
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Regarding claim 29, Xie discloses wherein the first semiconductive sheets and the second semiconductive sheets are in a first circuit region, and the third semiconductive sheets and the fourth semiconductive sheets are in a second circuit region different from the first circuit region (See attached figure).
Regarding claim 30, Xie discloses wherein the first circuit region is a core device region (Fig. 5A shows the first circuit region being part of the core device), and the second circuit region is a capacitor region, an e-fuse region, or an analog circuit region (Fig. 5A shows the second circuit region being comprising GAA transistors, and therefore being part of an analog circuit).
Allowable Subject Matter
Claims 2, 6, 8-9, and 22-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art of record fails to disclose wherein a gate pitch ratio of the second gate pitch to the first gate pitch is greater than about 1.1.
Regarding claim 6, the prior art of record fails to disclose wherein a ratio of the second distance to the first distance is greater than about 1.1.
Regarding claim 8, the prior art of record fails to disclose wherein a gate length ratio of the second gate length to the first gate length is greater than about 1.1.
Regarding claim 9, the prior art of record fails to disclose wherein the first gate length is in a range from about 8-20 nm, and the second gate length is in a range from about 8-16 nm.
Regarding claim 22, the prior art of record fails to disclose wherein the first gate comprises a first top spacer over the first semiconductive sheets and on a sidewall of the first gate, the third gate comprises a second top spacer over the third semiconductive sheets and on a sidewall of the third gate, and the second top spacer has a greater thickness than the first top spacer. Specifically, the prior art does not disclose the second top spacer having a greater thickness than the first top spacer.
Regarding claim 23, the prior art of record fails to disclose wherein the second top spacer is thicker than the first top spacer by about 0.5 nm to about 5 nm.
For this reason, claim 24 would also be allowable if claim 23 were rewritten in independent form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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