DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1-7, and 9-16 filed on 9/19/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 8, has been considered. New Claim(s) 21-23 have been considered and entered. Claim(s) 17-20 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 6-7, filed 07/06/2026, with respect to the rejection(s) of claim(s) 1-7, and 10-15 under 35 U.S.C. 102(a)(1) and claim(s) 8-9, and 16 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of SATO.
Regarding Claim 1. Applicant argues (see Remarks, page 6) that the cited references, alone or in combination, do not disclose or suggest the amended features, recites, “a power module comprising: a second substrate having a first surface…including a dielectric material…partially embedded…plurality of semiconductor dies, and a second conductive member…portion disposed between the first…second conductive member, the first conductive member…portion exposed through the second surface.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of SATO teaches a semiconductor module comprising; a package substrate including a dielectric film between the conductive films and are connected to the semiconductor chips or dies.
Regarding Claims 2-16, and 21-23: The independent Claim(s) 12, and dependent claims 2-11, 13-16, and 21-23 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 9-15, and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chia-Yen Lee et al, (hereinafter LEE), US 20170317015 A1, in view of Nobuyuki Sato, (hereinafter SATO), US 20050167849 A1.
Regarding Claim 1, LEE teaches a power module (Fig. 10, 7, power module package) comprising:
a first substrate (Fig. 11A, 20, patterned insulation metal substrate includes a carrier, 22, an insulation layer, 24, and a conductive layer, 26, [0034]);
a plurality of semiconductor dies (Fig. 11A, 30/40, semiconductor power chip) coupled to the first substrate (Fig. 11A, 20 includes a carrier, 22, an insulation layer, 24, and a conductive layer, 26, [0034]); and
LEE does not explicitly disclose a power module comprising: a second substrate having a first surface and a second surface, the first surface being coupled to the plurality of semiconductor dies, the second substrate including a dielectric material, a first conductive member at least partially embedded into the second substrate and connected to the plurality of semiconductor dies, and a second conductive member at least partially embedded into the second substrate and connected to the plurality of semiconductor dies, the dielectric material including a portion disposed between the first conductive member and the second conductive member, the first conductive member including a portion exposed through the second surface, the second conductive member including a portion exposed through the second surface.
SATO teaches a power module (Fig. 9, 81, planarized semiconductor module) comprising:
a second substrate (Fig. 9, 3, package substrate) having a first surface (annotated Figure 9) and a second surface (annotated Figure 9), the first surface (annotated Figure 9) being coupled to the plurality of semiconductor dies (Fig. 9, 9/5, driver IC chip/power MOS chip), the second substrate (Fig. 9, 3, package substrate) including a dielectric material (Fig. 9, 35, dielectric film), a first conductive member (Fig. 9, 37, conductive film) at least partially embedded (annotated Figure 9) into the second substrate (Fig. 9, 3, package substrate) and connected to the plurality of semiconductor dies (Fig. 9, 9/5, driver IC chip/power MOS chip), and a second conductive member (Fig. 9, 37, conductive film) at least partially embedded (annotated Figure 9) into the second substrate (Fig. 9, 3, package substrate) and connected to the plurality of semiconductor dies (Fig. 9, 9/5, driver IC chip/power MOS chip), the dielectric material (Fig. 9, 35, dielectric film) including a portion (annotated Figure 9) disposed between the first conductive member (Fig. 9, 37, conductive film) and the second conductive member (Fig. 9, 37, conductive film),
the first conductive member including a portion (Fig. 9, 37, conductive film) exposed through the second surface (annotated Figure 9), the second conductive member including a portion (Fig. 9, 37, conductive film) exposed through the second surface (annotated Figure 9).
PNG
media_image1.png
914
1497
media_image1.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEE to incorporate the teachings of SATO, such that a power module comprising: a second substrate having a first surface and a second surface, the first surface being coupled to the plurality of semiconductor dies, the second substrate including a dielectric material, a first conductive member at least partially embedded into the second substrate and connected to the plurality of semiconductor dies, and a second conductive member at least partially embedded into the second substrate and connected to the plurality of semiconductor dies, the dielectric material including a portion disposed between the first conductive member and the second conductive member, the first conductive member including a portion exposed through the second surface, the second conductive member including a portion exposed through the second surface. The said package substrate including dielectric films between the conductive members within a substrate and further the conductive members connected to the respect semiconductor dies thus serve the purpose of mitigating the voltage dropdown due to the presence of tiny parasitic impedance of wiring lines (SATO, [0007]).
Regarding Claim 2, LEE as modified by SATO teaches the power module of claim 1.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the first conductive member (annotated Figure 10) is connected to a source terminal (Fig. 10, 30S/40S, first source pad/second source pad) of each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip).
PNG
media_image2.png
798
895
media_image2.png
Greyscale
Regarding Claim 3, LEE as modified by SATO teaches the power module of claim 1.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the second conductive member (annotated Figure 10) is connected to a gate terminal (Fig. 10, 30G/40G, first gate pad/second gate pad) of each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip).
PNG
media_image2.png
798
895
media_image2.png
Greyscale
Regarding Claim 4 LEE as modified by SATO teaches the power module of claim 1.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip) includes a drain terminal (Fig. 10, 30D, drain pad) connected to the first substrate (Figs. 10/11A, 20, patterned insulation metal substrate).
Regarding Claim 5, LEE as modified by SATO teaches the power module of claim 1.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the first substrate (Figs. 10/11A, 20, patterned insulation metal substrate) includes a first conductive layer (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, [0060]), a second conductive layer (Figs. 10/11A, clip bond is electrically connected the second semiconductor chip, 40, [0060]), and a dielectric layer disposed between the first conductive layer and the second conductive layer (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, second semiconductor chip, 40, and the patterned insulation metal substrate, 20 [0060]).
Regarding Claim 6, LEE as modified by SATO teaches the power module of claim 1.
SATO further teaches the power module (Fig. 9, 81, planarized semiconductor module), wherein the portion of the first conductive member (Fig. 9, 37, conductive film) that is exposed through the second surface (annotated Figure 9) is a first contact region (Fig. 9, 29, wiring lines), and the portion of the second conductive member (Fig. 9, 37, conductive film) that is exposed through the second surface (annotated Figure 9) is a second contact region (Fig. 9, 29, wiring lines), the first contact region having a size greater than a size of the second contact region (annotated Figure 9).
PNG
media_image3.png
929
1497
media_image3.png
Greyscale
Regarding Claim 7, LEE as modified by SATO teaches the power module of claim 6.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the first contact region (annotated Figure 10) is a source contact region (Fig. 10, 30S/40S, first source pad/second source pad) for connecting an external device (Fig. 10, 50, passive components), and the second contact region (annotated Figure 10) is a gate contact region (Fig. 10, 30G/40G, first gate pad/second gate pad) for connecting to the external device (Fig. 10, 50, passive components).
PNG
media_image4.png
974
1362
media_image4.png
Greyscale
Regarding Claim 9, LEE as modified by SATO teaches the power module of claim 1.
SATO further teaches the power module (Fig. 9, 81, planarized semiconductor module), wherein the second substrate member (Fig. 9, 3, package substrate) is connected to each of the plurality of semiconductor dies Fig. 9, 9/5, driver IC chip/power MOS chip) via a die pad (Fig. 9, 33, conductive past material, [0032]).
Regarding Claim 10, LEE as modified by SATO teaches the power module of claim 1.
SATO further teaches the power module (Fig. 9, 81, planarized semiconductor module), wherein the second substrate member (Fig. 9, 3, package substrate) includes a plurality of recesses (Fig. 9, opening, [0032]) and each of the plurality of semiconductor dies (Fig. 9, 9/5, driver IC chip/power MOS chip) is included in a separate recess of the plurality of recesses (Fig. 9, opening, [0032]).
Regarding Claim 11, LEE as modified by SATO teaches the power module of claim 1.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the power module (Figs. 10/18, 7/10, power module package) further comprises:
a third substrate coupled to the second substrate (Fig. 18, 70A/70B/70C/70D, clip bond or RDL structures, [0060]).
Regarding Claim 12, LEE teaches a power module (Fig. 10, 7, power module package) comprising:
a first substrate (Figs. 10/11A, 20, patterned insulation metal substrate includes a carrier, 22, an insulation layer, 24, and a conductive layer, 26, [0034]) including a first conductive layer (Fig. 11A, 222, second part of the metal carrier, 22, [0038]), a second conductive layer (Fig. 11A, 26, conductive layer, [0034]), and a dielectric layer (Fig. 11A, 24, insulation layer, [0034]) disposed between the first conductive layer (Fig. 11A, 222, second part of the metal carrier, 22, [0038]) and the second conductive layer (Fig. 11A, 26, conductive layer, [0034]);
a plurality of semiconductor dies (Fig. 11A, 40, semiconductor power chip) coupled to the first conductive layer (Fig. 11A, 222, second part of the metal carrier, 22, [0038]) of the substrate (Figs. 10/11A, 20, patterned insulation metal substrate includes a carrier, 22, an insulation layer, 24, and a conductive layer, 26, [0034]).
LEE does not explicitly disclose a power module comprising: a second substrate member including a dielectric material, a first conductive member clip at least partially embedded into the second substrate and coupled to the plurality of semiconductor dies, a second conductive member at least partially embedded into the second substrate and coupled to the plurality of semiconductor dies, the dielectric material including a portion disposed between the first conductive member and the second conductive member, the first conductive member including a first contact region that is exposed through a surface of the second substrate, the second conductive member including a second contact region that is exposed through the surface of the second substrate.
SATO teaches a power module (Fig. 9, 81, planarized semiconductor module) comprising:
a second substrate member (Fig. 9, 3, package substrate) including a dielectric material (Fig. 9, 35, dielectric film), a first conductive member (Fig. 9, 37, conductive film) at least partially embedded (annotated Figure 9) into the second substrate (Fig. 9, 3, package substrate) and coupled to the plurality of semiconductor dies (Fig. 9, 9/5, driver IC chip/power MOS chip), a second conductive member (Fig. 9, 37, conductive film) at least partially embedded (annotated Figure 9) into the second substrate (Fig. 9, 3, package substrate) and coupled to the plurality of semiconductor dies (Fig. 9, 9/5, driver IC chip/power MOS chip), the dielectric material (Fig. 9, 35, dielectric film) including a portion (annotated Figure 9) disposed between the first conductive member (Fig. 9, 37, conductive film) and the second conductive member (Fig. 9, 37, conductive film),
the first conductive member (Fig. 9, 37, conductive film) including a first contact region (Fig. 9, 29, wiring lines) that is exposed through a surface (annotated Figure 9) of the second substrate (Fig. 9, 3, package substrate), the second conductive member (Fig. 9, 37, conductive film) including a second contact region (Fig. 9, 29, wiring lines) that is exposed through the surface (annotated Figure 9) of the second substrate (Fig. 9, 3, package substrate).
PNG
media_image5.png
914
1497
media_image5.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEE to incorporate the teachings of SATO, such that a power module comprising: a second substrate member including a dielectric material, a first conductive member clip at least partially embedded into the second substrate and coupled to the plurality of semiconductor dies, a second conductive member at least partially embedded into the second substrate and coupled to the plurality of semiconductor dies, the dielectric material including a portion disposed between the first conductive member and the second conductive member, the first conductive member including a first contact region that is exposed through a surface of the second substrate, the second conductive member including a second contact region that is exposed through the surface of the second substrate. The said package substrate including dielectric films between the conductive members within a substrate and further the conductive members connected to the respect semiconductor dies thus serve the purpose of mitigating the voltage dropdown due to the presence of tiny parasitic impedance of wiring lines (SATO, [0007]).
Regarding Claim 13, LEE as modified by SATO teaches the power module of claim 12.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the second contact region (Figs. 3/10, 32A, electrodes comprising drain, source, and gate, [0038]) includes a gate contact region (Fig. 10, 30G/40G, first gate pad/second gate pad) that is common to the plurality of semiconductor dies (Fig. 10, 30/40, semiconductor power chip).
Regarding Claim 14, LEE as modified by SATO teaches the power module of claim 13.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the first contact region (Figs. 3/10, 32A, electrodes comprising drain, source, and gate, [0038]) includes source contact region (Fig. 10, 30S/40S, first source pad/second source pad) that is common to the plurality of semiconductor dies (Fig. 10, 30/40, semiconductor power chip), the source contact region (Fig. 10, 30S/40S, first source pad/second source pad) having a size greater than a size (annotated Figure 3) of the gate contact region (Fig. 10, 30G/40G, first gate pad/second gate pad).
PNG
media_image6.png
962
715
media_image6.png
Greyscale
Regarding Claim 15, LEE as modified by SATO teaches the power module of claim 12.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the first conductive member (annotated Figure 10) is connected to a source terminal (Fig. 10, 30S/40S, first source pad/second source pad) of each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip), the second conductive member (annotated Figure 10) being connected to a gate terminal (Fig. 10, 30G/40G, first gate pad/second gate pad) of each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip).
PNG
media_image7.png
798
895
media_image7.png
Greyscale
Regarding Claim 21, LEE as modified by SATO teaches the power module of claim 1.
SATO further teaches the power module (Fig. 9, 81, planarized semiconductor module), wherein the first conductive member (Fig. 9, 37, conductive film) includes a portion that extends entirely through a thickness (annotated Figure 9) of the second substrate (Fig. 9, 3, package substrate) from the first surface (annotated Figure 9) to the second surface (annotated Figure 9).
Regarding Claim 22, LEE as modified by SATO teaches the power module of claim 1.
SATO further teaches the power module (Fig. 9, 81, planarized semiconductor module), wherein the dielectric material (Fig. 9, 35, dielectric film) includes a perimeter portion (annotated Figure 9) that extends around the first conductive member (Fig. 9, 37, conductive film) and the second conductive member (Fig. 9, 37, conductive film), the perimeter portion (annotated Figure 9) that defining a side of the second substrate (Fig. 9, 3, package substrate) that extends between the first surface (annotated Figure 9) and the second surface (annotated Figure 9).
Regarding Claim 23, LEE as modified by SATO teaches the power module of claim 1.
SATO further teaches the power module (Fig. 9, 81, planarized semiconductor module), wherein the second substrate (Fig. 9, 3, package substrate) includes a pre- molded (Fig. 9, 25, resin plate, [0031-0033]) printed circuit board (Fig. 12. 103, printed wiring board).
PNG
media_image8.png
848
1506
media_image8.png
Greyscale
Claim(s) 8, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE in view of SATO as applied to claims 1-7, and 10-15 above, and further in view of Seungwon Im et al, (hereinafter IM), US 20210066256 A1.
Regarding Claim 8, LEE as modified by SATO teaches the power module of claim 1.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip) includes a first semiconductor die (Figs. 10/11A, 30, semiconductor power chip), a second semiconductor die (Figs. 10/11A, 40, semiconductor power chip).
LEE does not explicitly disclose the power module, wherein the plurality of semiconductor dies includes a first semiconductor die, a second semiconductor die, and a third semiconductor die.
IM teaches the power module (Figs. 4A-4B, 400, semiconductor device), wherein the plurality of semiconductor dies (Fig. 5A, 510a/510b.520a/520b, IGBTs) includes a first semiconductor die (Fig. 5A, 510, IGBT, [0046]), and a second semiconductor die (Fig. 5A, 510, IGBT, [0046]), and a third semiconductor die (Fig. 5A, 510, IGBT, [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEE to incorporate the teachings of IM, such that the power module, wherein the plurality of semiconductor dies includes a first semiconductor die, a second semiconductor die, and a third semiconductor die, so that the arrangement of parallel IGBTs can reduce the stray (parasitic) inductance and thus improve the performance of power semiconductor devices included in package assemblies (IM, Figure 5A, [0003]).
Regarding Claim 16, LEE as modified by SATO teaches the power module of claim 12.
LEE further teaches the power module (Fig. 10, 7, power module package), wherein the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip) includes a first semiconductor die (Figs. 10/11A, 30, semiconductor power chip), a second semiconductor die (Figs. 10/11A, 40, semiconductor power chip).
SATO further teaches the power module (Fig. 9, 81, planarized semiconductor module), wherein the second substrate (Fig. 9, 3, package substrate) including a first recess (Fig. 9, opening, [0032]) with the first semiconductor die (Fig. 9, 9/5, driver IC chip/power MOS chip), a second recess (Fig. 9, opening, [0032]) with the second semiconductor die (Fig. 9, 9/5, driver IC chip/power MOS chip).
LEE as modified by SATO does not explicitly disclose the power module, wherein the plurality of semiconductor dies includes a first semiconductor die, a second semiconductor die, and a third semiconductor die, the clip substrate member including a first recess with the first semiconductor die, a second recess with the second semiconductor die, and a third recess with the third semiconductor die die.
IM teaches the power module (Figs. 4A-4B, 400, semiconductor device), wherein the plurality of semiconductor dies (Fig. 5A, 510a/510b.520a/520b, IGBTs) includes a first semiconductor die (Fig. 5A, 510, IGBT, [0046]), a second semiconductor die (Fig. 5A, 510, IGBT, [0046]), and a third semiconductor die (Fig. 5A, 510, IGBT, [0046]), the clip substrate member (Fig. 5C, 250, conductive clip) including a first recess (annotated Figure 5C) with the first semiconductor die (Fig. 5A, 510, IGBT, [0046]), a second recess (annotated Figure 5C) with the second semiconductor die (Fig. 5A, 510, IGBT, [0046]), and a third recess (annotated Figure 5C) with the third semiconductor die (Fig. 5A, 510, IGBT, [0046]).
PNG
media_image9.png
754
1150
media_image9.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEE as modified by SATO to incorporate the teachings of IM, such that the power module, wherein the plurality of semiconductor dies includes a first semiconductor die, a second semiconductor die, and a third semiconductor die, the clip substrate member including a first recess with the first semiconductor die, a second recess with the second semiconductor die, and a third recess with the third semiconductor die. This arrangement of parallel IGBTs can reduce the stray (parasitic) inductance and thus improve the performance of power semiconductor devices included in package assemblies (IM, Figure 5A, [0003]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20100314744 A1 – Figure 1
STATEMENT OF RELEVANCE – Schematic views shows a method of manufacturing a substrate having a single patterned metal layer exposing a patterned dielectric layer.
US 20100148327 A1 – Figure 5
STATEMENT OF RELEVANCE – A side cross-sectional view of a semiconductor die, 33 package comprising a source region (and a gate region) can be electrically and mechanically coupled to the source interconnect structure, 32, using a conductive adhesive, 56 such as solder.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
Prosecution Insights