DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Claim(s) 1-16 directed to a device, in the reply filed on 03/11/2026 is acknowledged.
Response to Amendment
The election of original claims with respect to claims 1-16 filed on 03/11/2026 have been fully considered for examination based on their merits. The non-elected claims 17-20 are canceled by the Applicant.
Response to Arguments
Applicant elected claim(s) 1-16 (without traverse) directed to a semiconductor device filed dated 03/11/2026 are considered and entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, and 10-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chia-Yen Lee et al, (hereinafter LEE), US 20170317015 A1.
Regarding Claim 1, LEE teaches a power module (Fig. 10, 7, power module package) comprising:
a substrate (Figs. 10/11A, 20, patterned insulation metal substrate);
a plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip) coupled to the substrate (Figs. 10/11A, 20); and
a clip substrate member (Figs. 10/11A, 70A, clip bond, [0060]) having a first surface (annotated Figure 11A) and a second surface (annotated Figure 11A), the first surface (annotated Figure 11A) being coupled (Fig. 11A, Q, bonded material) to the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip), the clip substrate member (Figs. 10/11A, 70A, clip bond, [0060]) including a first conductive clip (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, [0060]) and a second conductive clip (Figs. 10/11A, clip bond is electrically connected the second semiconductor chip, 40, [0060]), and a dielectric material portion disposed between the first conductive clip and the second conductive clip (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, second semiconductor chip, 40, and the patterned insulation metal substrate, 20 [0060]),
the second surface (annotated Figure 11A) including a first contact region (annotated Figure 11A) and a second contact region (annotated Figure 11A), the first contact region (annotated Figure 11A) including a portion of the first conductive clip (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, [0060]), the second contact region (annotated Figure 11A) including a portion of the second conductive clip (Figs. 10/11A, clip bond is electrically connected the second semiconductor chip, 40, [0060]).
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Regarding Claim 2, LEE teaches the power module (Fig. 10, 7, power module package) of claim 1, wherein the first conductive clip (annotated Figure 10) is connected to a source terminal (Fig. 10, 30S/40S, first source pad/second source pad) of each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip).
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Regarding Claim 3, LEE teaches the power module (Fig. 10, 7, power module package) of claim 1, wherein the second conductive clip (annotated Figure 10) is connected to a gate terminal (Fig. 10, 30G/40G, first gate pad/second gate pad) of each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip).
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Regarding Claim 4, LEE teaches the power module (Fig. 10, 7, power module package) of claim 1, wherein each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip) includes a drain terminal (Fig. 10, 30D, drain pad) connected to the substrate (Figs. 10/11A, 20, patterned insulation metal substrate).
Regarding Claim 5, LEE teaches the power module (Fig. 10, 7, power module package) of claim 1, wherein the substrate (Figs. 10/11A, 20, patterned insulation metal substrate) includes a first conductive layer (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, [0060]), a second conductive layer (Figs. 10/11A, clip bond is electrically connected the second semiconductor chip, 40, [0060]), and a dielectric layer disposed between the first conductive layer and the second conductive layer (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, second semiconductor chip, 40, and the patterned insulation metal substrate, 20 [0060]).
Regarding Claim 6, LEE teaches the power module (Fig. 10, 7, power module package) of claim 1, wherein the first contact region (annotated Figure 11A) has a size greater than a size (annotated Figure 11A) of the second contact region (annotated Figure 11A).
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Regarding Claim 7, LEE teaches the power module (Fig. 10, 7, power module package) of claim 1, wherein the first contact region (annotated Figure 10) is a source contact (Fig. 10, 30S/40S, first source pad/second source pad) for an external device (Fig. 10, 50, passive components), and the second contact region (annotated Figure 10) is a gate contact (Fig. 10, 30G/40G, first gate pad/second gate pad) for the external device (Fig. 10, 50, passive components).
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Regarding Claim 10, LEE teaches the power module (Figs. 10/18, 7/10, power module package) of claim 1, wherein the clip substrate member (Fig. 18, 70A/70B/70C/70D, clip bond or RDL structures, [0060]) includes a plurality of recesses (annotated Figure 18) and each of the plurality of semiconductor dies (Fig. 18, 30/40, semiconductor power chip) is included in a separate recess of the plurality of recesses (annotated Figure 18).
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Regarding Claim 11, LEE teaches the power module (Figs. 10/18, 7/10, power module package) of claim 1, wherein the substrate is a first substrate (Figs. 10/11A, 20, patterned insulation metal substrate), the power module (Figs. 10/18, 7/10, power module package) further comprising:
a second substrate coupled to the clip substrate member (Fig. 18, 70A/70B/70C/70D, clip bond or RDL structures, [0060]).
Regarding Claim 12, LEE teaches a power module (Fig. 10, 7, power module package) comprising:
a substrate (Figs. 10/11A, 20, patterned insulation metal substrate) including a first conductive layer (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, [0060]), a second conductive layer (Figs. 10/11A, clip bond is electrically connected the second semiconductor chip, 40, [0060]), and a dielectric layer disposed between the first conductive layer and the second conductive layer (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, second semiconductor chip, 40, and the patterned insulation metal substrate, 20 [0060]);
a plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip) coupled to the first conductive layer (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, [0060]) of the substrate (Figs. 10/11A, 20, patterned insulation metal substrate); and
a clip substrate member (Figs. 10/11A, 70A, clip bond, [0060]) including a first conductive clip (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, [0060]) coupled to the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip), a second conductive clip (Figs. 10/11A, clip bond is electrically connected the second semiconductor chip, 40, [0060]) coupled to the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip), and a dielectric material having a portion disposed between the first conductive clip and the second conductive clip (Figs. 10/11A, clip bond is electrically connected the first semiconductor chip, 30, second semiconductor chip, 40, and the patterned insulation metal substrate, 20 [0060]),
the clip substrate member (Figs. 10/11A, 70A, clip bond, [0060]) including a source contact region, the source contact region (Fig. 10, 30S/40S, first source pad/second source pad) including a first portion (annotated Figure 10) of a surface of the clip substrate member (Figs. 10/11A, 70A, clip bond, [0060]), the source contact region (Fig. 10, 30S/40S, first source pad/second source pad) including a portion of the first conductive clip (annotated Figure 10).
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Regarding Claim 13, LEE teaches the power module (Fig. 10, 7, power module package) of claim 12, wherein the clip substrate member (Figs. 10/11A, 70A, clip bond, [0060]) includes a gate contact region (Fig. 10, 30G/40G, first gate pad/second gate pad), the gate contact region (Fig. 10, 30G/40G, first gate pad/second gate pad) including a second portion (annotated Figure 10) of the surface of the clip substrate member (Figs. 10/11A, 70A, clip bond, [0060]), the gate contact region (Fig. 10, 30G/40G, first gate pad/second gate pad) including a portion of the second conductive clip (annotated Figure 10).
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Regarding Claim 14, LEE teaches the power module (Fig. 10, 7, power module package) of claim 13, wherein the source contact region (Fig. 10, 30S/40S, first source pad/second source pad) has a size greater than a size (annotated Figure 11A) of the gate contact region (Fig. 10, 30G/40G, first gate pad/second gate pad).
Regarding Claim 15, LEE teaches the power module (Fig. 10, 7, power module package) of claim 12, wherein the first conductive clip (annotated Figure 10) is connected to a source terminal (Fig. 10, 30S/40S, first source pad/second source pad) of each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip), the second conductive clip (annotated Figure 10) being connected to a gate terminal (Fig. 10, 30G/40G, first gate pad/second gate pad) of each of the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE in view of Seungwon Im et al, (hereinafter IM), US 20210066256 A1.
Regarding Claim 8, LEE teaches the power module (Fig. 10, 7, power module package) of claim 1, wherein the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip) includes a first semiconductor die (Figs. 10/11A, 30, semiconductor power chip), a second semiconductor die (Figs. 10/11A, 40, semiconductor power chip).
LEE does not explicitly disclose the power module, wherein the plurality of semiconductor dies includes a first semiconductor die, a second semiconductor die, and a third semiconductor die.
IM teaches the power module (Figs. 4A-4B, 400, semiconductor device), wherein the plurality of semiconductor dies (Fig. 5A, 510a/510b.520a/520b, IGBTs) includes a first semiconductor die (Fig. 5A, 510, IGBT, [0046]), a second semiconductor die (Fig. 5A, 510, IGBT, [0046]), and a third semiconductor die (Fig. 5A, 510, IGBT, [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEE to incorporate the teachings of IM, such that the power module, wherein the plurality of semiconductor dies includes a first semiconductor die, a second semiconductor die, and a third semiconductor die, so that the arrangement of parallel IGBTs can reduce the stray (parasitic) inductance and thus improve the performance of power semiconductor devices included in package assemblies (IM, Figure 5A, [0003]).
Regarding Claim 16, LEE teaches the power module (Fig. 10, 7, power module package) of claim 12, wherein the plurality of semiconductor dies (Figs. 10/11A, 30/40, semiconductor power chip) includes a first semiconductor die (Figs. 10/11A, 30, semiconductor power chip), a second semiconductor die (Figs. 10/11A, 40, semiconductor power chip), the clip substrate member (Fig. 18, 70A/70B/70C/70D, clip bond or RDL structures, [0060]) including a first recess (annotated Figure 18) with the first semiconductor die (Figs. 10/11A, 30, semiconductor power chip), a second recess (annotated Figure 18) with the second semiconductor die (Figs. 10/11A, 40, semiconductor power chip).
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LEE does not explicitly disclose the power module, wherein the plurality of semiconductor dies includes a first semiconductor die, a second semiconductor die, and a third semiconductor die, the clip substrate member including a first recess with the first semiconductor die, a second recess with the second semiconductor die, and a third recess with the third semiconductor die.
IM teaches the power module (Figs. 4A-4B, 400, semiconductor device), wherein the plurality of semiconductor dies (Fig. 5A, 510a/510b.520a/520b, IGBTs) includes a first semiconductor die (Fig. 5A, 510, IGBT, [0046]), a second semiconductor die (Fig. 5A, 510, IGBT, [0046]), and a third semiconductor die (Fig. 5A, 510, IGBT, [0046]), the clip substrate member (Fig. 5C, 250, conductive clip) including a first recess (annotated Figure 5C) with the first semiconductor die (Fig. 5A, 510, IGBT, [0046]), a second recess (annotated Figure 5C) with the second semiconductor die (Fig. 5A, 510, IGBT, [0046]), and a third recess (annotated Figure 5C) with the third semiconductor die (Fig. 5A, 510, IGBT, [0046]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEE to incorporate the teachings of IM, such that the power module, wherein the plurality of semiconductor dies includes a first semiconductor die, a second semiconductor die, and a third semiconductor die, the clip substrate member including a first recess with the first semiconductor die, a second recess with the second semiconductor die, and a third recess with the third semiconductor die. This arrangement of parallel IGBTs can reduce the stray (parasitic) inductance and thus improve the performance of power semiconductor devices included in package assemblies (IM, Figure 5A, [0003]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE in view of Yun Hwa Choi, (hereinafter CHOI), US 20220399300 A1.
Regarding Claim 9, LEE teaches the power module (Fig. 10, 7, power module package) of claim 1.
LEE does not explicitly disclose the power module, wherein the clip substrate member is connected to each of the plurality of semiconductor dies via a die pad.
CHOI teaches the power module (Fig. 1, semiconductor package, [0030]), wherein the clip substrate member (Fig. 11, 110, clip structure) is connected to each of the plurality of semiconductor dies (Fig. 11, 120, semiconductor device) via a die pad (Fig. 11, 110a, conductive adhesive).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEE to incorporate the teachings of CHOI, such that the power module, wherein the clip substrate member is connected to each of the plurality of semiconductor dies via a die pad, so that a clip structure including: a first bonding unit bonded to a terminal part of an upper surface or a lower surface of the semiconductor device by using a conductive adhesive interposed therebetween, for providing an efficient package device (CHOI, Figure 11, [0009]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220189848 A1 – Figure 1A
STATEMENT OF RELEVANCE – Semiconductor component directly bonded on the substrate, wherein the substrate includes a dielectric layer (132) is stacked in between the metal layers (132 and 133).
US 20210091054 A1 – Figure 7
STATEMENT OF RELEVANCE – A top view of the power electronic module, comprising two pairs of stacks of two semiconductor chips is connected in parallel and forms an arm of a half-bridge.
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/SESHA SAIRAMAN SRINIVASAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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