DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .\
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brunschwiler et al (US Publication 20170179001).
Regarding claim 1, Brunschwiler teaches a semiconductor package, comprising:
a first die having a front side and a backside (Fig. 1, bottom die of chip stack 106 with front / back sides top / bottom respectively);
a substrate carrying the first die with the substrate comprising a first cavity allowing a liquid to pass through (Fig. 1, substrate 112, para 29, first cavity 113); and
an upper portion defining a first part of the first cavity (Fig. 1, upper portion of 112 closest to 106 defining top portion of cavity 113);
a lower portion defining a second part of the first cavity (Fig. 1, lower portion of 112 closest to 102 defining lower portion of cavity 113); and
a bonding structure connecting the upper portion and the lower portion of the substrate (Fig. 1, solid black line through 112, para 29),
wherein the first part and the second part of the first cavity combined is configured to form a fluidic channel allowing the liquid to pass through (para 29).
a cold plate over the first die with the cold plate comprising a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first cavity and the second cavity (Fig. 1, cold plate 114, second cavity 115 connected to first cavity 113 fluid flow denoted by arrows).
Regarding claim 3, Brunschwiler teaches the limitations of claim 2 upon which claim 3 depends.
Brunschwiler teaches the bonding structure further comprises:
a first sealing structure on a surface of the upper portion facing the lower portion of the substrate (Fig. 1 and 2, top of 112 structure);
a second sealing structure on a surface of the lower portion facing the upper portion of the substrate (Fig. 1 and 2, bottom of 112 structure), wherein the second sealing structure geometrically matches the first sealing structure; and
a bonding material connecting the first sealing structure and the second sealing structure (para 29).
Regarding claim 4, Brunschwiler teaches the limitations of claim 3 upon which claim 4 depends.
Brunschwiler teaches wherein the substrate further comprises:
a first interconnect layer facing toward the first die (Fig. 1, 106 facing side of 112 with vias 108, para 32);
a second interconnect layer facing away from the first die (Fig. 1, 102 facing side of 112 with vias 108, para 32);
a through via electrically, optically, or thermally coupling the first interconnect layer and the second interconnect layer (Fig. 1, via 108); and
an isolation structure proximal to the first sealing structure and the second sealing structure, configured to isolate the through via from the first sealing structure and the second sealing structure (Fig. 2, vias 108 in 112 channel area 113).
Regarding claim 5, Brunschwiler teaches the limitations of claim 1 upon which claim 5 depends.
Brunschwiler teaches a plurality of second dies stacked over or disposed side-by-side with the first die (Fig. 1, die stack 106); and
a structural member disposed side-by-side with the first die and the second dies (Fig. 1, portions of 104 on either side of 106 defining flow path with arrows), the structural member comprising a third cavity configured to connect to the first cavity and the second cavity (Fig. 1, portions of 104 on either side of 106 defining flow path above 114), allowing for the liquid to flow between the first cavity, the second cavity, and the third cavity (Fig. 1, fluid flow path denoted by arrows),
wherein the cold plate is in direct thermal contact with at least one of a top die of the second dies or the first die (Fig. 1, top of die stack 106 in thermal contact with 114).
Regarding claim 16, Brunschwiler teaches the limitations of claim 5 upon which claim 16 depends.
Brunschwiler teaches a flexible circuit interconnect electrically connecting the substrate or an electronic component underneath the substrate to a circuit layer proximal to the cold plate with the flexible circuit interconnect configured to provide power or signaling to at least one of the second dies or the front side of the first die (Fig. 1, 101 and 118).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Brunschwiler et al (US Publication 20170179001) in view of Bothe et al (US Publication 20240429122, note these claims are not supported by the CIP and provisional applications that would come before this date).
Regarding claims 6 and 14, Brunschwiler teaches the limitations of claim 5 upon which claim 6 depends.
Brunschwiler teaches:
[claim 6] a first supporter disposed in between the first die and the substrate, and thermally coupled to the first die and the substrate (Fig. 8, 212 below 206, para 44).
[claim 14] a second supporter between the first die and one of the second dies, or between adjacent second dies (Fig. 8, supporters 212 and dies 206),; and a through via in the second supporter (Fig. 2, 108).
Brunschwiler lacks:
[claim 6] wherein a thermal conductivity of the first supporter is greater than a thermal conductivity of the first die.
[claim 14] wherein the second supporter comprises an interposer composed of a material with a thermal conductivity greater than that of silicon.
Bothe teaches:
[claim 6] wherein a thermal conductivity of the first supporter is greater than a thermal conductivity of the first die (para 35 and 65).
[claim 14] wherein the second supporter comprises an interposer composed of a material with a thermal conductivity greater than that of silicon (para 35 and 65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include the supporter with thermal conductivity greater than the die and silicon as taught by Bothe in order to improve the thermal management properties of the device.
Regarding claim 21, Brunschwiler teaches a semiconductor package, comprising:
a first die having a front side and a backside (Fig. 1, bottom die of chip stack 106 with front / back sides top / bottom respectively);
a substrate carrying the first die with the substrate comprising a first cavity allowing a liquid to pass through (Fig. 1, substrate 112, para 29, first cavity 113);
a cold plate over the first die with the cold plate comprising a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first cavity and the second cavity (Fig. 1, cold plate 114, second cavity 115 connected to first cavity 113 fluid flow denoted by arrows); and
a first supporter disposed in between the first die and the substrate, and thermally coupled to the first die and the substrate (Fig. 8, 212 below 206, para 44)
Brunschwiler does not specifically teach wherein a thermal conductivity of the first supporter is greater than a thermal conductivity of the first die.
Bothe teaches wherein a thermal conductivity of the first supporter is greater than a thermal conductivity of the first die (para 35 and 65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include the supporter with thermal conductivity greater than the die and silicon as taught by Bothe in order to improve the thermal management properties of the device.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Brunschwiler et al (US Publication 20170179001) in view of Chainer (US Publication 20170186728).
Regarding claim 17, Brunschwiler teaches a semiconductor package, comprising:,
a processor die having a front side and a backside (Fig. 1, bottom die of chip stack 106 with front / back sides top / bottom respectively);
a substrate carrying the processor die, the memory dies, and the control dies with the substrate comprising a first cavity allowing a liquid to pass through (Fig. 1, substrate 112, para 29, first cavity 113); and
wherein the substrate further comprises: an upper portion defining a first part of the first cavity (Fig. 1, upper portion of 112 closest to 106 defining top portion of cavity 113);
a lower portion defining a second part of the first cavity (Fig. 1, lower portion of 112 closest to 102 defining lower portion of cavity 113); and
a bonding structure connecting the upper portion and the lower portion of the substrate (Fig. 1, solid black line through 112, para 29),
wherein the first part and the second part of the first cavity combined is configured to form a fluidic channel allowing the liquid to pass through (para 29).
a cold plate over the processor die, the memory dies, and the control dies, with the cold plate comprising a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first cavity and the second cavity (Fig. 1, cold plate 114, second cavity 115 connected to first cavity 113 fluid flow denoted by arrows),
wherein the cold plate is in direct thermal contact with the processor die, a top die of the memory dies or the control dies (Fig. 1, 114 in direct thermal contact with top die of stack 106).
Brunschwiler lacks a plurality of memory dies and control dies stacked over the processor die and thus a substrate carrying all the dies and a cold plate over.
Chainer teaches a plurality of memory dies and control dies stacked over the processor die (Fig. 1, 100, para 23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include memory and control dies stacked where in the position where the processor die is presently as taught by Chainer in order to improve the semiconductor die types cooled by the thermal management device package.
Claims 7-10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Brunschwiler et al (US Publication 20170179001) in view of Bothe et al (US Publication 20240429122) and further in view of Chainer (US Publication 20170186728).
Regarding claim 7, Brunschwiler as modified teaches the limitations of claim 6 upon which claim 7 depends.
Brunschwiler lacks wherein the first supporter comprises an interposer composed of a material with a thermal conductivity greater than that of silicon, and
with the interposer having a cross sectional width greater than or substantially identical to a cross sectional width of the first die.
Bothe teaches wherein the first supporter comprises an interposer composed of a material with a thermal conductivity greater than that of silicon (para 35 and 65)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the interposer with thermal conductivity greater than silicon as taught by Bothe in order to improve the thermal management properties of the device.
Brunschwiler still lacks with the interposer having a cross sectional width greater than or substantially identical to a cross sectional width of the first die.
Chainer teaches with the interposer having a cross sectional width greater than or substantially identical to a cross sectional width of the first die (para 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the interposer width as taught by Chainer in order to improve the thermal and mechanical robustness of the device.
Regarding claim 8, Brunschwiler as modified teaches the limitations of claim 6 upon which claim 8 depends.
Brunschwiler lacks wherein the first supporter and the first die combined form a composite layer with at least one via passing through the first die and the first supporter.
Chainer teaches wherein the first supporter and the first die combined form a composite layer with at least one via passing through the first die and the first supporter (Fig. 10, 1000, para 57).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the supporter and die composite layer with at least on via as taught by Chainer in order to improve the thermal and mechanical robustness of the device.
Regarding claim 9, Brunschwiler as modified teaches the limitations of claim 6 upon which claim 9 depends.
Brunschwiler lacks wherein the first supporter is composed of diamond, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or a combination thereof, and the substrate is composed of silicon, diamond, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or a combination thereof.
Bothe teaches wherein the first supporter is composed of diamond, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or a combination thereof, and the substrate is composed of silicon, diamond, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, silicon carbide, or a combination thereof (para 35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the supporter material as taught by Bothe in order to improve the thermal management properties of the device.
Regarding claim 10, Brunschwiler as modified teaches the limitations of claim 6 upon which claim 10 depends.
Brunschwiler lacks wherein the backside of the first die is located in close proximity to the first supporter and the front side of the first die is farther away from the first supporter compared to the backside.
Chainer teaches wherein the backside of the first die is located in close proximity to the first supporter and the front side of the first die is farther away from the first supporter compared to the backside (Fig. 10, 1000).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the die and supporter orientation as taught by Chainer in order to improve the heat distribution/transfer properties of the device.
Regarding claim 19, Brunschwiler as modified teaches the limitations of claim 18 upon which claim 19 depends.
Brunschwiler teaches a first high thermal conductivity (HTC) structure disposed in between the processor die and the substrate, and thermally coupled to the processor die and the substrate (Fig. 8, 212 below 206, para 44);
a second HTC structure between the processor die and control dies or between adjacent memory dies, wherein a thermal conductivity of the second HTC structure is greater than the thermal conductivity of the processor die (Fig. 8, 212 below 206, para 44);
a first structural member disposed side-by-side with the processor die, the memory dies, and the control dies (Fig. 1, portions of 104 on either side of 106 defining flow path with arrows) with the first structural member comprising a third cavity configured to connect to the first cavity and the second cavity (Fig. 1, portions of 104 on either side of 106 defining flow path above 114), allowing the liquid to flow between the first cavity, the second cavity, and the third cavity (Fig. 1, fluid flow path denoted by arrows); and
a second structural member disposed side-by-side with the processor die, the plurality of memory dies or the control dies, wherein the second structural member is stacked with the second HTC structure (Fig. 1, 104).
Brunschwiler lacks , wherein a thermal conductivity of the first HTC structure is greater than a thermal conductivity of the processor die.
Bothe teaches wherein a thermal conductivity of the first HTC structure is greater than a thermal conductivity of the processor die (para 35 and 65)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the interposer with thermal conductivity greater than silicon as taught by Bothe in order to improve the thermal management properties of the device.
Claims 11-13, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Brunschwiler et al (US Publication 20170179001) in view of Bothe et al (US Publication 20240429122), Chainer (US Publication 20170186728), and further in view of Chung et al (US Publication 20240404951).
Regarding claims 11-13, Brunschwiler as modified teaches the limitations of claim 10 upon which claim 11 depends.
Brunschwiler teaches
[claim 13] a first power via and a first signal via in the first supporter, connecting the second RDL and the third RDL (Fig. 2, 108s)
Brunschwiler lacks
[claim 11] a global interconnect disposed on the backside of the first die;
a first re-distribution layer (RDL) disposed on the global interconnect; and
a second RDL on a first side of the first supporter facing the first die,
wherein the first die and the first supporter are bonded through the first RDL and the second RDL.
[claim 12] a buried power rail proximal to a front-end-of-line structure of the first die;
a power trace and a signal trace in the global interconnect, electrically connected to the buried power rail, to the FEOL structure and to the first supporter.
[claim 13] a third RDL on a second side of the first supporter opposite to the first side;
a first thermal via in the first supporter, connecting the second RDL and the third RDL;
a second thermal via proximal to the power trace and the signal trace in the global interconnect and the FEOL structure of the first die, wherein the second thermal via is thermally coupled to the first thermal via in the first supporter.
Chung teaches
[claim 11] a global interconnect disposed on the backside of the first die (Fig. 1A, 308b, para 45);
a first re-distribution layer (RDL) disposed on the global interconnect (Fig. 1A, 306 on 308b); and
a second RDL on a first side of the first supporter facing the first die (Fig. 1A, 306 on supporter of Brunschwiler as modified),
wherein the first die and the first supporter are bonded through the first RDL and the second RDL (Fig. 1A, 306, as stated above and bonded).
[claim 12] a buried power rail proximal to a front-end-of-line structure of the first die (Fig. 1A, 318, para 28,42, and 70);
a power trace and a signal trace in the global interconnect, electrically connected to the buried power rail, to the FEOL structure and to the first supporter (Fig. 1A, 312, para 38).
[claim 13] a third RDL on a second side of the first supporter opposite to the first side (Fig. 1A, 306 on supporter of Brunschwiler as modified);
a first thermal via in the first supporter, connecting the second RDL and the third RDL (Fig. 1A, 319 in supporter of Brunschwiler as modified);
a second thermal via proximal to the power trace and the signal trace in the global interconnect and the FEOL structure of the first die, wherein the second thermal via is thermally coupled to the first thermal via in the first supporter (Fig. 1A, 319, para 37).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the RDLs, buried power rail, global interconnect, and vias taught by Chung in order to improve the operability and reliability of the device.
Regarding claim 20, Brunschwiler as modified teaches the limitations of claim 19 upon which claim 20 depends.
Brunschwiler lacks spacer interconnects between the processor die and the plurality of memory dies and control dies;
an air gap defined by the spacer interconnects, the processor die, and the control dies, wherein the control dies govern interconnections between the processor die and the memory dies;
a redistribution layer (RDL) with conductive traces over a front side of the processor die; and
a heat spreading layer or a thermal isolation layer in respective interconnect structure of the processor die, the control dies, the memory dies, the first HTC structure, the second HTC structure, or a combination thereof.
Bothe teaches
spacer interconnects between the processor die and the plurality of memory dies and control dies (Fig. 1 and 11, 100);
an air gap defined by the spacer interconnects, the processor die, and the control dies, wherein the control dies govern interconnections between the processor die and the memory dies (Fig. 1 and 11, airgap between 300 and 200 defined by 100 on either side).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the spacers and air gap as taught by Bothe in order to improve the reliability and robustness of the device.
Brunschwiler still lacks a redistribution layer (RDL) with conductive traces over a front side of the processor die ; and
a heat spreading layer or a thermal isolation layer in respective interconnect structure of the processor die, the control dies, the memory dies, the first HTC structure, the second HTC structure, or a combination thereof.
Chung teaches a redistribution layer (RDL) with conductive traces over a front side of the processor die (Fig. 1A, 306 on 308b); and
a heat spreading layer or a thermal isolation layer in respective interconnect structure of the processor die, the control dies, the memory dies, the first HTC structure, the second HTC structure, or a combination thereof (514, para 49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the RDL and heat spreading layer as taught by Chung in order to improve the thermal properties as well as the operability and reliability of the device.
Response to Arguments
Applicant's arguments filed 29 March 2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 17, applicant argues that the solid black line traversing the cold plate 112 in Brunschwiler's Fig. 1 does not depict a bonding structure connecting an upper and a lower portion of the alleged substrate. Brunschwiler is completely silent regarding the nature of the referenced black line in Fig. 1 and provides no description of a "bonding structure" that connects upper portion and a lower portion to form a fluidic channel. Paragraph 29 of Brunschwiler states “The interposer cold plate 112 may be any material known in the art, such as, for example, silicon and may be formed by bonding two silicon halves. The interposer cold plate 112 has two or more expanding fluid channels 113 (may also be referred to as fluid cavities). Each expanding fluid channel 113 may have a channel inlet and a channel outlet on different sides of the interposer cold plate 112.” The referenced black line is assumed to show the bond point of the upper and lower half of the interposer cold plate.
Regarding claim 6, applicant argues that Brunschwiler does not teach an independent supporter disposed between the die and the substrate. Brunschwiler teaches (Fig. 8) supporter 212 and die 206 where there are multiple die and supporters. Brunschwiler para 29 states that “212 may be similar to the interposer cold plate 112”, but not identical or the same component.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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