Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group I-I, claims 1-8 in the reply filed on February 20th, 2026 is acknowledged. Non-elected invention of Group II-II, claims 9-20 have been cancelled. New claims 21-32 have been added. Claims 1-8 and 21-32 are pending.
Action on merits of Group I-I, claims 1-8 and 21-32 as follows.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on August 13th, 2024 and December 29th, 2025, have been considered by the examiner.
Drawings
The drawings filed on 09/25/2023 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112 (f)/ sixth paragraph
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a transistor layer is configured to receive power directly from an additional die …” as recited in claim 23.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-8, 21-22, 27-28 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2021/0074709, hereinafter as Liu ‘709) in view of Kalyanasundaram (US 10,555,436, hereinafter as Kaly ‘436).
Regarding Claim 1, Liu ‘709 teaches an integrated circuit comprising:
a first circuit die (device layer, Fig. 4, (410); [0050]) having a first metal stack (420; [0053]);
a second circuit die (SRAM cell, Fig. 4, (432); [0058]) having a second metal stack (430; [0057]) that is connected to the first metal stack (420) of the first circuit die (410);
Thus, Liu ‘709 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a temperature sensor placed in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die”.
Kaly ‘436 teaches a temperature sensor (Fig. 2, (44); col. 5, lines 20-30) placed in a transistor layer of the second circuit die (e.g. thermal sensor (44) implemented within a microprocessor, an application specific integrated circuit, or other integrated circuits component (26); col. 5, lines 30-35) in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die (see Fig. 2).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Liu ‘709 by having a temperature sensor placed in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die for the purpose of in predicting temperatures for one or more regions and taking remedial action to avoid overheating of the device (see col. lines 50-60) as suggested by Kaly ‘436 .
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Fig. 4 (Liu ‘709)
Regarding Claim 2, Liu ‘709 teaches the first circuit die includes logic transistors (418; [0051]) that are manufactured in isolation.
Regarding Claim 3, Liu ‘709 teaches the second circuit die (432) corresponds to a pair node and the first circuit die corresponds to an advanced node constructed according to a more advanced technology process compared to the pair node (advanced logic processes; see para. [0036]).
Further, it has been held to be within the general skill of a worker in the art to select a pair node for the second circuit die and an advanced node for the first circuit die on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select a pair node for the second circuit die and an advanced node for the first circuit die when this allows a good flow with the other steps in the fabrication process.
Product by process limitation:
The expression “constructed according to a more advanced technology process” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Regarding Claim 4, Liu ‘709 teaches a majority of static random access memory (SRAM) and analog devices of the integrated circuit (logic circuit) (see para. [0041]).
Further, it has been held to be within the general skill of a worker in the art to have a majority of static random access memory and analog devices of the integrated circuit are implemented in the pair node a on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select a pair node for the second circuit die and an advanced node for the first circuit die when this improves the performance of the semiconductor devices.
Regarding Claim 5, Liu ‘709 teaches a majority of all logic transistors (418) of the integrated circuit are implemented in the advanced node (see Fig. 4).
Regarding Claim 6, Liu ‘709 teaches the second circuit die (104) is positioned beneath the first circuit die (102) in a semiconductor device package including the first circuit die and the second circuit die (see Fig. 1B).
Regarding Claim 7, Liu ‘709 teaches the second metal stack (430) is connected to the first metal stack (420) at least one of face to face (see Fig. 4).
Regarding Claim 8, Liu ‘709 teaches the second metal stack (430) is connected to the first metal stack (420) by at least one of: hybrid bonding or direct bonding (see para. [0056]).
Regarding Claim 21, Liu ‘709 teaches a backside network in a passivation layer (444; [0060]) of at least one of the second circuit die (430).
Kaly ‘436 teaches a power delivery network (e.g. external source of power or internal battery; see col. 3 lines 20-25).
Regarding Claim 22, Liu ‘709 teaches the backside power delivery network provides power directly to a transistor layer of the at least one of the first circuit die or the second circuit die by at least one of backside vias (448; [0060]) (see Fig. 4).
Kaly ‘436 teaches a power delivery network (e.g. external source of power or internal battery; see col. 3 lines 20-25).
Regarding Claim 27, Liu ‘709 teaches one metal layer of the second metal stack (430) is utilized by both the first circuit die and the second circuit die (see Fig. 4).
Regarding Claim 28, Liu ‘709 teaches at least one redundant metal layer is eliminated from the first metal stack (420) (see Fig. 4).
Regarding Claim 30, Liu ‘709 teaches a circuit die (410); and the circuit die is coupled to an additional die (432) (see Fig. 4).
Kaly ‘436 teaches a temperature sensor (44) in a transistor layer of the circuit die (26) (see Fig. 2); and the temperature sensor (44) is positioned in planar proximity to at least one hot spot located in the additional circuit die.
Regarding Claim 31, Liu ‘709 teaches the circuit die is coupled to the additional die at least one of face to face.
Claims 23-25, 29 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Liu ‘709 and Kaly ‘436 as applied to claim 21 above, and further in view of Dubey (US 2020/0076424, hereinafter as Dube ‘424).
Regarding Claim 23, Liu ‘709 teaches a transistor layer of the first circuit die or the second circuit die (see Fig. 4).
Thus, Liu ‘709 and Kaly ‘436 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a transistor layer of the first circuit die or the second circuit die is configured to receive power directly from an additional die by direct bonding of a silicon body of the second circuit die to the additional die”.
Dube ‘424 teaches a transistor layer of the second circuit die (Fig. 1, (30); [0021]) is configured to receive power directly from an additional die (10; [0020]) by direct bonding of a silicon body (32; [0021]) of the second circuit die to the additional die (10).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Liu ‘709 and Kaly ‘436 by having a transistor layer of the first circuit die or the second circuit die is configured to receive power directly from an additional die by direct bonding of a silicon body of the second circuit die to the additional die in order to provide power gating for stacked die structures (see para. [0003]) as suggested by Dube ‘424.
Regarding Claim 24, Liu ‘709 teaches one or more connection elements (428; [0055]) provided to the second circuit die; wherein the first circuit die corresponds to a primary thermal source of the integrated circuit. It would obviously appear that the transistors (418; [0051]) are the primary thermal source of the integrated circuit.
Dube ‘424 teaches the one or more connection elements (36; [0022]) configure the second circuit die for connection to at least one of a package substrate or an additional die (10).
Regarding Claim 25, Dube ‘424 teaches one or more connection elements (36) include one routing layer in the second circuit die configured for connection to one of the packaging substrate additional die (10) using through silicon vias (TSV; see para. [0022]).
Regarding Claim 29, Dube ‘424 teaches an additional die (10; [0020]) connected to the second circuit die (30) (see Fig. 1).
Regarding Claim 32, Liu ‘709 teaches a circuit die having a metal stack (420), wherein the circuit die comprises: logic transistors (418); a hot spot; and wherein the circuit die is connected to an additional circuit die (432) (see Fig. 4); a backside network in a passivation layer (444; [0060]).
Kaly ‘436 teaches the additional circuit die comprising a temperature sensor (44) positioned in planar proximity to the hot spot.
Dube ‘424 teaches a backside power delivery network (16; [0031]) (see Fig. 1).
Claims 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Liu ‘709, Kaly ‘436 and Dube ‘424 as applied to claim 24 above, and further in view of Arabi (US 2006/0052970, hereinafter as Arab ‘970)
Regarding Claim 26, Liu ‘709, Kaly ‘436 and Dube ‘424 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the configuration of the second circuit die for connection configures the first circuit die for positioning closer than the second circuit die to a cooling solution of a semiconductor device containing the integrated circuit”.
Arab ‘970 teachers the configuration of the second circuit die (Fig. 1, (110); [0014]) for connection configures the first circuit die (140; [0015]) for positioning closer than the second circuit die to a cooling solution (130; [0016]) of a semiconductor device containing the integrated circuit.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Liu ‘709, Kaly ‘436 and Dube ‘424 by having the configuration of the second circuit die for connection configures the first circuit die for positioning closer than the second circuit die to a cooling solution of a semiconductor device containing the integrated circuit in order to ensure long-term product reliability (see para. [0004]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first/second circuit die that can be arranged in any order, thus the configuration of the second circuit die for connection configures the first circuit die for positioning closer than the second circuit die to a cooling solution of a semiconductor device involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement of the first and second circuit die for positioning closer than the second circuit die to a cooling solution of a semiconductor device when this improves the performance of the integrated circuit.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Thei et al. (US 2019/0363079 A1)
Teng et al. (US 2019/0131255 A1)
Kao et al. (US 2018/0025970 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893